TWI471985B - 晶片封裝體及其製作方法 - Google Patents

晶片封裝體及其製作方法 Download PDF

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TWI471985B
TWI471985B TW98127894A TW98127894A TWI471985B TW I471985 B TWI471985 B TW I471985B TW 98127894 A TW98127894 A TW 98127894A TW 98127894 A TW98127894 A TW 98127894A TW I471985 B TWI471985 B TW I471985B
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wafer
chip package
shielding layer
substrate
contacts
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Younghyo Eun
Dukman Kim
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Advanced Semiconductor Eng
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Description

晶片封裝體及其製作方法
本發明是有關於一種半導體裝置，且特別是有關於一種晶片封裝體。
對於大多數的電子裝置或封裝體而言，電磁干擾(electromagnetic interference,EMI)是一種共同但卻不受歡迎的干擾，其中所謂的干擾也許是中斷、阻礙、降低或限制電子裝置或整體電路的效能表現。
因此，於高頻裝置之封裝體需求不斷的提高之下，更好的電磁干擾屏蔽效能也被提升。在習知技術中，通常是利用額外屏蔽板或接地板，來作為提升電子裝置或封裝體之電磁干擾屏蔽的效能，但此卻會導致電子裝置或封裝體的厚度過厚且製程費用也較高。
本發明提供一種晶片封裝體的製作方法，可簡化製程。
本發明提供一種具有提升電磁干擾屏蔽效能的晶片封裝體。
本發明提出一種晶片封裝體，其包括一積層基板、至少一晶片、一第一遮蔽層、一封裝膠體以及一第二遮蔽層。積層基板上具有多個接點。晶片配置於積層基板上。第一遮蔽層配置於積層基板上，且暴露出接點與晶片。封裝膠體至少覆蓋晶片、接點、部份第一遮蔽層與部份積層基板。第二遮蔽層配置於封裝膠體上且覆蓋封裝膠體。
在本發明之一實施例中，上述之第一遮蔽層的材質與第二遮蔽層的材質皆包括焊料，且第一遮蔽層的材質與第二遮蔽層的材質可為相同材質，亦可為不同材質。
在本發明之一實施例中，上述之晶片透過多條焊線或多個凸塊而電性連接至晶片封裝體的基板。
本發明提供一種晶片封裝體的製作方法。首先，提供一基板。基板上具有多個接點與一晶片貼附區域。接著，形成一第一遮蔽層於基板的一上表面上，其中第一遮蔽層暴露出接點與晶片貼附區域。配置至少一晶片於基板的晶片貼附區域上，其中晶片電性連接至基板。之後，形成一封裝膠體於基板上，以包覆晶片、這些接點與至少一部份第一遮蔽層。最後，形成一第二遮蔽層於封裝膠體上。
在本發明之一實施例中，上述之形成第一遮蔽層的方法包括網版印刷法(screen printing)，形成第二遮蔽層的方法包括網版印刷或電鍍法(printing)。
基於上述，第一遮蔽層配置於基板上的作用可視為晶片封裝體底部防電磁輻射的電磁干擾屏蔽。在本發明之晶片封裝體不需額外金屬板，只需透過第一遮蔽層與第二遮蔽層即可達成完整之電磁干擾屏蔽的效果。因此，第一遮蔽層與第二遮蔽層可提高晶片封裝體的電磁干擾屏蔽效果，使晶片封裝體具有較佳的電磁干擾屏蔽效能。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本發明之一實施例之一種晶片封裝體的剖面示意圖。請參考圖1，在本實施例中，晶片封裝體100包括一基板102、至少一晶片104、多個接點106、一第一遮蔽層110、多條焊線120、一封裝膠體130以及一第二遮蔽層140。基板102可為一積層基板，其例如是一兩層積層的印刷電路板基板。晶片104可為一半導體晶片，其例如是一射頻(Radio-Frequency,RF)晶片。接點106的材質例如是銅、鋁或銅鋁合金。第一遮蔽層110與第二遮蔽層140的材質皆可包括一焊料(solder material)，且第一遮蔽層110與第二遮蔽層140的材質可以相同也可以不同。接點106配置於基板102的上表面且環繞晶片座108。第一遮蔽層110配置於基板102的上表面，且暴露出接點106與晶片座108。晶片104配置於晶片座108上，且透過焊線120電性連接至基板102的接點106。封裝膠體130包覆晶片104、接點106、焊線120、部份基板102與部份第一遮蔽層110。此外，第二遮蔽層140配置於封裝膠體130上，且覆蓋封裝膠體130的四個側壁與上表面。另外，第二遮蔽層140覆蓋基板102的一接地孔105，且第二遮蔽層140電性連接至接地孔105而接地。在此必須注意的是，如果封裝膠體130完全地覆蓋晶片140與基板102，則第一遮蔽層110覆蓋接地孔105而接地。
在本實施例之晶片封裝體100中，第一遮蔽層110配置於基板102上的作用可視為一電磁干擾屏蔽(EMI shield)，特別是保護晶片封裝體100免於底部輻射源的電磁干擾輻射。因此，相較於習知晶片封裝體而言，本實施例之晶片封裝體100不需包含一額外金屬板，且可提供一厚度較薄的封裝體。
第一遮蔽層110與第二遮蔽層140可提升晶片封裝體100電磁干擾屏蔽的效能。特別是，第一遮蔽層110覆蓋基板102的上表面，可幫助晶片封裝體100的底部免於電磁干擾輻射。第二遮蔽層140覆蓋晶片封裝體100的上部份(意即封裝膠體130的暴露表面)且第一遮蔽層110保護晶片封裝體100的底部免受電磁干擾輻射，可有效加強晶片封裝體100的電磁干擾屏蔽效能。
在本實施例中，封裝膠體130的邊緣可與接點106的邊緣或接地孔105的邊緣對齊。此外，本實施例之晶片封裝體100更包括多個位於基板102之背表面的凸塊(未繪示)，其可作為與外界電性連接的接點。理論上，晶片封裝體100可以是一堆疊式的上封裝或封裝結構的封裝體或一部份系統級封裝(system-in-package)結構。另外，在本實施例中，除了主動元件之外，晶片封裝體100還包括被動元件，例如是電阻、電容與電感。
圖2A至圖2E繪示本發明之一實施例之一種晶片封裝體的製作方法。在此必須說明的是，為了方便說明起見，圖2A至圖2B繪示上視圖，而2C至圖2E繪示剖面示意圖。請先參考圖2A，依照本實施例的晶片封裝體的製作方法，首先，提供一基板102，其中基板102上具有至少一晶片座108與多個接點106。這些接點106環繞晶片座108配置。
接著，請參考圖2B，形成一第一遮蔽層110於基板102的一上表面102a上。第一遮蔽層110的材質例如是一焊料。形成第一遮蔽層110的方法例如是網版印刷法。第一遮蔽層110的多個第一開口112暴露出底部相對應的接點106，同時第一遮蔽層110的一第二開口114暴露出晶片座108。一般來說，開口的尺寸大於其所對應暴露出的元件，可以防止發生短路的可能性。換言之，第一遮蔽層110應該完全地隔開接點106以防止發生短路。此外，於其他實施例中，第二開口114的尺寸可能大約等於晶片座108的尺寸。
請參考圖2C，至少一晶片104配置於基板102的晶片座108上。接著，形成多條焊線120於基板102與晶片104之間，使晶片104透過焊線120電性連接至基板102的接點106。
請參考圖2D，透過一封裝膠體130而完成一封膠製程，其中封裝膠體130配置於基板102上且包覆晶片104、接點106與至少一部份的第一遮蔽層110。
請參考圖2E，形成一第二遮蔽層140於封裝膠體130的暴露表面上。第二遮蔽層140的材質例如是一焊料。形成第二遮蔽層140的方法例如是網版印刷或電鍍法。在形成封裝膠體130之後與形成第二遮蔽層140之前，可任意地進行一半切割製程(a half cutting process)。
最後，進行一單體化製程(singulation process)以形成多個獨立的晶片封裝體100。
在本實施例中，晶片封裝體100之晶片104是透過打線接合技術而電性連接至基板102上。當然，於其他實施例中，晶片封裝體100也可包括一晶片104透過覆晶接合技術而電性連接至基板102上。請參考圖3，圖3之晶片封裝體300與圖2E之晶片封裝體100相似，其不同之處在於：晶片封裝體300包括一晶片304，且此晶片304透過多個位於晶片304與接點306之間的凸塊320，而電性連接至基板302的接點306。第一遮蔽層310配置於基板302的上表面且暴露出覆晶區域(flip-chip area)。也就是說，第一遮蔽層310完全隔離覆晶區域的周圍，以防止第一遮蔽層310與接點306或凸塊320發生短路。
封裝膠體330包覆晶片304、接點306、凸塊320、部份基板302與第一遮蔽層310。此外，第二遮蔽層340配置於封裝膠體330上，且覆蓋封裝膠體330的四個側表面與上表面。另外，第二遮蔽層340覆蓋基板302的多個接地孔305，且第二遮蔽層340電性連接至接地孔305而接地。在此必須注意的是，如果封裝膠體330完全包覆晶片304與基板302，則第一遮蔽層310會覆蓋接地孔305而接地。
綜上所述，由於第一遮蔽層與第二遮蔽層可有效地遮蔽外界電磁干擾輻射，因此可提高本發明之晶片封裝體的電磁干擾屏蔽的效能。本發明之晶片封裝體的製作方法，是改用一沒有額外接底板的薄化基層基板，使晶片封裝體的厚度與體積可以更為小型化。因此，這樣的設計適合具有高頻裝置的封裝，特別是一射頻裝置。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、300．．．晶片封裝體
102、302．．．基板
102a．．．上表面
104、304．．．晶片
105、305．．．接地孔
106、306．．．接點
108．．．晶片座
110、310．．．第一遮蔽層
112．．．第一開口
114．．．第二開口
120．．．焊線
130、330．．．封裝膠體
140、340．．．第二遮蔽層
320．．．凸塊
圖1為本發明之一實施例之一種晶片封裝體的剖面示意圖。
圖2A至圖2E繪示本發明之一實施例之一種晶片封裝體的製作方法。
圖3為本發明之另一實施例之一種晶片封裝體的剖面示意圖。
100．．．晶片封裝體
102．．．基板
104．．．晶片
105．．．接地孔
106．．．接點
108．．．晶片座
110．．．第一遮蔽層
120．．．焊線
130．．．封裝膠體
140．．．第二遮蔽層

Claims (16)

  1. 一種晶片封裝體，包括：一積層基板，該基層基板上具有多個接點；至少一晶片，配置於該積層基板上；一第一遮蔽層，配置於該積層基板上，且具有多個第一開口與至少一第二開口，該些第一開口暴露出暴露出該些接點，該第二開口暴露出該晶片；一封裝膠體，至少包覆該晶片、該些接點、部份該第一遮蔽層與部份該積層基板；以及一第二遮蔽層，配置於該封裝膠體上且覆蓋該封裝膠體。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該些第一開口的尺寸大於其所對應暴露出之該些接點的尺寸。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該晶片配置於該積層基板的一晶片座上，且該晶片透過多條焊線電性連接至該些接點。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該晶片透過多個配置於該晶片下方的凸塊而電性連接至該些接點。
  5. 如申請專利範圍第3項所述之晶片封裝體，其中該第二開口的尺寸不小於該晶片座的尺寸。
  6. 如申請專利範圍第4項所述之晶片封裝體，其中該第二開口的尺寸大於一排列該些凸塊區域的尺寸。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該晶片為一射頻晶片。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該第二遮蔽層電性連接至該積層基板的至少一接地孔。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該第一遮蔽層的材質包括一焊料。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該第二遮蔽層的材質包括一焊料。
  11. 一種晶片封裝體的製作方法，包括：提供一基板，該基板上具有多個接點與一晶片貼附區域；形成一第一遮蔽層於該基板的一上表面上，其中該第一遮蔽層具有多個第一開口與至少一第二開口，該些第一開口暴露出暴露出該接點，該第二開口暴露出該晶片貼附區域；配置至少一晶片於該基板的該晶片貼附區域上，其中該晶片電性連接至該基板；形成一封裝膠體於該基板上，以包覆該晶片、該些接點與至少一部份該第一遮蔽層；以及形成一第二遮蔽層於該封裝膠體上。
  12. 如申請專利範圍第11項所述之晶片封裝體的製作方法，其中形成該第一遮蔽層的方法包括網版印刷法。
  13. 如申請專利範圍第11項所述之晶片封裝體的製作方法，其中形成該第二遮蔽層的方法包括網版印刷或電 鍍法。
  14. 如申請專利範圍第11項所述之晶片封裝體的製作方法，其中形成該第二遮蔽層以覆蓋該封裝膠體的一暴露表面與該基板上的至少一接地孔。
  15. 如申請專利範圍第11項所述之晶片封裝體的製作方法，其中該晶片貼附區域包括一晶片座，且該晶片透過打線接合而電性連接至該基板。
  16. 如申請專利範圍第11項所述之晶片封裝體的製作方法，其中該晶片透過覆晶接合而電性連接至該基板。
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