TW201351599A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TW201351599A
TW201351599A TW101134232A TW101134232A TW201351599A TW 201351599 A TW201351599 A TW 201351599A TW 101134232 A TW101134232 A TW 101134232A TW 101134232 A TW101134232 A TW 101134232A TW 201351599 A TW201351599 A TW 201351599A
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Taiwan
Prior art keywords
electrical contact
semiconductor package
semiconductor
substrate
conductive
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Application number
TW101134232A
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English (en)
Inventor
林建成
許聰賢
朱恆正
楊超雅
鄭志銘
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101134232A priority Critical patent/TW201351599A/zh
Priority to CN2012103842197A priority patent/CN103456703A/zh
Priority to US13/660,277 priority patent/US8963299B2/en
Publication of TW201351599A publication Critical patent/TW201351599A/zh

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Abstract

一種半導體封裝件，係包括：具有電性接觸墊之基板、設於該基板上之半導體元件、形成於該半導體元件頂面及側面上且延伸至該電性接觸墊上之導電膠、以及設於該導電膠上之電子元件。藉由該導電膠與電性接觸墊作為屏蔽結構，使該半導體元件與電子元件間之電磁不會相互干擾。本發明復提供該半導體封裝件之製法。

Description

半導體封裝件及其製法
本發明係關於一種半導體封裝件，更詳言之，本發明係為一種防電磁干擾之半導體封裝件及其製法。
隨著電子產品輕薄短小及系統整合的趨勢，遂將一個或多個晶片、被動元件等不同的電子元件整合在同一個封裝件中以形成系統級封裝(System in package；SIP)，但鄰近之電子元件間容易互相電磁干擾(Electromagnetic Interference,EMI)，且封裝件中的電子元件的積集度日益增加，使得各該電子元件之間的相對位置越來越靠近，故各該電子元件之間的EMI問題更顯重要。
第7049682號美國專利係揭露一種半導體封裝件1a，如第1A圖所示，於一基板10a上排設且電性連接複數電子元件11a,14a，再以封裝膠體15a包覆各該電子元件11a,14a以形成複數封裝體12a，再以蓋體13a分別蓋設於各該封裝體12a外，以防止各該電子元件11a,14a之間發生EMI現象。
然而，利用並排式(side by side)設置複數電子元件11a,14a，當該些電子元件11a,14a之數目增加時，該基板20之使用面積會隨之增加，因而造成封裝成本過高及整體封裝結構尺寸過大等缺點。
再者，以蓋體13a作為屏蔽結構之成本極高，不符合經濟效益。
為解決上述問題，係使用垂直式之堆疊方法增加元件之數量，以節省基板之使用空間。如第1B圖所示，係第8049119號美國專利所揭露之半導體封裝件1b，其將一晶片11b覆晶結合於一內部具有第一屏蔽層100之基板10b上，且堆疊一電子元件14b於該晶片11b，該電子元件14b之底部係以濺鍍方式形成一第二屏蔽層140，並藉由導電膠13b電性連接該第一與第二屏蔽層100,140，以藉由第一與第二屏蔽層100,140防止該晶片11b與外部電子裝置發生EMI現象，再進行模壓(molding)製程，使封裝膠體15b包覆該電子元件14b，且該封裝膠體15b形成有一開口150，以令該電子元件14b之部分表面外露於該開口150，俾供接置其他電子元件。
惟，習知半導體封裝件1b中，利用濺鍍方式形成該第二屏蔽層140，其生產成本仍過高。
再者，該封裝膠體15b具有該開口150，故於模壓製程時，模具必須針對不同尺寸的外形而設計，以形成所需之開口150大小，因而同一模具無法泛用於不同尺寸的電子元件14b，以致於生產成本提高。
然而，如何克服習知技術之種種問題，實為一重要課題。
為解決上述習知技術之種種問題，本發明遂揭露一種半導體封裝件，係包括：一基板，係具有複數第一電性接觸墊與至少一第二電性接觸墊；至少一半導體元件，係設 於該基板上且電性連接該些第一電性接觸墊；以及導電膠，係形成於該半導體元件上且延伸至該基板之第二電性接觸墊上，以令該導電膠與該第二電性接觸墊構成屏蔽結構。
前述之半導體封裝件中，該導電膠係沿該半導體元件之側面延伸至該第二電性接觸墊上。
本發明復提供一種半導體封裝件之製法，係包括：提供一具有複數第一電性接觸墊與至少一第二電性接觸墊之基板；設置至少一半導體元件於該基板上，且該半導體元件電性連接該些第一電性接觸墊；以及形成導電膠於該半導體元件上，以覆蓋該半導體元件，且該導電膠由該半導體元件延伸至該基板之第二電性接觸墊上，以令該導電膠與該第二電性接觸墊構成屏蔽結構。
前述之製法中，形成該導電膠之方式係為點膠製程、網版塗佈製程、轉印製程或膜貼製程。
前述之半導體封裝件及其製法，該基板中復具有導電孔，以電性連接該第二電性接觸墊。該導電孔係為接地孔。
前述之半導體封裝件及其製法，該第二電性接觸墊係為接地墊。
前述之半導體封裝件及其製法，該半導體元件係藉由複數導電凸塊電性連接該些第一電性接觸墊，且復包括形成底膠於該半導體元件與該基板之間，以包覆該些導電凸塊。
前述之半導體封裝件及其製法，該基板復具有複數第 三電性接觸墊，且復包括設置至少一電子元件於該導電膠上，且該電子元件電性連接該些第三電性接觸墊；該電子元件係為封裝體或晶片。又包括形成封裝膠體於該基板上，以包覆該半導體元件、電子元件與該導電膠。
另外，前述之半導體封裝件及其製法，復包括形成底膠於該半導體元件與該基板之間，使該導電膠復形成於該底膠上。
由上可知，本發明半導體封裝件及其製法，係藉由該半導體元件的表面形成導電膠，且將導電膠連接到第二電性接觸墊上，使該導電膠具有接地效果，故於導電膠上堆疊電子元件，可避免該半導體元件與電子元件之電磁相互干擾。
再者，形成該導電膠之材質之方式相當簡單，故相較於習知濺鍍方式或製作蓋體之方式，本發明能有效降低生產成本。
又，該封裝膠體無需形成開口，故於模壓製程時，模具不須考量開口大小，因而同一模具能泛用於不同尺寸的電子元件，以達到降低生產成本之目的。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝 之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“側面”、“第一”、“第二”、“第三”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
以下即配合第2A至2C圖詳細說明本發明之半導體封裝件2之製法。
如第2A圖所示，提供一基板20，該基板20具有複數第一電性接觸墊201、複數第二電性接觸墊202與複數導電孔204，且該些導電孔204電性連接該些第二電性接觸墊202。
於本實施例中，該第二電性接觸墊202係為接地墊，且該導電孔204係為接地孔。
再者，於其它實施例中，可依需求，僅形成一個第二電性接觸墊202。
又，該基板20中復形成有其它功能之導電孔或線路(圖略)。
另外，有關基板20及其內部結構之種類繁多，並不限於上述，特此述明。
如第2B圖所示，設置一半導體元件21於該基板20 上，且該半導體元件21藉由複數導電凸塊210電性連接該些第一電性接觸墊201。
接著，形成底膠22於該半導體元件21與該基板20之間，以包覆該些導電凸塊210。
於本實施例中，該半導體元件21係為半導體晶片，且具有相對之作用面21a與非作用面21b及側面21c，該作用面21a係用以結合該些導電凸塊210，以令該半導體元件21接置於該基板20上。
如第2C圖所示，形成導電膠23於該半導體元件21之非作用面21b與側面21c上以覆蓋該半導體元件21，且該導電膠23由該半導體元件21之側面21c沿該底膠22之側面22a延伸至該基板20之第二電性接觸墊202上，以令該導電膠23與該第二電性接觸墊202構成屏蔽結構S。
於本實施例中，該導電膠23係為導電膠，且形成該導電膠23之方式係為點膠製程、網版塗佈(screen printing)製程、轉印(transfer printing)製程或膜貼(film type adhesive layer)製程。
第2D至2E圖係為本發明之半導體封裝件3之製法之另一實施例。本實施例與上述實施例之相同處不再贅述。
如第2D圖所示，該基板20復具有複數第三電性接觸墊203，且該第二電性接觸墊202的位置係不干涉該第三電性接觸墊203之位置。
接著，經上述第2A至2C圖之製程後，設置一電子元件24於該導電膠23上，且該電子元件24藉由複數銲線 240電性連接該些第三電性接觸墊203。
於本實施例中，該電子元件24係為封裝體或晶片。
如第2E圖所示，進行模壓製程，以形成封裝膠體25於該基板20上，使該封裝膠體25包覆該電子元件24、銲線240與該導電膠23，以完成另一半導體封裝件3之製作。
本發明之製法中，係藉由該半導體元件21的表面形成該導電膠23以作為屏蔽層，再於導電膠23上堆疊電子元件24，以避免該半導體元件21與電子元件24間之電磁相互干擾，故使該半導體元件21與電子元件24可保持應有的功效。
再者，於單一封裝件內進行元件堆疊，故能節省該基板20之使用空間。
又，該封裝膠體25無需形成開口，故於模壓製程時，模具不須考量開口大小，亦即模具不需針對不同尺寸的外形作設計。因此，同一模具能泛用於不同尺寸的基板20、電子元件24或晶片，故本發明之製法有效降低生產成本。
另外，形成該導電膠23之材質係為膠體，而形成膠體之方式係相當簡單，故相較於習知濺鍍方式或製作蓋體之方式，本發明能有效降低生產成本。
本發明提供一種半導體封裝件3，其包括：一基板20、一半導體元件21、底膠22、導電膠23、一電子元件24以及封裝膠體25。
所述之基板20係具有複數第一電性接觸墊201、第二電性接觸墊202、第三電性接觸墊203與導電孔204，該第 二電性接觸墊202係為接地墊，且該導電孔204係為接地孔並電性連接該第二電性接觸墊202。
所述之半導體元件21係設於該基板20上，且藉由複數導電凸塊210電性連接該些第一電性接觸墊201。
所述之底膠22係形成於該半導體元件21與該基板20之間，以包覆該些導電凸塊210。
所述之導電膠23係為導電膠，其形成於該半導體元件21上且沿該底膠22之側面22a延伸至該第二電性接觸墊202上，以令該導電膠23與該第二電性接觸墊202構成屏蔽結構S。
所述之電子元件24係為封裝體或晶片，其設於該導電膠23上，且藉由複數銲線240電性連接該些第三電性接觸墊203。
所述之封裝膠體25係形成於該基板20上，以包覆該電子元件24、該些銲線240與該導電膠23。
綜上所述，本發明之半導體封裝件及其製法中，主要藉由導電膠與第二電性接觸墊作為屏蔽結構，使該半導體元件與電子元件間之電磁不會相互干擾。
再者，形成該導電膠之方式相當簡單，故能有效降低生產成本。
又，該封裝膠體無需形成開口，故於模壓製程時，模具不須考量開口大小，因而同一模具能泛用於不同尺寸的基板或晶片，以達到降低生產成本之目的。
上述該些實施樣態僅例示性說明本發明之功效，而非 用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1a、1b、2、3‧‧‧半導體封裝件
10a、10b、20‧‧‧基板
100‧‧‧第一屏蔽層
11a、14a、14b、24‧‧‧電子元件
11b‧‧‧晶片
12a‧‧‧封裝體
13a‧‧‧蓋體
13b‧‧‧導電膠
140‧‧‧第二屏蔽層
15a、15b、25‧‧‧封裝膠體
150‧‧‧開口
201‧‧‧第一電性接觸墊
202‧‧‧第二電性接觸墊
203‧‧‧第三電性接觸墊
204‧‧‧導電孔
21‧‧‧半導體元件
21a‧‧‧作用面
21b‧‧‧非作用面
21c、22a‧‧‧側面
210‧‧‧導電凸塊
22‧‧‧底膠
23‧‧‧導電膠
240‧‧‧銲線
S‧‧‧屏蔽結構
第1A圖係顯示第7049682號美國專利之半導體封裝件之剖面示意圖；第1B圖係顯示第8049119號美國專利之半導體封裝件之剖面示意圖；第2A至2C圖係為本發明半導體封裝件之製法之剖面示意圖；以及第2D至2E圖係為本發明半導體封裝件之製法之另一實施例的剖面示意圖。
3‧‧‧半導體封裝件
20‧‧‧基板
201‧‧‧第一電性接觸墊
202‧‧‧第二電性接觸墊
203‧‧‧第三電性接觸墊
21‧‧‧半導體元件
21c‧‧‧側面
22‧‧‧底膠
23‧‧‧導電膠
24‧‧‧電子元件
25‧‧‧封裝膠體
S‧‧‧屏蔽結構

Claims (22)

  1. 一種半導體封裝件，係包括：一基板，係具有複數第一電性接觸墊與至少一第二電性接觸墊；至少一半導體元件，係設於該基板上且電性連接該些第一電性接觸墊；以及導電膠，係形成於該半導體元件上且延伸至該基板之第二電性接觸墊上，以令該導電膠與該第二電性接觸墊構成屏蔽結構。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該基板中復具有電性連接該第二電性接觸墊之導電孔。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，該導電孔係為接地孔。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該第二電性接觸墊係為接地墊。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件係藉由複數導電凸塊電性連接該些第一電性接觸墊。
  6. 如申請專利範圍第5項所述之半導體封裝件，復包括底膠，係形成於該半導體元件與該基板之間，以包覆該些導電凸塊。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電膠係沿該半導體元件之側面延伸至該第二電性 接觸墊上。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該基板復具有複數第三電性接觸墊，且該半導體封裝件復包括至少一電子元件，係設於該導電膠上且電性連接該些第三電性接觸墊。
  9. 如申請專利範圍第8項所述之半導體封裝件，其中，該電子元件係為封裝體或晶片。
  10. 如申請專利範圍第8項所述之半導體封裝件，復包括封裝膠體，係形成於該基板上，以包覆該半導體元件、電子元件與該導電膠。
  11. 如申請專利範圍第1項所述之半導體封裝件，復包括底膠，係形成於該半導體元件與該基板之間，令該導電膠復形成於該底膠上。
  12. 一種半導體封裝件之製法，係包括：提供一具有複數第一電性接觸墊與至少一第二電性接觸墊之基板；設置至少一半導體元件於該基板上，且該半導體元件電性連接該些第一電性接觸墊；以及形成導電膠於該半導體元件上，以覆蓋該半導體元件，且該導電膠由該半導體元件延伸至該基板之第二電性接觸墊上，以令該導電膠與該第二電性接觸墊構成屏蔽結構。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該基板中復具有電性連接該第二電性接觸墊之 導電孔。
  14. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該導電孔係為接地孔。
  15. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該第二電性接觸墊係為接地墊。
  16. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該半導體元件係藉由複數導電凸塊電性連接該些第一電性接觸墊。
  17. 如申請專利範圍第16項所述之半導體封裝件之製法，復包括形成底膠於該半導體元件與該基板之間，以包覆該些導電凸塊。
  18. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，形成該導電膠之方式係為點膠製程、網版塗佈製程、轉印製程或膜貼製程。
  19. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該基板復具有複數第三電性接觸墊，且該製法復包括設置至少一電子元件於該導電膠上，且該電子元件電性連接該些第三電性接觸墊。
  20. 如申請專利範圍第19項所述之半導體封裝件之製法，其中，該電子元件係為封裝體或晶片。
  21. 如申請專利範圍第19項所述之半導體封裝件之製法，復包括形成封裝膠體於該基板上，以包覆該半導體元件、電子元件與該導電膠。
  22. 如申請專利範圍第12項所述之半導體封裝件之製法， 復包括形成底膠於該半導體元件與該基板之間，使該導電膠復形成於該底膠上。
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