TWI767243B - 電子封裝件 - Google Patents

電子封裝件 Download PDF

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TWI767243B
TWI767243B TW109118096A TW109118096A TWI767243B TW I767243 B TWI767243 B TW I767243B TW 109118096 A TW109118096 A TW 109118096A TW 109118096 A TW109118096 A TW 109118096A TW I767243 B TWI767243 B TW I767243B
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Taiwan
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electronic package
carrier
wire
shielding
shielding structure
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TW109118096A
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TW202145497A (zh
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邱志賢
蔡文榮
葉育瑋
蔡宗賢
石啟良
楊勝明
廖彬宏
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矽品精密工業股份有限公司
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Priority to TW109118096A priority Critical patent/TWI767243B/zh
Priority to CN202010512317.9A priority patent/CN113745199A/zh
Priority to US16/931,180 priority patent/US11532568B2/en
Publication of TW202145497A publication Critical patent/TW202145497A/zh
Application granted granted Critical
Publication of TWI767243B publication Critical patent/TWI767243B/zh
Priority to US17/989,554 priority patent/US20230082767A1/en

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Abstract

一種電子封裝件，係以複數銲線作為屏蔽結構，該銲線銲係接於一承載有電子元件之承載件上，俾利用該銲線不會受溫度、濕度及其它環境因素的影響，避免該屏蔽結構從該承載件上剝離或脫落之問題。

Description

電子封裝件
本發明係有關一種半導體封裝製程，尤指一種具屏蔽結構之電子封裝件。
隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的。
為符合電子產品輕薄短小的趨勢，使得其上封裝件的設置密度增加，惟此將導致封裝件間容易產生電磁干擾(electromagnetic interference，EMI)之現象。
為解決各電子封裝件之間的電磁干擾的問題，通常會於封裝件之封裝過程中，於外部設置屏蔽件，以避免各封裝件間的電磁干擾。
如第1圖所示，習知半導體封裝件1係於一封裝基板10上設置至少一半導體元件11,11’，再以封裝膠體13包覆該半導體元件11,11’，之後，藉由導電膠120將一屏蔽罩12接合於該封裝基板10上，以令該屏蔽罩12遮蓋該半導體元件11,11’。
惟，習知半導體封裝件1中，該導電膠120之黏著性會受到溫度、濕度及其它環境因素的影響而降低，致使該屏蔽罩12容易從該封裝基板10上剝離或脫落。
再者，當該屏蔽罩12固定至該封裝膠體13上時，該屏蔽罩12的尺寸與形狀需與該封裝膠體13的尺寸與形狀相互配合，因而兩者的配合度需極為精密，使該屏蔽罩12與該封裝膠體13於製作上需具備一定的相對位置之準確度，導致製作成本提高且耗費製程時間。
又，該屏蔽罩12與該封裝膠體13於尺寸與形狀需相互配合，故若配置不同尺寸與形狀的半導體元件11,11’時，需搭配不同尺寸與形狀的屏蔽罩，導致需特製模具，以製作不同尺寸與形狀的封裝膠體13，因而增加製作成本與時間。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件，係包括：承載件；電子元件，係設於該承載件上；以及屏蔽結構，係包含複數銲線部，且各該銲線部係以連續打線方式立設於該承載件上，其中，該銲線部係呈弧形線狀，其定義有第一線段、第二線段及連結該第一線段與第二線段之彎折段。
前述之電子封裝件中，該第一線段之長度與該第二線段之長度係不相等。
前述之電子封裝件中，該銲線部係為單一線段。
前述之電子封裝件中，該屏蔽結構係形成一封閉迴路。
前述之電子封裝件中，復包括包覆該電子元件與該屏蔽結構之封裝層。例如，該屏蔽結構係局部外露於該封裝層。又包括形成於該封裝層上之屏蔽層。進一步，該屏蔽層係電性連接該承載件；或者，該屏蔽層係接觸該屏蔽結構；亦或，該屏蔽層係未接觸該屏蔽結構。
前述之電子封裝件中，該複數銲線部之間係全部連續打線，使該屏蔽結構呈一體式。
前述之電子封裝件中，該複數銲線部之其中相鄰兩者之間係中斷連續打線，使該屏蔽結構呈不連續之多段式。
本發明亦提供一種電子封裝件，係包括：承載件；電子元件，係設於該承載件上；以及屏蔽結構，係包含複數銲線部，且各該銲線部係以連續打線方式立設於該承載件上，其中，該銲線部係具有第一銲線及第二銲線，該第一銲線係呈弧形線狀且其一端對應該第二銲線配置，同時該第二銲線係為單一線段且其立設於該承載件上。
前述之電子封裝件中，該第一銲線相對該承載件之高度係低於該第二銲線相對該承載件之高度。
前述之電子封裝件中，該第一銲線係定義有第一線段、第二線段及連結該第一線段與第二線段之彎折段。
前述之電子封裝件中，該第二銲線係以其一端處結合至該第一銲線所接置之處。
前述之電子封裝件中，復包括包覆該電子元件與該屏蔽結構之封裝層。例如，該屏蔽結構係局部外露於該封裝層。又包括形成於該封 裝層上之屏蔽層。例如，該屏蔽層係電性連接該承載件；或者，該屏蔽層係接觸該屏蔽結構；亦或，該屏蔽層係未接觸該屏蔽結構。
由上可知，本發明之電子封裝件中，主要藉由該銲線部作為屏蔽結構，以銲接於該承載件上，而不會受溫度、濕度及其它環境因素的影響，故相較於習知技術，本發明之電子封裝件可有效避免該屏蔽結構從該承載件上剝離或脫落之問題。
1:半導體封裝件
10:封裝基板
11,11’:半導體元件
12:屏蔽罩
120:導電膠
13:封裝膠體
2,2’,3,4,5,6:電子封裝件
20:承載件
20a:第一側
20b:第二側
20c:側面
200:線路層
201:電性接觸墊
202,202’,302,402:功能墊
203:接地部
21:電子元件
21a:作用面
21b:非作用面
210:電極墊
211:導線
22,22’,32,42,52:屏蔽結構
220,220’,320,420,520:銲線部
220a:球體
220b:截斷處
220c,521c:彎折段
221,321,521a:第一線段
222,322,521b:第二線段
23:封裝層
23a:第一表面
23b:第二表面
24:屏蔽層
28:膠材
521:第一銲線
522:第二銲線
A:置晶區
B:外圍區
H,h:高度
第1圖係為習知半導體封裝件的剖視示意圖。
第2圖係為本發明之電子封裝件之第一實施例之上視示意圖。
第2’圖係為本發明之電子封裝件之第一實施例之其中一視角之剖視示意圖。
第2A圖係為第2圖之屏蔽結構之製作方式之側面示意圖。
第2B圖係為第2A圖之另一態樣示意圖。
第3A圖係為本發明之電子封裝件之第一實施例之另一視角之剖視示意圖。
第3A’圖係為第3A圖之另一態樣之剖視示意圖。
第3B圖係為本發明之電子封裝件之第二實施例之剖視示意圖。
第3C圖係為本發明之電子封裝件之第三實施例之剖視示意圖。
第4A圖係為本發明之電子封裝件之第四實施例之局部上視示意圖。
第4B圖係為第4A圖之局部立體示意圖。
第4C及4C’圖係為第4A圖之不同態樣之剖視示意圖。
第5圖係為本發明之電子封裝件之第五實施例之剖視示意圖。
第6圖係為本發明之電子封裝件之第六實施例之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、“上”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2圖係為本發明之電子封裝件2之第一實施例之上視示意圖。如第2圖所示，所述之電子封裝件2係包括一承載件20、至少一設於該承載件20上之電子元件21、以及一設於該承載件20上並遮蔽該電子元件21四周之屏蔽結構22。
於本實施例中，如第2’圖所示，該電子封裝件2復包括一包覆該電子元件21與該屏蔽結構22之封裝層23、以及一設於該封裝層23上之屏蔽層24。
所述之承載件20係具有相對之第一側20a與第二側20b，且該第一側20a上係定義有一置晶區A及圍繞該置晶區A之外圍區B。
於本實施例中，該承載件20係為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，該線路結構係於介電材上形成線路層200，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且介電材係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等。應可理解地，該承載件20亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(lead-frame)或矽中介板(silicon interposer)等載件，並不限於上述。
再者，該線路層200係包含有複數配置於該置晶區A上之電性接觸墊201及至少一可依需求配置於該外圍區B上之功能墊202。
另外，第2圖所示之X-X剖面線係呈現第2’圖所示之放大剖面結構，且第2圖所示之Y-Y剖面線係呈現第3A圖所示之局部放大剖面結構。
所述之電子元件21係設於該承載件20之第一側20a之置晶區A上。
於本實施例中，該電子元件21係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件21係為半導體晶片，其具有作用面21a與相對該作用面21a之非作用面21b，該電子元件21以其非作用面21b藉由膠材28設於該承載件20之第一側20a上，且該作用面21a上具有複數電極墊210，以藉由複數導線211以打線方式電性連接該電極墊210與電性接觸墊201；或者，該電子元件21可藉由複數導電凸塊(圖略)以覆晶方式電性連接該承載件20之電性接觸墊201，並以底膠(圖略)包覆該些導電凸塊；亦或，該電子元件21之電極墊210可直接接觸該電性接觸墊201以電性連接該線路層200。然而，有關該電子元件21電性連接該承載件20之方式不限於上述。
所述之屏蔽結構22係包含複數銲線部220(如第3A圖所示)，且該複數銲線部220係立設於該承載件20之第一側20a之外圍區B上。
於本實施例中，該銲線部220係接觸結合至該承載件20之功能墊202上，使該銲線部220電性連接該承載件20。例如，該銲線部220係為打線方式所用之金屬線材，且該銲線部220之兩端分別結合至該承載件20之兩個功能墊202上，如第3A圖所示。
再者，如第3A圖所示，該屏蔽結構22係以連續打線方式形成每一銲線部220，如弧形線狀或封閉弧圈狀，且單一銲線部220係定義有第一線段221、第二線段222及連結該第一線段221與第二線段222之彎折段220c。例如，該第一線段221與第二線段222之長度係不相等。具體地，該第一線段221之長度係短於該第二線段222之長度。
又，該屏蔽結構22之連續打線方式係藉由打線機台(圖略)之銲嘴(圖略)將一金線從一功能墊202拉到另一功能墊202上並予以銲接(Stitch Bond)且截斷，如第2A圖所示，再令該銲嘴以截斷處220b牽引出另 一金線。或者，如第2B圖所示，於截斷後，該銲嘴先於截斷處220b形成一球體220a，再牽引另一金線。
另外，該複數銲線部220之間可依需求全部連續打線，使該屏蔽結構22呈一體式(如第3A圖所示)，亦可如第3A’圖所示，將任相鄰兩銲線部220’之間中斷連續打線，使該屏蔽結構22’呈不連續之多段式。
所述之封裝層23係設於該承載件20之第一側20a上以包覆該電子元件21與該屏蔽結構22。
於本實施例中，該封裝層23之形成材質係為絕緣材，例如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝層(molding compound)。例如，該封裝層23之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該承載件20之第一側20a上。
再者，該封裝層23係定義有相對之第一表面23a與第二表面23b，且該封裝層23係以其第一表面23a係結合於該承載件20之第一側20a上。因此，該銲線部220可依需求外露於該封裝層23之第二表面23b，如第3A圖所示。例如，可藉由移除製程，移除該封裝層23之第二表面23b之部分材質，使該銲線部220之彎折段220c凸出該封裝層23之第二表面23b，以令該彎折段220c外露於該封裝層23之第二表面23b。或者，該銲線部220亦可未外露於該封裝層23，如第3B圖所示之第二實施例之電子封裝件2’。
又，如第3C圖所示之第三實施例之電子封裝件3，於移除製程中，可一併移除該封裝層23之第二表面23b之部分材質與該銲線部220之彎折段220c，使該銲線部320之第一線段321與第二線段322相互分離，供作為屏蔽結構32，且該第一線段321之端處及第二線段322之端處外露於該 封裝層23之第二表面23b，其中，該些銲線部320可形成於同一功能墊302上。
另外，該承載件20之外圍部B可依需求佈設複數功能墊202,402，使該屏蔽結構42形成一封閉迴路，如第4A圖所示之第四實施例之電子封裝件4。例如，基於第3A或3B圖之銲線部220，於該置晶區A之至少一側之外圍區B上以連續打線方式形成該封閉迴路型之屏蔽結構42，如第4B圖所示，其可外露於該封裝層23之第二表面23b(如第4C圖所示)或未外露於該封裝層23(如第4C’圖所示)。具體地，該些銲線部420係前、後兩排交錯配置，以交織形成圍籬狀或網狀，使該屏蔽結構42能提供較佳的屏蔽效果。
所述之屏蔽層24係形成於該封裝層23之第二表面23b上且電性連接該承載件20之線路層200。
於本實施例中，該屏蔽層24係為導電材或其它適當之屏蔽材料，其以濺鍍或其它方式形成於該封裝層23之第二表面23b上。應可理解地，有關該屏蔽層24之構造與製作方式繁多，並無特別限制。
再者，該屏蔽層24係接觸該屏蔽結構22,32,42(如第3A、3C或4C圖所示之銲線部220,320,420)，以間接電性連接該承載件20之線路層200。於其它實施例中，若該屏蔽結構22,42未外露於該封裝層23(如第3B或4C’圖所示之銲線部220,420)，該屏蔽層24可延伸形成至該承載件20之外露處(如該承載件20之側面20c)，以接觸該線路層200之接地部203，使該屏蔽層24直接電性連接該承載件20之線路層200。
應可理解地，有關該屏蔽層24電性連接該承載件20之方式繁多，並不限於上述。
第5圖係為本發明之電子封裝件5之第五實施例之局部剖面示意圖。本實施例與上述各實施例之差異在於屏蔽結構之設計，其它構件大致相同，故以下不再贅述相同處。
如第5圖所示，該屏蔽結構52係基於第3B及3C圖之銲線部220,320以形成銲線部520。
於本實施例中，該銲線部520係包含有第一銲線521及第二銲線522，該第一銲線521相對該承載件20之高度h係低於該第二銲線522相對該承載件20之高度H，以令該第一銲線521未外露於該封裝層23，而該第二銲線522外露於該封裝層23之第二表面23b。
再者，該第一銲線521之相對兩端係分別結合至兩該功能墊202,202’上以呈弧形線狀或封閉弧圈狀，其定義有一長度較短之第一線段521a、一長度較長之第二線段521b及連結該第一線段521a與第二線段521b之彎折段521c，以令該第二線段521b之端部對應該第二銲線522配置。
又，該第二銲線522係為單一線段，其立設於該承載件20之第一側20a上，使其一端處係結合至該第一銲線521之第二線段521b所接置之功能墊202’上，而另一端處係外露於該封裝層23之第二表面23b。
應可理解地，基於第一至第五實施例，該承載件20之置晶區A之四周可依需求同時配置不同之屏蔽結構22,32,42,52於該外圍區B上，如第6圖所示之第六實施例之電子封裝件6，且各該屏蔽結構22,32,42,52之間係採用非連續打線方式形成者。
因此，本發明之電子封裝件2,2’,3,4,5,6，主要藉由該銲線部220,320,420,520作為屏蔽結構22,32,42,52，以銲接於該承載件20上，而不會受溫度、濕度及其它環境因素的影響，故相較於習知技術，本發明之電 子封裝件2,2’,3,4,5,6能有效避免該屏蔽結構22,32,42,52從該承載件20上剝離或脫落之問題。
再者，該封裝層23包覆該屏蔽結構22,32,42,52，因而該屏蔽結構22,32,42,52的尺寸與形狀無需配合該封裝層23的尺寸與形狀，使兩者的配合度無需關精密製程，故相較於習知技術，本發明之電子封裝件2於製作該屏蔽結構22,32,42,52與該封裝層23上無關相對位置之準確度，以大幅降低製作成本及製程時間。
又，由於該承載件20已定義出該置晶區A與該外圍區B，故相較於習知技術，本發明之電子封裝件2,2’,3,4,5,6當配置不同尺寸與形狀的電子元件21時，無需製作不同尺寸與形狀的封裝層23，因而無需特製模具，以大幅降低製作成本與時間。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
20:承載件
202:功能墊
22:屏蔽結構
220:銲線部
220c:彎折段
221:第一線段
222:第二線段
23:封裝層
23a:第一表面
23b:第二表面
24:屏蔽層

Claims (21)

  1. 一種電子封裝件，係包括：承載件；電子元件，係設於該承載件上；以及屏蔽結構，係包含複數銲線部，且各該銲線部係以連續打線方式立設於該承載件上，其中，該銲線部係呈弧形線狀，其定義有第一線段、第二線段及連結該第一線段與第二線段之彎折段；其中，該屏蔽結構係形成一封閉迴路。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該第一線段之長度與該第二線段之長度係不相等。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該銲線部係為單一線段。
  4. 如申請專利範圍第1項所述之電子封裝件，復包括包覆該電子元件與該屏蔽結構之封裝層。
  5. 如申請專利範圍第4項所述之電子封裝件，其中，該屏蔽結構係局部外露於該封裝層。
  6. 如申請專利範圍第4項所述之電子封裝件，復包括形成於該封裝層上之屏蔽層。
  7. 如申請專利範圍第6項所述之電子封裝件，其中，該屏蔽層係電性連接該承載件。
  8. 如申請專利範圍第6項所述之電子封裝件，其中，該屏蔽層係接觸該屏蔽結構。
  9. 如申請專利範圍第6項所述之電子封裝件，其中，該屏蔽層係未接觸該屏蔽結構。
  10. 如申請專利範圍第1項所述之電子封裝件，其中，該複數銲線部之間係全部連續打線，使該屏蔽結構呈一體式。
  11. 如申請專利範圍第1項所述之電子封裝件，其中，該複數銲線部之其中相鄰兩者之間係中斷連續打線，使該屏蔽結構呈不連續之多段式。
  12. 一種電子封裝件，係包括：承載件；電子元件，係設於該承載件上；以及屏蔽結構，係包含複數銲線部，且各該銲線部係以連續打線方式立設於該承載件上，其中，該銲線部係具有第一銲線及第二銲線，該第一銲線係呈弧形線狀且其一端對應該第二銲線配置，同時該第二銲線係為單一線段且其立設於該承載件上。
  13. 如申請專利範圍第12項所述之電子封裝件，其中，該第一銲線相對該承載件之高度係低於該第二銲線相對該承載件之高度。
  14. 如申請專利範圍第12項所述之電子封裝件，其中，該第一銲線係定義有第一線段、第二線段及連結該第一線段與第二線段之彎折段。
  15. 如申請專利範圍第12項所述之電子封裝件，其中，該第二銲線係以其一端處結合至該第一銲線所接置之處。
  16. 如申請專利範圍第12項所述之電子封裝件，復包括包覆該電子元件與該屏蔽結構之封裝層。
  17. 如申請專利範圍第16項所述之電子封裝件，其中，該屏蔽結構係局部外露於該封裝層。
  18. 如申請專利範圍第16項所述之電子封裝件，復包括形成於該封裝層上之屏蔽層。
  19. 如申請專利範圍第18項所述之電子封裝件，其中，該屏蔽層係電性連接該承載件。
  20. 如申請專利範圍第18項所述之電子封裝件，其中，該屏蔽層係接觸該屏蔽結構。
  21. 如申請專利範圍第18項所述之電子封裝件，其中，該屏蔽層係未接觸該屏蔽結構。
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