CN113745199A - 电子封装件 - Google Patents

电子封装件 Download PDF

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Publication number
CN113745199A
CN113745199A CN202010512317.9A CN202010512317A CN113745199A CN 113745199 A CN113745199 A CN 113745199A CN 202010512317 A CN202010512317 A CN 202010512317A CN 113745199 A CN113745199 A CN 113745199A
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Prior art keywords
wire
electronic package
package according
shielding
shielding structure
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Inventor
邱志贤
蔡文荣
叶育玮
蔡宗贤
石启良
杨胜明
廖彬宏
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN113745199A publication Critical patent/CN113745199A/zh
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Abstract

本发明涉及一种电子封装件，其以多个焊线作为屏蔽结构，该焊线焊接于一承载有电子元件的承载件上，从而利用该焊线不会受温度、湿度及其它环境因素的影响，避免该屏蔽结构从该承载件上剥离或脱落的问题。

Description

电子封装件
技术领域
本发明有关一种半导体封装制程，尤指一种具屏蔽结构的电子封装件。
背景技术
随着电子产业的蓬勃发展，许多高阶电子产品都逐渐朝往轻、薄、短、小等高集成度方向发展，且随着封装技术的演进，芯片的封装技术也越来越多样化，半导体封装件的尺寸或体积也随之不断缩小，借以使该半导体封装件达到轻薄短小的目的。
为符合电子产品轻薄短小的趋势，使得其上封装件的设置密度增加，但是此将导致封装件间容易产生电磁干扰(electromagnetic interference，EMI)的现象。
为解决各电子封装件之间的电磁干扰的问题，通常会于封装件的封装过程中，于外部设置屏蔽件，以避免各封装件间的电磁干扰。
如图1所示，悉知半导体封装件1通过于一封装基板10上设置至少一半导体元件11,11’，再以封装胶体13包覆该半导体元件11,11’，之后，经由导电胶120将一屏蔽罩12接合于该封装基板10上，以令该屏蔽罩12遮盖该半导体元件11,11’。
然而，悉知半导体封装件1中，该导电胶120的粘着性会受到温度、湿度及其它环境因素的影响而降低，致使该屏蔽罩12容易从该封装基板10上剥离或脱落。
此外，当该屏蔽罩12固定至该封装胶体13上时，该屏蔽罩12的尺寸与形状需与该封装胶体13的尺寸与形状相互配合，因而两者的配合度需极为精密，使该屏蔽罩12与该封装胶体13于制作上需具备一定的相对位置的准确度，导致制作成本提高且耗费制程时间。
另外，该屏蔽罩12与该封装胶体13于尺寸与形状需相互配合，故若配置不同尺寸与形状的半导体元件11,11’时，需搭配不同尺寸与形状的屏蔽罩，导致需特制模具，以制作不同尺寸与形状的封装胶体13，因而增加制作成本与时间。
因此，如何克服上述悉知技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述悉知技术的种种缺陷，本发明提供一种电子封装件，可避免屏蔽结构从承载件上剥离或脱落的问题。
本发明的电子封装件包括：承载件；电子元件，其设于该承载件上；以及屏蔽结构，其包含多个焊线部，且各该焊线部以连续打线方式立设于该承载件上，其中，该焊线部呈弧形线状，其定义有第一线段、第二线段及连接该第一线段与第二线段的弯折段。
前述的电子封装件中，该第一线段的长度与该第二线段的长度为不相等。
前述的电子封装件中，该焊线部为单一线段。
前述的电子封装件中，该屏蔽结构形成一封闭回路。
前述的电子封装件中，还包括包覆该电子元件与该屏蔽结构的封装层。例如，该屏蔽结构局部外露于该封装层。又包括形成于该封装层上的屏蔽层。进一步，该屏蔽层电性连接该承载件；或者，该屏蔽层接触该屏蔽结构；亦或，该屏蔽层未接触该屏蔽结构。
前述的电子封装件中，该多个焊线部之间全部连续打线，使该屏蔽结构呈一体式。
前述的电子封装件中，该多个焊线部的其中相邻两者之间中断连续打线，使该屏蔽结构呈不连续的多段式。
本发明还提供一种电子封装件，包括：承载件；电子元件，其设于该承载件上；以及屏蔽结构，其包含多个焊线部，且各该焊线部以连续打线方式立设于该承载件上，其中，该焊线部具有第一焊线及第二焊线，该第一焊线呈弧形线状且其一端对应该第二焊线配置，同时该第二焊线为单一线段且其立设于该承载件上。
前述的电子封装件中，该第一焊线相对该承载件的高度低于该第二焊线相对该承载件的高度。
前述的电子封装件中，该第一焊线定义有第一线段、第二线段及连接该第一线段与第二线段的弯折段。
前述的电子封装件中，该第二焊线以其一端处结合至该第一焊线所接置之处。
前述的电子封装件中，还包括包覆该电子元件与该屏蔽结构的封装层。例如，该屏蔽结构局部外露于该封装层。又包括形成于该封装层上的屏蔽层。例如，该屏蔽层电性连接该承载件；或者，该屏蔽层接触该屏蔽结构；亦或，该屏蔽层未接触该屏蔽结构。
由上可知，本发明的电子封装件中，主要经由该焊线部作为屏蔽结构，以焊接于该承载件上，而不会受温度、湿度及其它环境因素的影响，故相比于悉知技术，本发明的电子封装件可有效避免该屏蔽结构从该承载件上剥离或脱落的问题。
附图说明
图1为悉知半导体封装件的剖视示意图。
图2为本发明的电子封装件的第一实施例的上视示意图。
图2’为本发明的电子封装件的第一实施例的其中一视角的剖视示意图。
图2A为图2的屏蔽结构的制作方式的侧面示意图。
图2B为图2A的另一态样示意图。
图3A为本发明的电子封装件的第一实施例的另一视角的剖视示意图。
图3A’为图3A的另一态样的剖视示意图。
图3B为本发明的电子封装件的第二实施例的剖视示意图。
图3C为本发明的电子封装件的第三实施例的剖视示意图。
图4A为本发明的电子封装件的第四实施例的局部上视示意图。
图4B为图4A的局部立体示意图。
图4C及图4C’为图4A的不同态样的剖视示意图。
图5为本发明的电子封装件的第五实施例的剖视示意图。
图6为本发明的电子封装件的第六实施例的上视示意图。
附图标记说明
1 半导体封装件 10 封装基板
11,11’ 半导体元件 12 屏蔽罩
120 导电胶 13 封装胶体
2,2’,3,4,5,6 电子封装件 20 承载件
20a 第一侧 20b 第二侧
20c 侧面 200 线路层
201 电性接触垫 202,202’,302,402 功能垫
203 接地部 21 电子元件
21a 作用面 21b 非作用面
210 电极垫 211 导线
22,22’,32,42,52 屏蔽结构 220,220’,320,420,520 焊线部
220a 球体 220b 截断处
220c,521c 弯折段 221,321,521a 第一线段
222,322,521b 第二线段 23 封装层
23a 第一表面 23b 第二表面
24 屏蔽层 28 胶材
521 第一焊线 522 第二焊线
A 置晶区 B 外围区
H,h 高度。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“第一”、“第二”、“上”、及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2为本发明的电子封装件2的第一实施例的上视示意图。如图2所示，所述的电子封装件2包括一承载件20、至少一设于该承载件20上的电子元件21、以及一设于该承载件20上并遮蔽该电子元件21四周的屏蔽结构22。
于本实施例中，如图2’所示，该电子封装件2还包括一包覆该电子元件21与该屏蔽结构22的封装层23、以及一设于该封装层23上的屏蔽层24。
所述的承载件20具有相对的第一侧20a与第二侧20b，且该第一侧20a上定义有一置晶区A及围绕该置晶区A的外围区B。
于本实施例中，该承载件20为具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构，该线路结构于介电材上形成线路层200，如扇出(fanout)型重布线路层(redistribution layer，简称RDL)，且介电材为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等。应可理解地，该承载件20也可为其它可供承载如芯片等电子元件的承载单元，例如导线架(lead-frame)或硅中介板(silicon interposer)等载件，并不限于上述。
此外，该线路层200包含有多个配置于该置晶区A上的电性接触垫201及至少一可依需求配置于该外围区B上的功能垫202。
另外，图2所示的X-X剖面线呈现图2’所示的放大剖面结构，且图2所示的Y-Y剖面线呈现图3A所示的局部放大剖面结构。
所述的电子元件21设于该承载件20的第一侧20a的置晶区A上。
于本实施例中，该电子元件21为主动元件、被动元件或其组合者，且该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。例如，该电子元件21为半导体芯片，其具有作用面21a与相对该作用面21a的非作用面21b，该电子元件21以其非作用面21b经由胶材28设于该承载件20的第一侧20a上，且该作用面21a上具有多个电极垫210，以经由多个导线211以打线方式电性连接该电极垫210与电性接触垫201；或者，该电子元件21可经由多个导电凸块(图略)以覆晶方式电性连接该承载件20的电性接触垫201，并以底胶(图略)包覆该些导电凸块；亦或，该电子元件21的电极垫210可直接接触该电性接触垫201以电性连接该线路层200。然而，有关该电子元件21电性连接该承载件20的方式不限于上述。
所述的屏蔽结构22包含多个焊线部220(如图3A所示)，且该多个焊线部220立设于该承载件20的第一侧20a的外围区B上。
于本实施例中，该焊线部220接触结合至该承载件20的功能垫202上，使该焊线部220电性连接该承载件20。例如，该焊线部220为打线方式所用的金属线材，且该焊线部220的两端分别结合至该承载件20的两个功能垫202上，如图3A所示。
此外，如图3A所示，该屏蔽结构22以连续打线方式形成每一焊线部220，如弧形线状或封闭弧圈状，且单一焊线部220定义有第一线段221、第二线段222及连接该第一线段221与第二线段222的弯折段220c。例如，该第一线段221与第二线段222的长度为不相等。具体地，该第一线段221的长度短于该第二线段222的长度。
另外，该屏蔽结构22的连续打线方式经由打线机台(图略)的焊嘴(图略)将一金线从一功能垫202拉到另一功能垫202上并予以焊接(Stitch Bond)且截断，如图2A所示，再令该焊嘴以截断处220b牵引出另一金线。或者，如图2B所示，于截断后，该焊嘴先于截断处220b形成一球体220a，再牵引另一金线。
另外，该多个焊线部220之间可依需求全部连续打线，使该屏蔽结构22呈一体式(如图3A所示)，也可如图3A’所示，将任相邻两焊线部220’之间中断连续打线，使该屏蔽结构22’呈不连续的多段式。
所述的封装层23设于该承载件20的第一侧20a上以包覆该电子元件21与该屏蔽结构22。
于本实施例中，该封装层23的形成材料为绝缘材，例如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装层(molding compound)。例如，该封装层23的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该承载件20的第一侧20a上。
此外，该封装层23定义有相对的第一表面23a与第二表面23b，且该封装层23以其第一表面23a结合于该承载件20的第一侧20a上。因此，该焊线部220可依需求外露于该封装层23的第二表面23b，如图3A所示。例如，可经由移除制程，移除该封装层23的第二表面23b的部分材料，使该焊线部220的弯折段220c凸出该封装层23的第二表面23b，以令该弯折段220c外露于该封装层23的第二表面23b。或者，该焊线部220也可未外露于该封装层23，如图3B所示的第二实施例的电子封装件2’。
另外，如图3C所示的第三实施例的电子封装件3，于移除制程中，可一并移除该封装层23的第二表面23b的部分材料与该焊线部220的弯折段220c，使该焊线部320的第一线段321与第二线段322相互分离，供作为屏蔽结构32，且该第一线段321的端处及第二线段322的端处外露于该封装层23的第二表面23b，其中，该些焊线部320可形成于同一功能垫302上。
另外，该承载件20的外围部B可依需求布设多个功能垫202,402，使该屏蔽结构42形成一封闭回路，如图4A所示的第四实施例的电子封装件4。例如，基于图3A或图3B的焊线部220，于该置晶区A的至少一侧的外围区B上以连续打线方式形成该封闭回路型的屏蔽结构42，如图4B所示，其可外露于该封装层23的第二表面23b(如图4C所示)或未外露于该封装层23(如图4C’所示)。具体地，该些焊线部420为前、后两排交错配置，以交织形成围篱状或网状，使该屏蔽结构42能提供较佳的屏蔽效果。
所述的屏蔽层24形成于该封装层23的第二表面23b上且电性连接该承载件20的线路层200。
于本实施例中，该屏蔽层24为导电材或其它适当的屏蔽材料，其以溅镀或其它方式形成于该封装层23的第二表面23b上。应可理解地，有关该屏蔽层24的构造与制作方式繁多，并无特别限制。
此外，该屏蔽层24接触该屏蔽结构22,32,42(如图3A、图3C或图4C所示的焊线部220,320,420)，以间接电性连接该承载件20的线路层200。于其它实施例中，若该屏蔽结构22,42未外露于该封装层23(如图3B或图4C’所示的焊线部220,420)，该屏蔽层24可延伸形成至该承载件20的外露处(如该承载件20的侧面20c)，以接触该线路层200的接地部203，使该屏蔽层24直接电性连接该承载件20的线路层200。
应可理解地，有关该屏蔽层24电性连接该承载件20的方式繁多，并不限于上述。
图5为本发明的电子封装件5的第五实施例的局部剖面示意图。本实施例与上述各实施例的差异在于屏蔽结构的设计，其它构件大致相同，故以下不再赘述相同处。
如图5所示，该屏蔽结构52基于图3B及图3C的焊线部220,320以形成焊线部520。
于本实施例中，该焊线部520包含有第一焊线521及第二焊线522，该第一焊线521相对该承载件20的高度h低于该第二焊线522相对该承载件20的高度H，以令该第一焊线521未外露于该封装层23，而该第二焊线522外露于该封装层23的第二表面23b。
此外，该第一焊线521的相对两端分别结合至两该功能垫202,202’上以呈弧形线状或封闭弧圈状，其定义有一长度较短的第一线段521a、一长度较长的第二线段521b及连接该第一线段521a与第二线段521b的弯折段521c，以令该第二线段521b的端部对应该第二焊线522配置。
另外，该第二焊线522为单一线段，其立设于该承载件20的第一侧20a上，使其一端处结合至该第一焊线521的第二线段521b所接置的功能垫202’上，而另一端处为外露于该封装层23的第二表面23b。
应可理解地，基于第一至第五实施例，该承载件20的置晶区A的四周可依需求同时配置不同的屏蔽结构22,32,42,52于该外围区B上，如图6所示的第六实施例的电子封装件6，且各该屏蔽结构22,32,42,52之间采用非连续打线方式形成者。
因此，本发明的电子封装件2,2’,3,4,5,6，主要经由该焊线部220,320,420,520作为屏蔽结构22,32,42,52，以焊接于该承载件20上，而不会受温度、湿度及其它环境因素的影响，故相比于悉知技术，本发明的电子封装件2,2’,3,4,5,6能有效避免该屏蔽结构22,32,42,52从该承载件20上剥离或脱落的问题。
此外，该封装层23包覆该屏蔽结构22,32,42,52，因而该屏蔽结构22,32,42,52的尺寸与形状无需配合该封装层23的尺寸与形状，使两者的配合度无需关精密制程，故相比于悉知技术，本发明的电子封装件2于制作该屏蔽结构22,32,42,52与该封装层23上无关相对位置的准确度，以大幅降低制作成本及制程时间。
另外，由于该承载件20已定义出该置晶区A与该外围区B，故相比于悉知技术，本发明的电子封装件2,2’,3,4,5,6当配置不同尺寸与形状的电子元件21时，无需制作不同尺寸与形状的封装层23，因而无需特制模具，以大幅降低制作成本与时间。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (22)

1.一种电子封装件，其特征在于，包括：
承载件；
电子元件，其设于该承载件上；以及
屏蔽结构，其包含多个焊线部，且各该焊线部以连续打线方式立设于该承载件上，其中，该焊线部呈弧形线状，其定义有第一线段、第二线段及连接该第一线段与第二线段的弯折段。
2.如权利要求1所述的电子封装件，其特征在于，该第一线段的长度与该第二线段的长度为不相等。
3.如权利要求1所述的电子封装件，其特征在于，该焊线部为单一线段。
4.如权利要求1所述的电子封装件，其特征在于，该屏蔽结构形成一封闭回路。
5.如权利要求1所述的电子封装件，其特征在于，该电子封装件还包括包覆该电子元件与该屏蔽结构的封装层。
6.如权利要求5所述的电子封装件，其特征在于，该屏蔽结构为局部外露于该封装层。
7.如权利要求5所述的电子封装件，其特征在于，该电子封装件还包括形成于该封装层上的屏蔽层。
8.如权利要求7所述的电子封装件，其特征在于，该屏蔽层电性连接该承载件。
9.如权利要求7所述的电子封装件，其特征在于，该屏蔽层接触该屏蔽结构。
10.如权利要求7所述的电子封装件，其特征在于，该屏蔽层未接触该屏蔽结构。
11.如权利要求1所述的电子封装件，其特征在于，该多个焊线部之间为全部连续打线，使该屏蔽结构呈一体式。
12.如权利要求1所述的电子封装件，其特征在于，该多个焊线部的其中相邻两者之间为中断连续打线，使该屏蔽结构呈不连续的多段式。
13.一种电子封装件，其特征在于，包括：
承载件；
电子元件，其设于该承载件上；以及
屏蔽结构，其包含多个焊线部，且各该焊线部以连续打线方式立设于该承载件上，其中，该焊线部具有第一焊线及第二焊线，该第一焊线呈弧形线状且其一端对应该第二焊线配置，同时该第二焊线为单一线段且其立设于该承载件上。
14.如权利要求13所述的电子封装件，其特征在于，该第一焊线相对该承载件的高度低于该第二焊线相对该承载件的高度。
15.如权利要求13所述的电子封装件，其特征在于，该第一焊线定义有第一线段、第二线段及连接该第一线段与第二线段的弯折段。
16.如权利要求13所述的电子封装件，其特征在于，该第二焊线以其一端处结合至该第一焊线所接置之处。
17.如权利要求13所述的电子封装件，其特征在于，该电子封装件还包括包覆该电子元件与该屏蔽结构的封装层。
18.如权利要求17所述的电子封装件，其特征在于，该屏蔽结构为局部外露于该封装层。
19.如权利要求17所述的电子封装件，其特征在于，该电子封装件还包括形成于该封装层上的屏蔽层。
20.如权利要求19所述的电子封装件，其特征在于，该屏蔽层电性连接该承载件。
21.如权利要求19所述的电子封装件，其特征在于，该屏蔽层为接触该屏蔽结构。
22.如权利要求19所述的电子封装件，其特征在于，该屏蔽层未接触该屏蔽结构。
CN202010512317.9A 2020-05-29 2020-06-08 电子封装件 Pending CN113745199A (zh)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11437306B2 (en) * 2020-02-04 2022-09-06 Stmicroelectronics (Grenoble 2) Sas Electronics unit with integrated metallic pattern
JP2022144711A (ja) * 2021-03-19 2022-10-03 三菱電機株式会社 半導体装置の製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8399972B2 (en) * 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
JP4881620B2 (ja) * 2006-01-06 2012-02-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US20080014678A1 (en) * 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film
US20080310114A1 (en) * 2007-06-18 2008-12-18 Lucent Technologies Inc. Heat-transfer device for an electromagnetic interference (emi) shield using conductive bristles
US8373264B2 (en) * 2008-07-31 2013-02-12 Skyworks Solutions, Inc. Semiconductor package with integrated interference shielding and method of manufacture thereof
US8012868B1 (en) * 2008-12-15 2011-09-06 Amkor Technology Inc Semiconductor device having EMI shielding and method therefor
TWI379367B (en) * 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
KR20120026909A (ko) * 2010-09-10 2012-03-20 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US9071335B2 (en) * 2011-07-08 2015-06-30 Skyworks Solutions, Inc. Radio-frequency modules having tuned shielding-wirebonds
US8836136B2 (en) * 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
TWI505425B (zh) * 2012-01-30 2015-10-21 Advanced Semiconductor Eng 整合屏蔽膜之半導體封裝件及其製造方法
KR20160006257A (ko) * 2012-06-14 2016-01-18 스카이워크스 솔루션즈, 인코포레이티드 Bifet 및 고조파 종단 및 관련된 시스템, 장치, 및 방법을 갖는 전력 증폭기 모듈
CN104885216B (zh) * 2012-07-13 2017-04-12 天工方案公司 在射频屏蔽应用中的轨道设计
JP2014107486A (ja) * 2012-11-29 2014-06-09 Fujitsu Ltd 配線構造、及び、電子装置
US9419667B2 (en) * 2013-04-16 2016-08-16 Skyworks Solutions, Inc. Apparatus and methods related to conformal coating implemented with surface mount devices
WO2016196189A1 (en) * 2015-05-31 2016-12-08 Skyworks Solutions, Inc. Shielded module having compression overmold
US20170117229A1 (en) * 2015-10-22 2017-04-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit package with trench features to provide internal shielding between electronic components
KR101815754B1 (ko) * 2016-03-10 2018-01-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
EP3440698A4 (en) * 2016-04-01 2020-02-12 INTEL Corporation SEMICONDUCTOR HOUSING WITH STRUCTURES FOR SHIELDING ELECTROMAGNETIC INTERFERENCES
US10134686B2 (en) * 2016-09-30 2018-11-20 Avago Technologies International Sales Pte. Limited Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components disposed inside of system electronic packages
US10178757B2 (en) * 2016-09-30 2019-01-08 Avago Technologies International Sales Pte. Limited Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components disposed inside of system electronic packages
US20180374798A1 (en) * 2017-06-24 2018-12-27 Amkor Technology, Inc. Semiconductor device having emi shielding structure and related methods
US11342276B2 (en) * 2019-05-24 2022-05-24 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing semiconductor device

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