CN107785277B - 电子封装结构及其制法 - Google Patents

电子封装结构及其制法 Download PDF

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CN107785277B
CN107785277B CN201610785726.XA CN201610785726A CN107785277B CN 107785277 B CN107785277 B CN 107785277B CN 201610785726 A CN201610785726 A CN 201610785726A CN 107785277 B CN107785277 B CN 107785277B
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carrier
electronic component
electronic
opening
bearing piece
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CN107785277A (zh
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邱志贤
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装结构及其制法，包括：具有开口的第一承载件、设于该第一承载件上的第一电子组件与多个导电组件、结合至该些导电组件上的第二承载件、设于该第二承载件上并容置于该开口中的第二电子组件、以及形成于该第一承载件与该第二承载件上且包覆该第一电子组件、第二电子组件与导电组件的包覆层，以通过将该第二电子组件容置于该开口中，而降低该电子封装结构的高度。

Description

电子封装结构及其制法
技术领域
本发明关于一种封装结构，特别是关于一种应用于堆栈的电子封装结构及其制法。
背景技术
随着近年來可携式电子产品的蓬勃发展，各类相关产品逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展，为因应此趋势，半导体封装业界遂开发各实施例的堆栈封装(package on package，简称PoP)技术，以期能符合轻薄短小与高密度的要求。
如图1所示，其为现有封装堆栈结构1的剖视示意图。如图1所示，该封装堆栈结构1包括：具有相对的第一表面10a及第二表面10b的第一基板10；结合于该第一基板10上的第一半导体芯片11；形成于该第一基板10上的焊锡柱13；形成于该第一基板10上以包覆该第一半导体芯片11与焊锡柱13的第一封装胶体16；设于该第二表面10b上的焊球15；通过焊锡柱13迭设于该第一基板10上的第二基板14；以打线方式结合于该第二基板14上的第二半导体芯片12；以及形成于该第二基板14上以包覆该第二半导体芯片12的第二封装胶体17。
然而，现有封装堆栈结构1中，并无空间增设被动组件，致使电性难以优化。若欲增设被动组件，该被动组件的高度通常极高(一般被动组件均高于第一与第二半导体芯片11,12)，致使该封装堆栈结构1的高度会因增设该被动组件而大幅增加(例如，被动组件设于该第一基板10上，该焊锡柱13的高度会增加；被动组件设于该第二基板14上，该第二封装胶体17的高度会增加)，导致该封装堆栈结构1无法符合轻薄短小的需求。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种电子封装结构及其制法，以降低该电子封装结构的高度。
本发明的电子封装结构，包括：第一承载件，其具有开口；第一电子组件，其设于该第一承载件上并电性连接该第一承载件；多个导电组件，其设于该第一承载件上并电性连接该第一承载件；第二承载件，其结合至该些导电组件上以电性连接至该第一承载件；第二电子组件，其设于该第二承载件上并容置于该开口中；以及包覆层，其形成于该第一承载件与该第二承载件上且包覆该第一电子组件、第二电子组件与导电组件。
本发明还提供一种电子封装结构的制法，包括：提供一具有开口的第一承载件，其中，该第一承载件上接置并电性连接有第一电子组件；提供一第二承载件，以将该第一承载件通过多个导电组件结合并电性连接至该第二承载件上，且令至少一第二电子组件容置于该第一承载件的开口中并设于该第二承载件上；以及形成包覆层于该第一承载件与该第二承载件上，且令该包覆层包覆该第一电子组件、第二电子组件与该些导电组件。
前述的电子封装结构及其制法中，该开口位于该第一承载件的边缘内。
前述的电子封装结构及其制法中，该开口位于该第一承载件的侧边。
前述的电子封装结构及其制法中，该开口位于该第一承载件的角落处。
前述的电子封装结构及其制法中，该第一电子组件为封装件、主动组件、或被动组件。
前述的电子封装结构及其制法中，该导电组件为焊球、铜核心球、金属件或电路板。
前述的电子封装结构及其制法中，该第一电子组件位于该第一承载件与该第二承载件之间。
前述的电子封装结构及其制法中，该第二电子组件为封装件、主动组件、被动组件或其三者组合。
前述的电子封装结构及其制法中，该第一承载件及第二承载件为线路结构、导线架、晶圆、或具有金属布线的载板。
前述的电子封装结构及其制法中，该第二电子组件电性连接该第一承载件及/或第二承载件。
前述的电子封装结构及其制法中，该第二承载件包含至少一板体，以作为电磁干扰屏蔽。例如，该第二电子组件通过导电体电性连接至该第一承载件。
另外，前述的电子封装结构及其制法中，还包括于形成该包覆层之前，形成用以包覆该第一电子组件的封装层。
由上可知，本发明的电子封装结构及其制法中，主要通过将该第二电子组件(如被动组件)容置于该第一承载件的开口中，以减少该电子封装结构的高度，而能符合轻薄短小的需求。
附图说明
图1为现有封装堆栈结构的剖面示意图；
图2A至图2C为本发明的电子封装结构的制法第一实施例的剖面示意图；其中，图2B’为图2B的另一实施例，图2C’及图2C”为图2C的其它实施例；
图3A至图3D为图2A的第一承载件的不同实施例的上视示意图；
图4为本发明的电子封装结构的第二实施例的剖面示意图；以及
图5A及图5B为图2C’的不同实施例的剖面示意图。
主要组件符号说明：
1 封装堆栈结构
10 第一基板
10a、26a 第一表面
10b、26b 第二表面
11 第一半导体芯片
12 第二半导体芯片
13 焊锡柱
14 第二基板
15 焊球
16 第一封装胶体
17 第二封装胶体
2、4 电子封装结构
20 第一承载件
20a 第一侧
20b 第二侧
20c 边缘
200 线路层
201 开口
21、21’、21” 第一电子组件
210 导电凸块
22 第二电子组件
220 导电体
23、23’、23” 导电组件
23a 焊锡材料
24、24’ 第二承载件
240、240’ 电性接触垫
241 板体
25 支撑件
26 包覆层
47 封装层
500 侧面线路
540 线路。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的电子封装结构2的制法第一实施例的剖面示意图。
如图2A所示，提供一第一承载件20，其具有相对的第一侧20a与第二侧20b及连通该第一侧20a与第二侧20b的至少一开口201，且于该第一承载件20的第一侧20a上设有至少一第一电子组件21与多个如焊球(solder ball)的导电组件23，并于该第一承载件20的第二侧20b上设有多个第一电子组件21’,21”。
于本实施例中，该第一承载件20为具有核心层或无核心层(coreless)的线路结构(如封装基板substrate)，其具有多个线路层200，如扇出(fan out)型重布线路层(redistribution layer，简称RDL)。应可理解地，该第一承载件20也可为其它承载芯片的承载件，如导线架(leadframe)、晶圆(wafer)、或其他具有金属布线(routing)的载板(如低温共烧陶瓷(low temperature cofired ceramic，简称LTCC)或铁氧体(Ferrite))，并不限于上述。
此外，该开口201的数量可为一个或多个，其位置可依需求而定或配合该线路层200的布设范围而改变，例如，位于该第一承载件20的中心、周围或角落，以提高该第一承载件20的面积利用率。具体地，如图3A所示，为该第一承载件20的上视示意图，该开口201完全位于该第一承载件20的边缘20c内；如图3B所示，该开口201的一侧连通该第一承载件20的边缘20c，即位于该第一承载件20的侧边；如图3C所示，该开口201的两侧连通该第一承载件20的边缘20c，即位于该第一承载件20的角落处；如图3D所示，该开口201的三侧连通该第一承载件20的边缘20c，即移除该第一承载件20的其中一侧面部分的材质。
又，该第一电子组件21,21’,21”为封装件(如标号21’)、主动组件(如标号21)、被动组件(如标号21”)或其三者组合等，其中，该封装件为例如芯片级封装(Chip ScalePackage，简称CSP)，该主动组件为例如半导体芯片，且该被动组件为例如电阻、电容及电感。例如，该第一电子组件21,21’通过多个如焊锡材料的导电凸块210以覆晶方式设于该线路层200上并电性连接该线路层200；或者，该第一电子组件21,21’可通过多个焊线(图略)以打线方式电性连接该线路层200。抑或，该第一电子组件21”可直接接触该线路层200。然而，有关该第一电子组件电性连接该第一承载件20的方式不限于上述。
另外，还提供一其上设有至少一第二电子组件22的第二承载件24，该第二承载件24为例如为导线架(leadframe)，其包含多个相分离的电性接触垫240,240’，使该第二电子组件22结合至该电性接触垫240’上以电性连接该第二承载件24。应可理解地，该第二承载件24亦可为其它承载芯片的承载件，例如，具有核心层或无核心层(coreless)的线路结构、晶圆(wafer)、或其他具有金属布线(routing)的载板(如低温共烧陶瓷(low temperaturecofired ceramic，简称LTCC)、铁氧体(Ferrite))，并不限于上述。
所述的第二承载件24可选择性地设于一如胶带(tape)的支撑件25上，且该第二电子组件22为封装件、主动组件、被动组件或其三者组合等，其中，该封装件为例如芯片级封装(CSP)，且该主动组件为例如半导体芯片，而该被动组件为例如电阻、电容及电感。于本实施例中，该第二电子组件22以被动组件为例。
如图2B所示，将该第一承载件20以该些导电组件23结合至第二承载件24的该电性接触垫240上，使该第一承载件20的线路层200电性连接该第二承载件24，且令该第二电子组件22对应容置于该第一承载件20的开口201中。
于另一实施例中，如图2B’所示，也可先将该第一承载件20与该第二承载件24相堆栈后，再将该第二电子组件22容置于该开口201中并设于该电性接触垫240’上。
如图2C所示，形成一包覆层26于该第一承载件20与该第二承载件24(或该支撑件25)上并填入该开口201中，使该包覆层26包覆该些第一电子组件21,21’,21”、该第二电子组件22、及该些导电组件23。之后，移除该支撑件25。
于本实施例中，形成该包覆层26的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材(molding compound)，且该包覆层26具有相对的第一表面26a与第二表面26b，使该第二承载件24嵌设于该包覆层26的第一表面26a，且该些电性接触垫240外露于该包覆层26的第一表面26a(例如，该些电性接触垫240的表面齐平该包覆层26的第一表面26a)，从而供后续于该些电性接触垫240的外露表面上形成有如焊球的焊锡材料(图略)，以接置于如电路板或另一线路板的电子装置。
此外，如图2C’所示，该导电组件23’可为环状电路板(ring tape circuit board)或长条状电路板，其通过焊锡材料23a结合于该线路层200与该电性接触垫240上，以增加该第一承载件20与该第二承载件24之间的间距(gap)，使该第一与第二承载件20,24之间有足够空间接置该第一电子组件21。或者，如图2C”所示，该导电组件23”也可为铜核心球(Cucore ball)或如铜材或金材的金属件(如柱状、块状或针状)等。
又，如图2C’所示，该第二电子组件22也可通过如焊线(bonding wire)或夹条(clip bar)的导电体220电性连接至该第一承载件20的线路层200。于其它实施例中，如图5A所示，该导电体220可电性连接该第一承载件20的线路层200与该第二承载件24的线路540，且该线路540电性连接该电性接触垫240’；或者，如图5B所示，该导电体220可电性连接该第一承载件20的侧面线路500与该第二电子组件22，其中，该导电体220例如为导电胶或焊锡材料。
另外，如图2C”所示，该第二承载件24’还包含至少一板体241，其可与该些电性接触垫240,240’相分离或相连结，并可接地，以提供电磁干扰(electromagneticinterference，简称EMI)屏蔽(shielding)的效果。
因此，本发明通过将接置在第二承载件24的该第二电子组件22(如被动组件)容置于该第一承载件20的开口201中，以减少该电子封装结构2的高度，而能符合轻薄短小的需求。
此外，该第二承载件24’不仅能提供EMI屏蔽的效果，且若该第二承载件24,24’为导线架或金属板，可提高该电子封装结构2的散热效率。
又，一般主动组件与被动组件设于同一基板上，因而可通过基板的线路直接相互电性连接。然而，本发明的电子封装结构2由于该第二电子组件22(被动组件)的设置与该第一电子组件21(主动组件)的设置分别位于不同承载件上，因而无法以同一承载件的线路直接电性连接，故通过该导电体220的设计，可以减少该第一承载件20与该第二承载件24的布线范围(例如减少I/O数)，且减少直流阻抗与交流阻抗。若如图2C所示，该第一电子组件21通过该导电组件23与电性接触垫240，再经由该第二承载件24的线路(图略)电性连接该电性接触垫240’与第二电子组件22，其中，该电性接触垫240,240’之间的线路(图略)长于图5A所示的线路540。
图4为本发明的电子封装结构4的第二实施例的剖面示意图。本实施例与第一实施例大致相同，主要的差异在于封装制造方法，故以下仅说明相异处，而不再赘述相同处。
如图4所示，于图2B的制造方法之前，可先于该第一承载件20的第二侧20b上形成用以包覆该些第一电子组件21’,21”的封装层47，且该封装层47未填满该开口201，之后才进行图2B至图2C的制造方法，以得到如图4所示的电子封装结构4。
于本实施例中，形成该封装层47的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材(molding compound)。应可理解地，该包覆层26的材质与该封装层47的材质可相同或不相同。
通过前述制造方法，本发明提供一种电子封装结构2,4，其包括：一第一承载件20、多个第一电子组件21,21’,21”、多个导电组件23,23’,23”、一第二承载件24,24’、一第二电子组件22以及一包覆层26。
所述的第一承载件20具有至少一开口201。
所述的第一电子组件21,21’,21”设于该第一承载件20上并电性连接该第一承载件20。
所述的导电组件23,23’,23”设于该第一承载件20上并电性连接该第一承载件20。
所述的第二承载件24,24’结合至该些导电组件23上以堆栈并电性连接至该第一承载件20。
所述的第二电子组件22设于该第二承载件24,24’上并容置于该开口201中。
所述的包覆层26形成于该第一承载件20与该第二承载件24,24’上且包覆该第一电子组件21(及该第一电子组件21’,21”)、第二电子组件22与导电组件23,23’,23”。
于一实施例中，该开口201完全位于该第一承载件20的边缘20c内。
于一实施例中，该开口201位于该第一承载件20的一侧边(其中一边缘20c)。
于一实施例中，该开口201位于该第一承载件20的角落处。
于一实施例中，该第一电子组件21,21’,21”为封装件、主动组件、被动组件或其三者组合。
于一实施例中，该导电组件23,23’,23”为焊球、铜核心球、金属件或电路板。
于一实施例中，该第一电子组件21位于该第一承载件20与该第二承载件24之间。
于一实施例中，该第二电子组件22为封装件、主动组件、被动组件或其三者组合。
于一实施例中，该第二电子组件22电性连接该第一承载件20及/或第二承载件24,24’。
于一实施例中，该第一承载件20及第二承载件24,24’为线路结构、导线架、晶圆、或具有金属布线的载板。
于一实施例中，该第二承载件24’包含至少一板体241，以作为电磁干扰屏蔽。
于一实施例中，该电子封装结构4还包括包覆部分该第一电子组件21’,21”的封装层47。
综上所述，本发明的电子封装结构及其制法，通过该开口的设计，使该第二电子组件(如被动组件)能容置于该开口中，以降低该电子封装结构的高度，而能符合轻薄短小的需求。
此外，该第二承载件不仅能提供EMI屏蔽的效果，且能提高该电子封装结构的散热效率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装结构，其特征为，该电子封装结构包括：
第一承载件，其具有相对的第一侧与第二侧，且具有开口；
第一电子组件，其接置并电性连接至该第一承载件上；
多个导电组件，其接置并电性连接至该第一承载件的第一侧上，其中，该导电组件包括电性连接至该第一承载件的环状电路板或长条状电路板；
第二承载件，其经焊锡材料结合至所述导电组件的环状电路板或长条状电路板以电性连接至该第一承载件，其中，该第二承载件为导线架；
第二电子组件，其设于该第二承载件上并容置于该第一承载件的开口中，其中，该第二电子组件未突出该第一承载件的第二侧，且该第二电子组件经焊线电性连接至该第一承载件；以及
包覆层，其形成于该第一承载件与该第二承载件上且包覆该第一电子组件、第二电子组件与导电组件。
2.如权利要求1所述的电子封装结构，其特征为，该开口位于该第一承载件的边缘内。
3.如权利要求1所述的电子封装结构，其特征为，该开口位于该第一承载件的侧边。
4.如权利要求1所述的电子封装结构，其特征为，该开口位于该第一承载件的角落处。
5.如权利要求1所述的电子封装结构，其特征为，该第一电子组件及第二电子组件为封装件、主动组件、或被动组件。
6.如权利要求1所述的电子封装结构，其特征为，该第一承载件为线路结构、导线架、晶圆、或具有金属布线的载板。
7.如权利要求1所述的电子封装结构，其特征为，该第一电子组件位于该第一承载件与该第二承载件之间。
8.如权利要求1所述的电子封装结构，其特征为，该第二电子组件电性连接该第一承载件及第二承载件。
9.如权利要求1所述的电子封装结构，其特征为，该第二承载件包含至少一板体，以作为电磁干扰屏蔽。
10.如权利要求1所述的电子封装结构，其特征为，该电子封装结构还包括包覆该第一电子组件的封装层。
11.一种电子封装结构的制法，其特征为，该制法包括：
提供一具有相对的第一侧与第二侧，且具有开口的第一承载件，其中，该第一承载件上接置并电性连接有第一电子组件；
提供一第二承载件，以将该第一承载件的第一侧通过多个导电组件结合并电性连接至该第二承载件上，且令至少一第二电子组件容置于该第一承载件的开口中并设于该第二承载件上，其中，该导电组件包括电性连接至该第一承载件的环状电路板或长条状电路板，该第二承载件为导线架，该第二承载件经焊锡材料结合至所述导电组件的环状电路板或长条状电路板，该第二电子组件未突出该第一承载件的第二侧，且该第二电子组件经焊线电性连接至该第一承载件；以及
形成包覆层于该第一承载件与该第二承载件上，以令该包覆层包覆该第一电子组件、第二电子组件与所述导电组件。
12.如权利要求11所述的电子封装结构的制法，其特征为，该开口位于该第一承载件的边缘内。
13.如权利要求11所述的电子封装结构的制法，其特征为，该开口位于该第一承载件的侧边。
14.如权利要求11所述的电子封装结构的制法，其特征为，该开口位于该第一承载件的角落处。
15.如权利要求11所述的电子封装结构的制法，其特征为，该第一电子组件及第二电子组件为封装件、主动组件、或被动组件。
16.如权利要求11所述的电子封装结构的制法，其特征为，该第一承载件为线路结构、导线架、晶圆、或具有金属布线的载板。
17.如权利要求11所述的电子封装结构的制法，其特征为，该第一电子组件位于该第一承载件与该第二承载件之间。
18.如权利要求11所述的电子封装结构的制法，其特征为，该第二电子组件电性连接该第一承载件及第二承载件。
19.如权利要求11所述的电子封装结构的制法，其特征为，该第二承载件包含至少一板体，以作为电磁干扰屏蔽。
20.如权利要求11所述的电子封装结构的制法，其特征为还包括于形成该包覆层之前，形成用以包覆该第一电子组件的封装层。
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