CN113363221A - 电子封装件 - Google Patents

电子封装件 Download PDF

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Publication number
CN113363221A
CN113363221A CN202010175389.9A CN202010175389A CN113363221A CN 113363221 A CN113363221 A CN 113363221A CN 202010175389 A CN202010175389 A CN 202010175389A CN 113363221 A CN113363221 A CN 113363221A
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Prior art keywords
electronic
package
layer
electronic package
electronic components
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Pending
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CN202010175389.9A
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English (en)
Inventor
陈麒任
许智勋
潘嘉伟
林长甫
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN113363221A publication Critical patent/CN113363221A/zh
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Abstract

本发明涉及一种电子封装件，包括一包含有多个电子元件的多芯片封装体以及一布设于该多芯片封装体上的应力缓冲层，且该应力缓冲层接触该多个电子元件，使应力平均分散于该应力缓冲层而不会集中于特定区域，避免结构应力集中于该些电子元件的角落处。

Description

电子封装件
技术领域
本发明有关一种封装结构，尤指一种散热型电子封装件。
背景技术
随着科技的演进，电子产品需求趋势朝向异质整合迈进，为此，多芯片封装结构(MCM/MCP)逐渐兴起。
如图1所示的多芯片封装结构1，用于将多个半导体芯片11经由多个焊锡凸块13结合至一封装基板10上，并以底胶14包覆该些焊锡凸块13及该多个半导体芯片11。以经由将多颗半导体芯片11封装成一模块，使其具有较多的I/O数，且可以大幅增加处理器的运算能力，减少信号传递的延迟时间，以应用于高密度线路/高传输速度/高叠层数/大尺寸设计的高阶产品。
然而，如图1所示的多芯片封装结构1(其图中省略封装胶体及散热件)，随着功能需求愈来愈多，该半导体芯片11的数量亦愈来愈多，因而该封装基板10的整体平面封装面积也愈来愈大，故于高温时，整体结构会呈笑脸(如图所示的虚线路径L1)翘曲状，而于室温时，则呈哭脸(如图所示的虚线路径L2)翘曲状，造成该多芯片封装结构1多次拉伸(如图所示的箭头方向X1)或收缩(如图所示的箭头方向X2)的变化，以致于因各该半导体芯片11之间的应力不连续的情况而导致于该半导体芯片11的角落处的应力会过大，致使各该半导体芯片11之间的底胶14之处容易发生断裂，因而造成产品可靠度不佳及制程良率低的问题。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件，避免结构应力集中于电子元件的角落处。
本发明的电子封装件包括：多芯片封装体，其包含有多个电子元件及结合该多个电子元件的包覆层；以及应力缓冲层，其布设于该多芯片封装体上以接触该多个电子元件及该包覆层。
前述的电子封装件中，该多个电子元件的至少二者为相互分离地配置。
前述的电子封装件中，该包覆层形成于任二该电子元件之间。
前述的电子封装件中，该包覆层为底胶。
前述的电子封装件中，该多芯片封装体还包含有承载及电性连接该多个电子元件的承载结构，且该包覆层形成于该承载结构上。例如，该承载结构为无核心层形式线路结构。
前述的电子封装件中，该多芯片封装体还包含有包覆该多个电子元件及该包覆层的封装层。例如，该应力缓冲层还接触该封装层。或者，该电子元件的一表面齐平该封装层的上表面。
前述的电子封装件中，还包括结合至该多个电子元件上的散热件。例如，该散热件经由散热材结合至该应力缓冲层上。或者，该应力缓冲层设于该多个电子元件与该散热件之间。
前述的电子封装件中，该应力缓冲层为金属层。
由上可知，本发明的电子封装件主要经由该应力缓冲层布设于该多芯片封装体上，以连接各该电子元件的非作用面及包覆层的表面，使应力平均分散于该应力缓冲层而不会集中于特定区域，故相比于现有技术，本发明的电子封装件能有效避免结构应力集中于该些电子元件的角落处，进而避免该些电子元件或包覆层发生碎裂而导致可靠性不佳及制程良率低的问题。
附图说明
图1为现有多芯片封装结构的剖视示意图。
图2为本发明的电子封装件的剖视示意图。
图2’为图2的局部放大图。
附图标记说明
1 多芯片封装结构 10,3 封装基板
11 半导体芯片 13 焊锡凸块
14,260 底胶 2 电子封装件
2a 多芯片封装体 20 承载结构
20a 第一侧 20b 第二侧
200 绝缘层 201 线路层
21,21’ 电子元件 21a 作用面
21b 非作用面 21c 侧面
210 电极垫 211 导电凸块
212 包覆层 212a 上表面
22 封装层 22a 第一表面
22b 第二表面 23 散热件
230 散热体 231 支撑脚
24 应力缓冲层 25 散热材
26 导电体 27 粘着层
30 导电元件 L1,L2 虚线路径
X1,X2 箭头方向。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2及图2’为本发明的电子封装件2的剖面示意图。如图2及图2’所示，所述的电子封装件2包括：一多芯片封装体2a(其包括一承载结构20、多个电子元件21,21’及封装层22)、一应力缓冲层24、一散热材25以及一散热件23。
所述的承载结构20为载板形式，其例如为具有核心层的封装基板、无核心层(coreless)形式线路结构、具导电硅穿孔(Through-siliconvia，简称TSV)的硅中介板(Through Silicon interposer，简称TSI)或其它板型。
于本实施例中，该承载结构20为无核心层形式线路结构，其包含至少一绝缘层200及至少一结合该绝缘层200的线路层201，如至少一扇出(fan out)型重布线路层(redistribution layer，简称RDL)。应可理解地，该承载结构20亦可为其它承载芯片的板材，如导线架(lead frame)、晶圆(wafer)、或其它具有金属布线(routing)的板体等，并不限于上述。
此外，该承载结构20具有相对的第一侧20a与第二侧20b，且于其第二侧20b可形成多个导电体26，以供该电子封装件2可经由该些导电体26接置一封装基板3，并可由底胶260包覆该些导电体26。或者，该电子封装件2可经由该些导电体26接置一如电路板的电子装置(图略)。例如，该导电体26可为如铜柱的金属柱、包覆有绝缘块的金属凸块、焊球(solderball)、具有核心铜球(Cu core ball)的焊球或其它导电构造等。
另外，该承载结构20的载板制程方式繁多，例如，可采用晶圆制程制作线路层201，通过化学气相沉积(Chemical vapor deposition，简称CVD)形成氮化硅或氧化硅以作为绝缘层200；或者，可采用一般非晶圆制程方式形成线路层201，即采用成本较低的高分子介电材作为绝缘层200，如聚酰亚胺(Polyimide，简称PI)、聚对二唑苯(Polybenzoxazole，简称PBO)、预浸材(Prepreg，简称PP)、封装胶体(molding compound)、感光型介电层或其它材料等以涂布方式形成。
所述的多个电子元件21,21’为相互分离地配置于该承载结构20的第一侧20a，且该电子元件21,21’为主动元件、被动元件或其组合者，其中，该主动元件例如为半导体芯片，而该被动元件例如为电阻、电容及电感。
于本实施例中，该些电子元件21,21’为半导体芯片，其具有相对的作用面21a与非作用面21b，并使该作用面21a的电极垫210经由多个如焊锡材料、金属柱(pillar)或其它等的导电凸块211以覆晶方式设于该承载结构20的第一侧20a的线路层201上并电性连接该线路层201，且以如底胶的包覆层212包覆该些导电凸块211；或者，该电子元件21,21’可经由多个焊线(图未示)以打线方式电性连接该承载结构20的线路层201；亦或，该电子元件21,21’可直接接触该承载结构20的线路层201。因此，可于该承载结构20上接置所需类型及数量的电子元件，以提升其电性功能，且有关电子元件21,21’电性连接承载结构20的方式繁多，并不限于上述。
此外，该包覆层212还形成于各该电子元件21,21’之间，如沿该电子元件21,21’的侧面21c延伸布设，且各该电子元件21,21’的非作用面21b齐平该包覆层212的上表面212a。
所述的封装层22形成于该承载结构20的第一侧20a上以包覆该电子元件21,21’与该包覆层212。
于本实施例中，该封装层22具有相对的第一表面22a与第二表面22b，并以该第一表面22a结合该承载结构20的第一侧20a，且该电子元件21的非作用面21b齐平该封装层22的第二表面22b，以令该些电子元件21外露于该封装层22的第二表面22b。
此外，形成该封装层22的材料为绝缘材，如聚酰亚胺(PI)、环氧树脂(epoxy)的封装胶体或封装材，其可用模压(molding)、压合(lamination)或涂布(coating)的方式形成。
所述的应力缓冲层24布设于该多芯片封装体2a上以接触该多个电子元件21,21’及该包覆层212。
于本实施例中，该应力缓冲层24为金属层，如铜，且以溅镀(Sputter)或其它方式形成于各该电子元件21,21’的非作用面21b、该包覆层212的上表面212a及该封装层22的第二表面22b上，以接触该多个电子元件21,21’、该包覆层212及该封装层22。
此外，以溅镀方式形成该应力缓冲层24，不仅可降低制作成本，且制程简单，因而易于大量制作。
所述的散热材25布设于该应力缓冲层24上，且该散热材25为导热介面材(ThermalInterface Material，简称TIM)，如高导热金属胶材。
所述的散热件23经由该散热材25结合至该应力缓冲层24上，以令该散热件23、散热材25与该应力缓冲层24作为该些电子元件21,21’的散热机制。
于本实施例中，该散热件23具有一散热体230与多个设于该散热体230下侧的支撑脚231，该散热体230为散热片型式，并以下侧接触该散热材25，且该支撑脚231经由粘着层27结合于该封装基板3上或承载结构20的第一侧20a上。应可理解地，有关该散热件23的态样繁多，如片体型(无支撑脚231)，并不限于上述。
此外，该应力缓冲层24设于该多个电子元件21,21’与该散热件23之间。
另外，于后续制程中，可植设多个导电元件30于该封装基板3下侧，以经由该些导电元件30接置一如电路板的电子装置(图略)。例如，该导电元件30可为如铜柱的金属柱、包覆有绝缘块的金属凸块、焊球(solder ball)、具有核心铜球(Cu core ball)的焊球或其它导电构造等。
综上所述，本发明的电子封装件2，主要经由该应力缓冲层24布设于该多芯片封装体2a上，以连接各该电子元件21,21’的非作用面21b及包覆层212的上表面212a，使应力平均分散于该应力缓冲层24而不会集中于特定区域，故相比于现有技术，本发明的电子封装件2于该承载结构20的整体平面封装面积愈大时，能有效避免结构应力集中于该些电子元件21,21’的角落处，进而避免该些电子元件21,21’或包覆层212发生碎裂而导致可靠性不佳及制程良率低的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (13)

1.一种电子封装件，其特征在于，包括：
多芯片封装体，其包含有多个电子元件及结合该多个电子元件的包覆层；以及
应力缓冲层，其布设于该多芯片封装体上以接触该多个电子元件及该包覆层。
2.根据权利要求1所述的电子封装件，其特征在于，该多个电子元件的至少二者为相互分离地配置。
3.根据权利要求1所述的电子封装件，其特征在于，该包覆层形成于任二该电子元件之间。
4.根据权利要求1所述的电子封装件，其特征在于，该包覆层为底胶。
5.根据权利要求1所述的电子封装件，其特征在于，该多芯片封装体还包含有承载及电性连接该多个电子元件的承载结构，且该包覆层形成于该承载结构上。
6.根据权利要求5所述的电子封装件，其特征在于，该承载结构为无核心层形式线路结构。
7.根据权利要求1所述的电子封装件，其特征在于，该多芯片封装体还包含有包覆该多个电子元件及该包覆层的封装层。
8.根据权利要求7所述的电子封装件，其特征在于，该应力缓冲层还接触该封装层。
9.根据权利要求7所述的电子封装件，其特征在于，该电子元件的一表面为齐平该封装层的上表面。
10.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括结合至该多个电子元件上的散热件。
11.根据权利要求10所述的电子封装件，其特征在于，该散热件经由散热材结合至该应力缓冲层上。
12.根据权利要求10所述的电子封装件，其特征在于，该应力缓冲层设于该多个电子元件与该散热件之间。
13.根据权利要求1所述的电子封装件，其特征在于，该应力缓冲层为金属层。
CN202010175389.9A 2020-03-06 2020-03-13 电子封装件 Pending CN113363221A (zh)

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