TWI552277B - 半導體封裝件及其製法 - Google Patents
半導體封裝件及其製法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 80
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 title claims description 10
- 239000008393 encapsulating agent Substances 0.000 claims description 30
- 239000010410 layer Substances 0.000 claims description 27
- 239000012790 adhesive layer Substances 0.000 claims description 23
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 239000000084 colloidal system Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 34
- 230000000694 effects Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000003491 array Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係有關於一種半導體封裝件及其製法,尤指一種內埋有板體的半導體封裝件及其製法。
隨著半導體技術的演進,已開發出半導體產品的不同封裝產品型態,而為了追求半導體封裝件之輕薄短小,因而發展出一種晶片尺寸封裝件(Chip Scale Package,CSP),其特徵在於此種晶片尺寸封裝件僅具有與晶片尺寸相等或略大的尺寸。
第1A至1D圖所示者,係習知半導體封裝件之製法的剖視圖。
如第1A圖所示,提供一第一承載板10,並於其上依序形成離型層11與第一黏著層12。
如第1B圖所示,於該第一黏著層12上以覆晶方式設置複數具有相對之作用面13a與非作用面13b的半導體晶片13,令該半導體晶片13以其作用面13a接置於該第一黏著層12上。
如第1C圖所示,於該第一黏著層12上形成封裝膠體
14,以包覆該等半導體晶片13,並經過固化(curing)步驟以使該封裝膠體14固化,該封裝膠體14具有連接該第一黏著層12的第一表面14a及與其相對之第二表面14b。
如第1D圖所示,於該封裝膠體14之第二表面14b上依序接置第二黏著層15與第二承載板16,並移除該第一承載板10、離型層11與第一黏著層12,以外露該第一表面14a與作用面13a。
最後,於該第一表面與作用面上形成電性連接該半導體晶片的線路重佈層,再移除該第二承載板,並進行切單步驟,以得到複數半導體封裝件。(未圖示此步驟)
惟,於前述習知半導體封裝件之製程中,對封裝膠體進行固化步驟後,因封裝膠體的熱膨脹係數與第一承載板的熱膨脹係數差異過大,所以會產生翹曲(warpage)現象(如第1D圖所示),因此必須額外貼附第二承載板,以平衡應力並減小翹曲程度,之後方可於半導體晶片之作用面及封裝膠體之第一表面上形成線路重佈層,然而這樣會增加整體製程成本及時間。
因此,如何避免上述習知技術中之種種問題,實為目前業界所急需解決的課題。
有鑒於上述習知技術之缺失,本發明提供一種半導體封裝件,係包括:板體;半導體晶片,係具有相對之作用面與非作用面,且以其非作用面接置於該板體上;以及封裝膠體,係包覆該板體與半導體晶片,且該封裝膠體具有
相對之第一表面與第二表面,該第一表面外露該半導體晶片之作用面。
於前述之半導體封裝件中,復包括線路重佈層,係形成於該第一表面上,且電性連接該半導體晶片,並復包括複數導電元件,係形成於該線路重佈層上。
於本發明中,該板體係為氧化鋁板,該板體復具有貫穿之圖案化通口,且該封裝膠體復填入該圖案化通口中,又該圖案化通口係使該板體呈網狀,該封裝膠體之側表面係與該板體之側表面齊平。
本發明復提供一種半導體封裝件之製法,係包括:於一承載板上設置具有相對之作用面與非作用面的半導體晶片,令該半導體晶片以其作用面接置於該承載板上;於該半導體晶片的非作用面上接置板體;於該承載板上形成封裝膠體,以包覆該板體與半導體晶片,該封裝膠體具有連接該承載板的第一表面及與其相對之第二表面;以及移除該承載板,以外露該半導體晶片的作用面與該封裝膠體之第一表面。
於前述之半導體封裝件之製法中,復包括於該外露之第一表面上形成電性連接該半導體晶片的線路重佈層,於形成該線路重佈層之後,復包括進行切單步驟,且於進行該切單步驟之後,該封裝膠體之側表面係與該板體之側表面齊平,並復包括於該線路重佈層上形成複數導電元件,且該板體係為氧化鋁板。
本發明之半導體封裝件之製法中,該板體復具有貫穿
之圖案化通口,且該封裝膠體復填入該圖案化通口中,該圖案化通口係使該板體呈網狀,又於設置該半導體晶片之前,該承載板上復依序形成有離型層與黏著層,令該半導體晶片以其作用面接置於該黏著層上,且移除該承載板復包括移除該離型層與黏著層。
由上可知,本發明係於半導體晶片的非作用面上接置板體,以平衡應力、增加整體結構強度與提高半導體晶片的散熱效果,使得半導體封裝件於固化步驟後不會翹曲,且無須接置與移除第二個承載板,故可減少製程時間與成本,增加生產效率。
10‧‧‧第一承載板
11、21‧‧‧離型層
12‧‧‧第一黏著層
13、23‧‧‧半導體晶片
13a、23a‧‧‧作用面
13b、23b‧‧‧非作用面
14、25‧‧‧封裝膠體
14a、25a‧‧‧第一表面
14b、25b‧‧‧第二表面
15‧‧‧第二黏著層
16‧‧‧第二承載板
20‧‧‧承載板
22‧‧‧黏著層
24‧‧‧板體
240‧‧‧圖案化通口
26‧‧‧線路重佈層
27‧‧‧導電元件
第1A至1D圖所示者係習知半導體封裝件之製法的剖視圖;以及第2A至2F圖所示者係本發明之半導體封裝件之製法的剖視圖,其中,第2C’圖係第2C圖之板體的俯視圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功
效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之用語亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2F圖所示者,係本發明之半導體封裝件之製法的剖視圖。
如第2A圖所示,於一承載板20上視需要依序形成有離型層21與黏著層22,形成該承載板20之材質可為玻璃。
如第2B圖所示,於該黏著層22上設置具有相對之作用面23a與非作用面23b的半導體晶片23,令該半導體晶片23以其作用面23a接置於該黏著層22上。
如第2C圖所示,於該半導體晶片23的非作用面23b上接置具有複數貫穿之奈米孔(未圖示)的板體24,該奈米孔之孔徑在100奈米以下,該板體24係為具有較佳散熱性之陽極氧化鋁(anodic aluminum oxide,AAO)板,該等奈米孔可為六邊形(hexagon)高規則奈米孔洞陣列,其孔道筆直均勻且散熱性佳,其中,第2C’圖係板體24之俯視圖,該板體24復具有貫穿之圖案化通口240,該圖案化通口240係使該板體24呈網狀。
如第2D圖所示,於該黏著層22上形成封裝膠體25,以包覆該板體24與半導體晶片23,該封裝膠體25具有連接該黏著層22的第一表面25a及與其相對之第二表面25b,且該封裝膠體25復填入該圖案化通口240中,該圖
案化通口240係使得便於填充該封裝膠體25。
如第2E圖所示,移除該承載板20、離型層21與黏著層22,以外露該半導體晶片23的作用面23a與該封裝膠體25之第一表面25a。
如第2F圖所示,於該第一表面25a上形成電性連接該半導體晶片23的線路重佈層26,再進行切單步驟,並於該線路重佈層26上形成複數導電元件27,該導電元件27可為銲球,該封裝膠體25之側表面係與該板體24之側表面齊平;該切單步驟亦可於形成該等導電元件27後才進行。
本發明之半導體封裝件,係包括:板體24;半導體晶片23,係具有相對之作用面23a與非作用面23b,且以其非作用面23b接置於該板體24上;以及封裝膠體25,係包覆該板體24與半導體晶片23,且具有相對之第一表面25a與第二表面25b,該第一表面25a外露該半導體晶片23之作用面23a。
於前述之半導體封裝件中,復包括線路重佈層26,係形成於該第一表面25a上,且電性連接該半導體晶片23,並復包括複數導電元件27,係形成於該線路重佈層26上。
於本實施例中,該板體24係為氧化鋁板,該板體24復具有貫穿之圖案化通口240,且該封裝膠體25復填入該圖案化通口240中,又該圖案化通口240係使該板體24呈網狀,該封裝膠體25之側表面係與該板體24之側表面齊平。
綜上所述,相較於習知技術,由於本發明係於半導體晶片的非作用面上接置具有複數貫穿之奈米孔的板體,以平衡應力與增加整體結構強度,使得半導體封裝件於固化步驟後不會翹曲,而無須接置第二個承載板,進而無須移除該第二個承載板,故可減少製程時間與成本,增加生產效率;此外,由於該板體係連接該半導體晶片的非作用面,所以能增進散熱效果。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
23‧‧‧半導體晶片
23a‧‧‧作用面
23b‧‧‧非作用面
24‧‧‧板體
25‧‧‧封裝膠體
25a‧‧‧第一表面
25b‧‧‧第二表面
Claims (16)
- 一種半導體封裝件,係包括:板體;半導體晶片,係具有相對之作用面與非作用面,且以其非作用面接置於該板體上;以及封裝膠體,係包覆該板體與半導體晶片,且該封裝膠體具有相對之第一表面與第二表面,該第一表面外露該半導體晶片之作用面。
- 如申請專利範圍第1項所述之半導體封裝件,復包括線路重佈層,係形成於該第一表面上,且電性連接該半導體晶片。
- 如申請專利範圍第2項所述之半導體封裝件,復包括複數導電元件,係形成於該線路重佈層上。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該板體係為氧化鋁板。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該板體復具有貫穿之圖案化通口,且該封裝膠體復填入該圖案化通口中。
- 如申請專利範圍第5項所述之半導體封裝件,其中,該圖案化通口係使該板體呈網狀。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該封裝膠體之側表面係與該板體之側表面齊平。
- 一種半導體封裝件之製法,係包括:於一承載板上設置具有相對之作用面與非作用面 的半導體晶片,令該半導體晶片以其作用面接置於該承載板上;於該半導體晶片的非作用面上接置板體;於該承載板上形成封裝膠體,以包覆該板體與半導體晶片,該封裝膠體具有連接該承載板的第一表面及與其相對之第二表面;以及移除該承載板,以外露該半導體晶片的作用面與該封裝膠體之第一表面。
- 如申請專利範圍第8項所述之半導體封裝件之製法,復包括於該外露之第一表面上形成電性連接該半導體晶片的線路重佈層。
- 如申請專利範圍第9項所述之半導體封裝件之製法,於形成該線路重佈層之後,復包括進行切單步驟。
- 如申請專利範圍第10項所述之半導體封裝件之製法,於進行該切單步驟之後,該封裝膠體之側表面係與該板體之側表面齊平。
- 如申請專利範圍第9項所述之半導體封裝件之製法,復包括於該線路重佈層上形成複數導電元件。
- 如申請專利範圍第8項所述之半導體封裝件之製法,其中,該板體係為氧化鋁板。
- 如申請專利範圍第8項所述之半導體封裝件之製法,其中,該板體復具有貫穿之圖案化通口,且該封裝膠體復填入該圖案化通口中。
- 如申請專利範圍第14項所述之半導體封裝件之製法, 其中,該圖案化通口係使該板體呈網狀。
- 如申請專利範圍第8項所述之半導體封裝件之製法,於設置該半導體晶片之前,該承載板上復依序形成有離型層與黏著層,令該半導體晶片以其作用面接置於該黏著層上,且移除該承載板復包括移除該離型層與黏著層。
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