CN105280573B - 半导体封装件的制法 - Google Patents

半导体封装件的制法 Download PDF

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CN105280573B
CN105280573B CN201410311771.2A CN201410311771A CN105280573B CN 105280573 B CN105280573 B CN 105280573B CN 201410311771 A CN201410311771 A CN 201410311771A CN 105280573 B CN105280573 B CN 105280573B
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CN105280573A (zh
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陈威宇
詹慕萱
林畯棠
林泽源
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Siliconware Precision Industries Co Ltd
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Abstract

一种半导体封装件及其制法,该半导体封装件包括板体、半导体晶片与封装胶体,该半导体晶片具有相对的作用面与非作用面,且以其非作用面接置于该板体上,该封装胶体包覆该板体与半导体晶片,且具有相对的第一表面与第二表面,该第一表面外露该半导体晶片的作用面。本发明能有效增进结构强度,以防止半导体封装件翘曲。

Description

半导体封装件的制法
技术领域
本发明涉及一种半导体封装件的制法,尤指一种内埋有板体的半导体封装件及其制法。
背景技术
随着半导体技术的演进,已开发出半导体产品的不同封装产品型态,而为了追求半导体封装件的轻薄短小,因而发展出一种晶片尺寸封装件(Chip Scale Package,CSP),其特征在于此种晶片尺寸封装件仅具有与晶片尺寸相等或略大的尺寸。
图1A至图1D所示者,为现有半导体封装件的制法的剖视图。
如图1A所示,提供一第一承载板10,并于其上依序形成离型层11与第一粘着层12。
如图1B所示,于该第一粘着层12上以覆晶方式设置多个具有相对的作用面13a与非作用面13b的半导体晶片13,令该半导体晶片13以其作用面13a接置于该第一粘着层12上。
如图1C所示,于该第一粘着层12上形成封装胶体14,以包覆该等半导体晶片13,并经过固化(curing)步骤以使该封装胶体14固化,该封装胶体14具有连接该第一粘着层12的第一表面14a及与其相对的第二表面14b。
如图1D所示,于该封装胶体14的第二表面14b上依序接置第二粘着层15与第二承载板16,并移除该第一承载板10、离型层11与第一粘着层12,以外露该第一表面14a与作用面13a。
最后,于该第一表面与作用面上形成电性连接该半导体晶片的线路重布层,再移除该第二承载板,并进行切单步骤,以得到多个半导体封装件。(未图示此步骤)
惟,于前述现有半导体封装件的制程中,对封装胶体进行固化步骤后,因封装胶体的热膨胀系数与第一承载板的热膨胀系数差异过大,所以会产生翘曲(warpage)现象(如图1D所示),因此必须额外贴附第二承载板,以平衡应力并减小翘曲程度,之后方可于半导体晶片的作用面及封装胶体的第一表面上形成线路重布层,然而这样会增加整体制程成本及时间。
因此,如何避免上述现有技术中的种种问题,实为目前业界所急需解决的课题。
发明内容
有鉴于上述现有技术的缺失,本发明的目的为提供一种半导体封装件及其制法,能有效增进结构强度,以防止半导体封装件翘曲。
本发明的半导体封装件包括:板体;半导体晶片,其具有相对的作用面与非作用面,且以其非作用面接置于该板体上;以及封装胶体,其包覆该板体与半导体晶片,且该封装胶体具有相对的第一表面与第二表面,该第一表面外露该半导体晶片的作用面。
于前述的半导体封装件中,还包括线路重布层,其形成于该第一表面上,且电性连接该半导体晶片,并包括多个导电元件,其形成于该线路重布层上。
于本发明中,该板体为氧化铝板,该板体还具有贯穿的图案化通口,且该封装胶体还填入该图案化通口中,又该图案化通口用于使该板体呈网状,该封装胶体的侧表面与该板体的侧表面齐平。
本发明还提供一种半导体封装件的制法,包括:于一承载板上设置具有相对的作用面与非作用面的半导体晶片,令该半导体晶片以其作用面接置于该承载板上;于该半导体晶片的非作用面上接置板体;于该承载板上形成封装胶体,以包覆该板体与半导体晶片,该封装胶体具有连接该承载板的第一表面及与其相对的第二表面;以及移除该承载板,以外露该半导体晶片的作用面与该封装胶体的第一表面。
于前述的半导体封装件的制法中,还包括于该外露的第一表面上形成电性连接该半导体晶片的线路重布层,于形成该线路重布层之后,还包括进行切单步骤,且于进行该切单步骤之后,该封装胶体的侧表面与该板体的侧表面齐平,并包括于该线路重布层上形成多个导电元件,且该板体为氧化铝板。
本发明的半导体封装件的制法中,该板体还具有贯穿的图案化通口,且该封装胶体还填入该图案化通口中,该图案化通口用于使该板体呈网状,又于设置该半导体晶片之前,该承载板上还依序形成有离型层与粘着层,令该半导体晶片以其作用面接置于该粘着层上,且移除该承载板还包括移除该离型层与粘着层。
由上可知,本发明通过于半导体晶片的非作用面上接置板体,以平衡应力、增加整体结构强度与提高半导体晶片的散热效果,使得半导体封装件于固化步骤后不会翘曲,且无须接置与移除第二个承载板,故可减少制程时间与成本,增加生产效率。
附图说明
图1A至图1D所示者为现有半导体封装件的制法的剖视图。
图2A至图2F所示者为本发明的半导体封装件的制法的剖视图,其中,图2C’为图2C的板体的俯视图。
符号说明
10 第一承载板
11、21 离型层
12 第一粘着层
13、23 半导体晶片
13a、23a 作用面
13b、23b 非作用面
14、25 封装胶体
14a、25a 第一表面
14b、25b 第二表面
15 第二粘着层
16 第二承载板
20 承载板
22 粘着层
24 板体
240 图案化通口
26 线路重布层
27 导电元件。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用于配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用于限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的用语也仅为便于叙述的明了,而非用于限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2F所示者,为本发明的半导体封装件的制法的剖视图。
如图2A所示,于一承载板20上视需要依序形成有离型层21与粘着层22,形成该承载板20的材质可为玻璃。
如图2B所示,于该粘着层22上设置具有相对的作用面23a与非作用面23b的半导体晶片23,令该半导体晶片23以其作用面23a接置于该粘着层22上。
如图2C所示,于该半导体晶片23的非作用面23b上接置具有多个贯穿的纳米孔(未图示)的板体24,该纳米孔的孔径在100纳米以下,该板体24为具有较佳散热性的阳极氧化铝(anodic aluminum oxide,AAO)板,该等纳米孔可为六边形(hexagon)高规则纳米孔洞阵列,其孔道笔直均匀且散热性佳,其中,图2C’为板体24的俯视图,该板体24还具有贯穿的图案化通口240,该图案化通口240用于使该板体24呈网状。
如图2D所示,于该粘着层22上形成封装胶体25,以包覆该板体24与半导体晶片23,该封装胶体25具有连接该粘着层22的第一表面25a及与其相对的第二表面25b,且该封装胶体25还填入该图案化通口240中,该图案化通口240用于使得便于填充该封装胶体25。
如图2E所示,移除该承载板20、离型层21与粘着层22,以外露该半导体晶片23的作用面23a与该封装胶体25的第一表面25a。
如图2F所示,于该第一表面25a上形成电性连接该半导体晶片23的线路重布层26,再进行切单步骤,并于该线路重布层26上形成多个导电元件27,该导电元件27可为焊球,该封装胶体25的侧表面与该板体24的侧表面齐平;该切单步骤也可于形成该等导电元件27后才进行。
本发明的半导体封装件包括:板体24;半导体晶片23,其具有相对的作用面23a与非作用面23b,且以其非作用面23b接置于该板体24上;以及封装胶体25,其包覆该板体24与半导体晶片23,且具有相对的第一表面25a与第二表面25b,该第一表面25a外露该半导体晶片23的作用面23a。
于前述的半导体封装件中,还包括线路重布层26,其形成于该第一表面25a上,且电性连接该半导体晶片23,并包括多个导电元件27,其形成于该线路重布层26上。
于本实施例中,该板体24为氧化铝板,该板体24还具有贯穿的图案化通口240,且该封装胶体25还填入该图案化通口240中,又该图案化通口240用于使该板体24呈网状,该封装胶体25的侧表面与该板体24的侧表面齐平。
综上所述,相较于现有技术,由于本发明通过于半导体晶片的非作用面上接置具有多个贯穿的纳米孔的板体,以平衡应力与增加整体结构强度,使得半导体封装件于固化步骤后不会翘曲,而无须接置第二个承载板,进而无须移除该第二个承载板,故可减少制程时间与成本,增加生产效率;此外,由于该板体连接该半导体晶片的非作用面,所以能增进散热效果。
上述实施例仅用于例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。

Claims (9)

1.一种半导体封装件的制法,其包括:
于一承载板上设置具有相对的作用面与非作用面的多个半导体晶片,令该多个半导体晶片以其作用面接置于该承载板上;
于该多个半导体晶片的非作用面上接置一单一板体;
于该承载板上形成封装胶体,以包覆该板体与多个半导体晶片,该封装胶体具有连接该承载板的第一表面及与其相对的第二表面;以及
移除该承载板,以外露该多个半导体晶片的作用面与该封装胶体的第一表面。
2.如权利要求1所述的半导体封装件的制法,其特征在于,该制法还包括于该外露的第一表面上形成电性连接该多个半导体晶片的线路重布层。
3.如权利要求2所述的半导体封装件的制法,其特征在于,于形成该线路重布层之后,还包括进行切单步骤。
4.如权利要求3所述的半导体封装件的制法,其特征在于,于进行该切单步骤之后,该封装胶体的侧表面与该板体的侧表面齐平。
5.如权利要求2所述的半导体封装件的制法,其特征在于,该制法还包括于该线路重布层上形成多个导电元件。
6.如权利要求1所述的半导体封装件的制法,其特征在于,该板体为氧化铝板。
7.如权利要求1所述的半导体封装件的制法,其特征在于,该板体还具有贯穿的图案化通口,且该封装胶体也填入该图案化通口中。
8.如权利要求7所述的半导体封装件的制法,其特征在于,该图案化通口用于使该板体呈网状。
9.如权利要求1所述的半导体封装件的制法,其特征在于,于设置该多个半导体晶片之前,该承载板上还依序形成有离型层与粘着层,令该多个半导体晶片以其作用面接置于该粘着层上,且移除该承载板还包括移除该离型层与粘着层。
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