TWI717407B - 包括高密度互連橋之封裝配置 - Google Patents

包括高密度互連橋之封裝配置 Download PDF

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TWI717407B
TWI717407B TW105134851A TW105134851A TWI717407B TW I717407 B TWI717407 B TW I717407B TW 105134851 A TW105134851 A TW 105134851A TW 105134851 A TW105134851 A TW 105134851A TW I717407 B TWI717407 B TW I717407B
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die
interconnection bridge
bridge
interconnection
redistribution layers
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TW105134851A
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TW201727773A (zh
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隆清 王
莉娟 張
羅瑞 希南
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新加坡商馬維爾亞洲私人有限公司
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Abstract

實施例提供一種封裝配置，該封裝配置包括高密度互連橋，該高密度互連橋用於互連該封裝配置內之晶粒。該封裝配置包含一或多個再分佈層及嵌入該一或多個再分佈層內之互連橋。第一晶粒耦接至(i)該一或多個再分佈層之第一部分及(ii)該互連橋之第一部分。第二晶粒耦接至(ii)該一或多個再分佈層之第二部分及(ii)該互連橋之第二部分，以便至少經由第一互連橋電氣耦接該第一晶粒及該第二晶粒。

Description

包括高密度互連橋之封裝配置 【相關申請案之交互參照】
本申請案要求2016年2月3日申請之美國臨時專利申請案第62/290,722號及2015年10月29日申請之美國臨時專利申請案第62/247,864號之優先權，該等申請案以全文引用方式併入本文中。
本揭露內容之實施例係關於半導體封裝配置，且尤其係關於包括高密度互連橋之封裝配置，該高密度互連橋用於互連該封裝配置內之晶粒。
用於半導體裝置之封裝配置往往在封裝內包括大量半導體裝置。一些半導體裝置可能需要相對於封裝內之其他半導體裝置及組件的高密度互連。然而，用於創建並提供此類高密度互連之材料可為昂貴及/或複雜的。
在各種實施例中，本揭露內容提供一種封裝配置，該封裝配置包含一或多個再分佈層及嵌入該一或多個再分佈層內之互連橋。第一晶粒耦接至(i)該一或多個再分佈層之第一部分及(ii)該互連橋之第一部分。第二晶粒耦接至(ii)該一或多個再分佈層之第二部分及(ii)該互連橋之第二部分，以便至少經由第一互連橋電氣耦接該第一晶粒及該第二晶粒。
在各種實施例中，本揭露內容亦提供一種方法，該方法包含提供載體，以及將互連橋耦接至該載體。圍繞互連橋在載體上形成一或多個再分佈層，且在互連橋及一或多個再分佈層上形成銅柱。將第一晶粒耦接至互連橋上之第一組銅柱及一或多個再分佈層上之第一組銅柱。將第二 晶粒耦接至互連橋上之第二組銅柱及一或多個再分佈層上之第二組銅柱。移除載體。
結合隨附圖式藉由以下詳細描述將容易理解本揭露內容之實施例。為便於此描述，相同參考數字指定相同結構元件。各種實施例在隨附圖式之諸圖中藉由實例之方式而非藉由限制之方式加以例示。
圖1A示意性地例示根據實施例之包括高密度互連橋的封裝配置之平台的俯視圖。
圖1B示意性地例示根據實施例之圖1A的封裝配置沿著線B’-B’所見之橫截面視圖。
圖2示意性地例示根據實施例之包括高密度互連橋的另一封裝配置之俯視圖。
圖3為根據實施例之用於製作包括高密度互連橋的封裝配置之示例性方法的流程圖。
圖1A示意性地例示封裝配置100之平台的俯視圖，該封裝配置100包括載體102及載體102之頂部表面上的一或多個再分佈層104。如此處將進一步論述，最終將自封裝配置100移除載體102。將第一晶粒106、第二晶粒108及第三晶粒110配置在載體102上。第一晶粒106經由第一互連橋112電氣地或通訊地耦接至第二晶粒108。第一晶粒106亦經由第二互連橋114電氣地或通訊地耦接至第三晶粒110。第一晶粒106、第二晶粒108及第三晶粒110通常為半導體裝置，該等半導體裝置通常經組配來提供例如處理器、處理核心、各種類型之記憶體、系統單晶片(SOC)等。
第一互連橋112通常經組配來提供第一晶粒106與第二晶粒108之間的高密度互連。第二互連橋114通常經組配來提供第一晶粒106與第三晶粒110之間的高密度互連。例如，互連橋112、114可經組配來允許互連具有兩微米或兩微米以下之尺寸，及各種互連之間兩微米或兩微米以下之間距。在實施例中，互連橋包含矽。
圖1B為圖1A之封裝配置100沿著線B’-B’所見的橫截面視 圖。如可見，第一晶粒106及第二晶粒108經由第一銅圓柱或銅柱116耦接至第一互連橋112。在第一晶粒106及第二晶粒108上可包括通常呈銅凸塊形式之微凸塊118，以允許將第一晶粒106及第二晶粒108倒裝晶片附接至第一銅柱116上。另外，提供第二銅圓柱或銅柱120以便將第一晶粒106及第二晶粒108電氣地或通訊地耦接至一或多個再分佈層104。再次，可在第一晶粒106及第二晶粒108上提供通常呈銅凸塊形式之微凸塊122，以允許在將第一晶粒及第二晶粒倒裝晶片附接至第一銅柱116的同時，將第一晶粒106及第二晶粒108倒裝晶片附接至第二銅柱120上。或者，可將微凸塊118及微凸塊122分別置放於第一銅柱116及第二銅柱120上，以便在必要時倒裝晶片附接第一晶粒106及第二晶粒108。在實施例中，銅柱120通常允許大於兩微米的互連密度。因此，銅柱120之尺寸通常大於兩微米，且彼此間隔大於兩微米。
儘管在圖1B中未例示，但第一晶粒106及第三晶粒110耦接至將第一晶粒106耦接至第二互連橋114之銅柱(類似於銅柱116及微凸塊118)。此外，第三晶粒110亦附接至將第三晶粒110耦接至一或多個再分佈層104之銅柱(類似於銅柱120及微凸塊122)。因此，第一晶粒106經由第一互連橋112電氣地或通訊地耦接至第二晶粒108，且第一晶粒106經由第二互連橋114電氣地或通訊地耦接至第三晶粒110。另外，第一晶粒106、第二晶粒108及第三晶粒110經由一或多個再分佈層104彼此電氣地或通訊地耦接。藉由將高密度互連橋僅用於需要高密度互連之彼等互連，高密度互連需要較少高密度矽，且因此可藉由利用互連橋112、114來節約成本及複雜性。
如圖1A中可見，互連橋112、114大體上平行於一或多個再分佈層104之邊緣及/或晶粒106、108及/或110之邊緣。圖2示意性地例示封裝配置200，其中第一互連橋112不平行於一或多個再分佈層104之邊緣及/或晶粒106、108及/或110之邊緣，而是經對角地定位。此允許使用第一互連橋112來電氣地或通訊地耦接第一晶粒106、第二晶粒108及第四晶粒202。通常使用銅柱及微凸塊如先前所描述來達成該耦接。在實施例中，互連橋112、114中之一者或兩者可大體上平行於一或多個再分佈層104 之一或多個邊緣及/或晶粒106、108及/或110之邊緣。此外，在實施例中，互連橋112、114均不大體上平行於一或多個再分佈層104之一或多個邊緣及/或晶粒106、108及/或110之邊緣。此外，必要時可在封裝配置100內包括更多或更少的晶粒106、108、110及更多或更少的互連橋112、114，其中一些互連橋、沒有互連橋或所有互連橋大體上平行於一或多個再分佈層104之一或多個邊緣及/或晶粒之邊緣。在實施例中，必要時，互連橋亦可用來電氣地或通訊地耦接兩個以上的晶粒。
為了製作或製造封裝配置100及200，提供載體102。載體102包括晶粒附接帶或膜。將第一互連橋112與第二互連橋114一起置放於載體102上。然後，圍繞第一互連橋112及第二互連橋114在載體102上形成/生長一或多個再分佈層104。因此，互連橋112、114嵌入一或多個再分佈層104內。在實施例中，使用具有兩微米/兩微米或兩微米以上之銅金屬線寬/間距的後端聚合物/電鍍製程來形成一或多個再分佈層104。因此，一般而言，在實施例中，互連間隔之線寬及間距(例如銅柱116之間距)小於一或多個再分佈層104之銅金屬線寬/間距。在實施例中，可在將第一互連橋112及第二互連橋114置放於載體102上之前生長再分佈層104，且因此第一互連橋112及第二互連橋114將置放於再分佈層104上。
在實施例中，可出於平滑化目的來模製並研磨再分佈層104之側面或邊緣。當生長再分佈層104時，亦在再分佈層104及互連橋112、114上形成/生長銅柱116、120。然後將微凸塊118、122分別置放於銅柱116、120上，或第一晶粒106、第二晶粒108及第三晶粒110上。然後可將第一晶粒106、第二晶粒108及第三晶粒110倒裝晶片附接至銅柱116、120。然後可將模具或囊封劑(未例示)置放於晶粒106、108、110及互連橋112、114上方，以便大體上囊封包括一或多個再分佈層104的組件。
然後，自封裝配置100、200拆除載體102。在拆除載體102之後，可出於平滑化目的來研磨一或多個再分佈層104之背面124。因此，封裝配置100之底部將包括一或多個再分佈層104之背面124，以及嵌入再分佈層104內之互連橋112、114之背面。在再分佈層104及/或互連橋112、114之底部內界定的焊墊(未例示)可因此接納銅球或凸塊，且封裝配置100、 200可倒裝晶片附接至基板(未例示)。
因此，根據實施例，互連橋112、114允許晶粒106、108、110之間的高密度(例如，尺寸為兩微米或兩微米以下的)互連及間距，並且僅有少量矽用於互連橋112、114。第一晶粒106、第二晶粒108、第三晶粒110之間經由一或多個再分佈層104的其他互連以及接納封裝配置100、200之基板可具備銅柱120，該等銅柱120處於如下組態中：密度不高，例如銅柱120之密度在尺寸上可大於兩微米，並且銅柱120之間的間距大於兩微米。
圖3為用於製作包括高密度互連橋之封裝配置(例如，圖1A、圖1B及圖2中所例示之封裝配置100及200)的示例性方法300之流程圖，該高密度互連橋用於互連該封裝配置內之晶粒。
在302處，提供載體(例如，載體102)。在304處，將互連橋(例如，互連橋112、114)耦接至載體。在306處，圍繞互連橋在載體上形成一或多個再分佈層(例如，再分佈層104)。在308處，在互連橋及一或多個再分佈層上形成銅柱(例如，銅柱116、120)。在310處，將第一晶粒(例如，晶粒106)耦接至互連橋上之第一組銅柱及一或多個再分佈層上之第一組銅柱。在312處，將第二晶粒(例如，晶粒108)耦接至互連橋上之第二組銅柱及一或多個再分佈層上之第二組銅柱。在314處，移除載體。
描述可使用可各自涉及相同或不同實施例中之一或多個的片語「在一實施例中」或「在實施例中」。重複地使用片語「在一些實施例中」。片語通常不涉及相同實施例；然而，片語可涉及相同實施例。術語「包含」、「具有」及「包括」為同義的，除非上下文另有規定。片語「A及/或B」意謂(A)、(B)或(A及B)。片語「A/B」意謂(A)、(B)或(A及B)，類似於片語「A及/或B」。片語「A、B及C中之至少一個」意謂(A)、(B)、(C)、(A及B)、(A及C)、(B及C)或(A、B及C)。片語「(A)B」意謂(B)或(A及B)，亦即，A為可選的。
儘管本文中已例示且描述某些實施例，但在不脫離本發明之範疇的情況下，旨在達成相同目的的多種替代性及/或等效實施例或實行方案可替代所例示及描述的實施例。本申請案意欲涵蓋本文中所論述的實施 例之任何調適或變化。因此，顯然意圖在於，根據本發明之實施例僅受申請專利範圍及其等效物限制。

Claims (20)

  1. 一種封裝配置，其包含：一或多個再分佈層；一互連橋，其嵌入該一或多個再分佈層內；一第一晶粒，其耦接至(i)該一或多個再分佈層之一第一部分及(ii)該互連橋之一第一部分；以及一第二晶粒，其耦接至(ii)該一或多個再分佈層之一第二部分及(ii)該互連橋之一第二部分，以便至少經由該互連橋電氣耦接該第一晶粒及該第二晶粒，其中，該互連橋之背面與該一或多個再分佈層之背面對齊，且該互連橋之正面相較於該一或多個再分佈層之正面突向該第一晶粒及該第二晶粒。
  2. 如申請專利範圍第1項之封裝配置，其中該互連橋為一第一互連橋，且該封裝配置進一步包含：一第二互連橋，其嵌入該一或多個再分佈層內；以及一第三晶粒，其耦接至(i)該一或多個再分佈層之一第三部分及(ii)該第二互連橋之一第一部分，其中該第一晶粒耦接至該第二互連橋之一第二部分，以便至少經由該第二互連橋電氣耦接該第一晶粒及該第三晶粒。
  3. 如申請專利範圍第2項之封裝配置，其中該第一互連橋及該第二互連橋中之至少一者大體上平行於(i)該第一晶粒、(ii)該第二晶粒或(iii)該第三晶粒中之至少一者的一邊緣。
  4. 如申請專利範圍第3項之封裝配置，其中該第一互連橋及該第二互連橋兩者均大體上平行於(i)該第一晶粒、(ii)該第二晶粒或(iii)該第三晶粒之一邊緣。
  5. 如申請專利範圍第3項之封裝配置，其中該第一互連橋大體上平行於該第一晶粒之一第一邊緣，且該第二互連橋大體上平行於該第一晶粒之一第二邊緣。
  6. 如申請專利範圍第1項之封裝配置，其中該互連橋為一第一互連橋，且該封裝配置進一步包含： 一第二互連橋，其嵌入該一或多個再分佈層內；一第三晶粒，其耦接至(i)該一或多個再分佈層之一第三部分及(ii)該第二互連橋之一第一部分；一第四晶粒，其耦接至(i)該一或多個再分佈層之一第四部分及(ii)該第二互連橋之一第二部分，以便至少經由該第二互連橋電氣耦接該第三晶粒及該第四晶粒，其中該第一晶粒耦接至(i)該第二互連橋之一第三部分，以便至少經由該第二互連橋電氣耦接該第一晶粒及該第三晶粒，且耦接至(ii)該第二互連橋之一第四部分，以便至少經由該第二互連橋電氣耦接該第一晶粒及該第四晶粒。
  7. 如申請專利範圍第6項之封裝配置，其中該第一互連橋及該第二互連橋中之至少一者大體上平行於(i)該第一晶粒、(ii)該第二晶粒或(iii)該第三晶粒中之至少一者的一邊緣。
  8. 如申請專利範圍第7項之封裝配置，其中該第一互連橋及該第二互連橋兩者均大體上平行於(i)該第一晶粒、(ii)該第二晶粒或(iii)該第三晶粒之一邊緣。
  9. 如申請專利範圍第7項之封裝配置，其中該第一互連橋大體上平行於該第一晶粒之一第一邊緣，且該第二互連橋大體上平行於該第一晶粒之一第二邊緣。
  10. 如申請專利範圍第7項之封裝配置，其中該第一互連橋及該第二互連橋均不大體上平行於該第一晶粒之一邊緣。
  11. 如申請專利範圍第1項之封裝配置，其中該互連橋經組配以使得該第一晶粒及該第二晶粒係由隔開兩微米或兩微米以下的耦接結構耦接至該互連橋，其中該等耦接結構具有兩微米或兩微米以下之一尺寸。
  12. 如申請專利範圍第11項之封裝配置，其中該等耦接結構之線寬及間距小於該一或多個再分佈層之線寬/間距。
  13. 如申請專利範圍第11項之封裝配置，其中該等耦接結構包含銅柱。
  14. 如申請專利範圍第13項之封裝配置，其中該等銅柱經由微凸塊耦接至該第二晶粒。
  15. 如申請專利範圍第1項之封裝配置，其進一步包含一模具，該模具大 體上包裹該互連橋、該第一晶粒及該第二晶粒。
  16. 一種製作封裝配置之方法，其包含：提供一載體；將一互連橋耦接至該載體；圍繞該互連橋在該載體上形成一或多個再分佈層；在該互連橋及該一或多個再分佈層上形成銅柱；將一第一晶粒耦接至該互連橋上之一第一組銅柱及該一或多個再分佈層上之一第一組銅柱；將一第二晶粒耦接至該互連橋上之一第二組銅柱及該一或多個再分佈層上之一第二組銅柱；以及移除該載體。
  17. 如申請專利範圍第16項之方法，其中耦接該第一晶粒包含將該第一晶粒倒裝晶片附接至該互連橋上之該第一組銅柱及該一或多個再分佈層上之該第一組銅柱上，並且其中耦接該第二晶粒包含將該第二晶粒倒裝晶片附接至該互連橋上之該第二組銅柱及該一或多個再分佈層上之該第二組銅柱上。
  18. 如申請專利範圍第16項之方法，其進一步包含圍繞該第一晶粒、該第二晶粒及該互連橋將一模具置放於該一或多個再分佈層上。
  19. 如申請專利範圍第16項之方法，其中該互連橋為一第一互連橋，且該方法進一步包含：將一第二互連橋耦接至該載體；圍繞該第一互連橋及該第二互連橋在該載體上形成該一或多個再分佈層；在該第二互連橋及該一或多個再分佈層上形成銅柱；將該第一晶粒耦接至該第二互連橋上之一第一組銅柱及該一或多個再分佈層上之一第三組銅柱；以及將一第三晶粒耦接至該第二互連橋上之一第二組銅柱及該一或多個再分佈層上之一第四組銅柱。
  20. 如申請專利範圍第16項之方法，其中該互連橋為一第一互連橋，且該方法進一步包含： 將一第二互連橋耦接至該載體；圍繞該第一互連橋及該第二互連橋在該載體上形成該一或多個再分佈層；在該第二互連橋及該一或多個再分佈層上形成銅柱；將該第一晶粒耦接至該第二互連橋上之一第一組銅柱及該一或多個再分佈層上之一第三組銅柱；將一第三晶粒耦接至該第二互連橋上之一第二組銅柱及該一或多個再分佈層上之一第四組銅柱；以及將一第四晶粒耦接至該第二互連橋上之一第三組銅柱及該一或多個再分佈層上之一第五組銅柱。
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