TWI622105B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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Publication number
TWI622105B
TWI622105B TW105121366A TW105121366A TWI622105B TW I622105 B TWI622105 B TW I622105B TW 105121366 A TW105121366 A TW 105121366A TW 105121366 A TW105121366 A TW 105121366A TW I622105 B TWI622105 B TW I622105B
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Taiwan
Prior art keywords
package
substrate
sensor
groove
forming
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TW105121366A
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TW201721770A (zh
Inventor
余振華
陳志華
蔡豪益
陳玉芬
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台灣積體電路製造股份有限公司
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Abstract

本發明描述封裝結構及形成封裝結構之方法。一種方法包括將一第一封裝置放於一第一基板之一凹槽內。該第一封裝包括一第一晶粒。該方法進一步包括將一第一感測器附接至該第一封裝及該第一基板。該第一感測器電耦合至該第一封裝及該第一基板。

Description

封裝結構及其形成方法
本發明係關於一種封裝結構及其形成方法。
半導體裝置用於多種電子應用，諸如(作為實例)個人電腦、行動電話、數位相機及其他電子設備。半導體裝置通常係藉由以下步驟予以製作：將絕緣或介電質材料層、導電材料層及半導電材料層依序地沈積於半導體基板上方，且使用微影來圖案化該各種材料層以在其上形成電路組件及元件。通常在單一半導體晶圓上製造數十或數百個積體電路。藉由沿著切割道來鋸切積體電路而單粒化個別晶粒。接著，舉例而言，以多晶片模組或以其他類型之封裝來分離地封裝個別晶粒。
半導體行業繼續藉由不斷地縮減最小構件大小(此允許將更多組件整合至給定區域中)來改良各種電子組件(例如，電晶體、二極體、電阻器、電容器等等)之整合密度。在一些應用中，諸如積體電路晶粒之此等較小電子組件亦可需要相較於過去之封裝利用較少區域的較小封裝。
一實施例為一種方法，其包括將一第一封裝置放於一第一基板之一凹槽內。該第一封裝包括一第一晶粒。該方法進一步包括將一第 一感測器附接至該第一封裝及該第一基板。該第一感測器電耦合至該第一封裝及該第一基板。
在一實施例中，該第一感測器包含一心跳速率監測器、一環境光感測器、一紫外線光感測器、一環境溫度感測器、一加速度計、一陀螺儀、一磁力計、一氣壓感測器、一血氧定量感測器、一全球定位系統(GPS)感測器、一膚電傳導感測器、一膚溫感測器、一血液葡萄糖監測器，或其一組合。
在一實施例中，進一步包含：在該第一基板之該凹槽中形成一第一接合墊，該第一封裝運用一第一導電連接器而電耦合至該第一基板之該第一接合墊。
在一實施例中，進一步包含：在該第一基板之一第一表面上形成一第二接合墊，該第一表面在該第一基板之該凹槽外部，該第一封裝運用一第二導電連接器而電耦合至該第一基板之該第二接合墊。
在一實施例中，進一步包含：將一第二感測器附接至該第一封裝，該第二感測器電耦合至該第一封裝。
在一實施例中，進一步包含：將一第三感測器附接至該第一封裝及該第一基板，該第三感測器電耦合至該第一封裝及該第一基板。
在一實施例中，進一步包含：形成該第一封裝，該形成該第一封裝包含：運用一封裝物至少側向地封裝該第一晶粒；及在該第一晶粒及該封裝物上方形成一第一重佈結構，該第一感測器電耦合至該第一重佈結構。
在一實施例中，進一步包含：在該第一基板之該凹槽中形成一第三接合墊。並且其中該形成該第一封裝進一步包含：形成自該第一重佈結構至該第一晶粒之一背側延伸通過該封裝物的一貫穿通路，該第一晶粒之一主動側耦合至該第一重佈結構，該主動側與該背側相對，該第一封裝之該貫穿通路運用一第一導電連接器而電耦合至該第 一基板之該第三接合墊。
在一實施例中，進一步包含：將一熱電產生器附接至該第一封裝及該第一基板，該熱電產生器電耦合至該第一封裝。
在一實施例中，進一步包含：形成該第一封裝，該形成該第一封裝包含：運用一封裝物至少側向地封裝該第一晶粒及一第二晶粒；及在該第一晶粒、該第二晶粒及該封裝物上方形成一第一重佈結構，該第一感測器電耦合至該第一重佈結構。
另一實施例為一種方法，其包括形成一第一封裝，該形成該第一封裝包括：運用一封裝物至少側向地封裝一第一晶粒，該第一晶粒具有一主動側及一背側，該背側與該主動側相對；及在該第一晶粒及該封裝物上方形成一第一重佈結構，該第一重佈結構耦合至該第一晶粒之該主動側。該方法進一步包括：將該第一封裝耦合至一第一基板，該第一封裝之至少一部分在該第一基板中之一凹槽內延伸；及將一第一感測器接合至該第一封裝及該第一基板，該第一感測器電耦合至該第一封裝及該第一基板。
在一實施例中，其中該第一感測器包含一心跳速率監測器、一環境光感測器、一紫外線光感測器、一環境溫度感測器、一加速度計、一陀螺儀、一磁力計、一氣壓感測器、一血氧定量感測器、一全球定位系統(GPS)感測器、一膚電傳導感測器、一膚溫感測器、一血液葡萄糖監測器，或其一組合。
在一實施例中，其中該形成該第一封裝進一步包含：形成自該第一重佈結構至該第一晶粒之該背側之一層級延伸通過該封裝物的一貫穿通路。
在一實施例中，進一步包含：在該第一基板之該凹槽中形成一第一接墊，該第一封裝之該貫穿通路運用一第一導電連接器而電耦合至該第一基板之該第一接墊。
在一實施例中，進一步包含：將一第二感測器接合至該第一封裝，該第二感測器電耦合至該第一封裝。
在一實施例中，其中該第一感測器包含直接地在該第一基板之該凹槽上方的一第一部分及直接地在該第一基板之位於該凹槽外部之一部分上方的一第二部分，且其中該第二感測器僅直接地在該第一基板之該凹槽上方。
在一實施例中，進一步包含：將一第三感測器接合至該第一封裝，該第三感測器電耦合至該第一封裝；及將一第四感測器接合至該第一封裝，該第四感測器電耦合至該第一封裝。
一另外實施例為一種裝置，其包括：一第一封裝，其在一第一基板之一凹槽中，該第一封裝包括一第一晶粒；及一第一感測器，其電耦合至該第一封裝及該第一基板，該第一感測器具有直接地在該第一基板之該凹槽上方的一第一部分及直接地在該第一基板之位於該凹槽外部之一部分上方的一第二部分。
在一實施例中，其中該第一感測器包含一心跳速率監測器、一環境光感測器、一紫外線光感測器、一環境溫度感測器、一加速度計、一陀螺儀、一磁力計、一氣壓感測器、一血氧定量感測器、一全球定位系統(GPS)感測器、一膚電傳導感測器、一膚溫感測器、一血液葡萄糖監測器，或其一組合。
在一實施例中，進一步包含：一第二感測器，其電耦合至該第一封裝，該第二感測器僅直接地在該第一基板之該凹槽上方。
100‧‧‧載體基板
102‧‧‧離型層
103‧‧‧黏著劑
104‧‧‧介電質層
106‧‧‧金屬化圖案
108‧‧‧介電質層
110‧‧‧背側重佈結構
112‧‧‧貫穿通路
114-1‧‧‧積體電路晶粒
114-2‧‧‧積體電路晶粒
114-3‧‧‧積體電路晶粒
114-4‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧半導體基板
120‧‧‧互連結構
122‧‧‧墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接器
128‧‧‧介電質材料
130‧‧‧封裝物
132‧‧‧介電質層
138‧‧‧金屬化圖案
140‧‧‧介電質層
146‧‧‧金屬化圖案
148‧‧‧介電質層
154‧‧‧金屬化圖案
156‧‧‧介電質層
160‧‧‧前側重佈結構
162‧‧‧墊
170‧‧‧膠帶
184‧‧‧鋸切
200‧‧‧封裝
300‧‧‧第一封裝區
302‧‧‧第二封裝區
402‧‧‧基板
404‧‧‧凹槽
406‧‧‧接點區域/接合墊
408‧‧‧導電連接器
410‧‧‧接點區域/接合墊
420-1‧‧‧感測器
420-2‧‧‧感測器
420-3‧‧‧感測器
420-4‧‧‧感測器
422‧‧‧接點區域/接合墊
424‧‧‧導電連接器
430‧‧‧導電元件
500‧‧‧封裝
602‧‧‧組件
604A‧‧‧表面
604B‧‧‧表面
606‧‧‧表面
622‧‧‧接點區域
624‧‧‧導電連接器
H1‧‧‧厚度
H2‧‧‧深度
H3‧‧‧高度
H4‧‧‧高度
H5‧‧‧高度
H6‧‧‧深度
L1‧‧‧長度
W1‧‧‧寬度
當與附圖一起進行閱讀時自以下詳述描述最佳地理解本揭露之態樣。應注意，根據行業標準方法，未按比例繪製各種構件。事實上，可出於論述清晰性起見而任意地增加或縮減各種構件之尺寸。
圖1至圖3、圖4A至圖4B、圖5至圖24及圖25A至圖25B為根據一些實施例之在用於形成封裝結構之製程期間之中間步驟的視圖。
圖26、圖27A至圖27B、圖28至圖32及圖33A至圖33B為根據另一實施例之在用於形成封裝結構之製程期間之中間步驟的視圖。
圖34為根據另一實施例之封裝結構的剖面圖。
以下揭露提供許多不同實施例或實例以用於實施所提供之主題之不同特徵。下文描述組件及配置之特定實例以簡化本揭露。當然，此等者僅僅為實例且並不意欲為限制性的。舉例而言，在以下描述中將第一構件形成於第二構件上方或上可包括將第一構件與第二構件形成為進行直接接觸的實施例，且亦可包括可在第一構件與第二構件之間形成額外構件使得第一構件與第二構件可不進行直接接觸的實施例。另外，本揭露可在各種實例中重複參考數字及/或字母。此重複係出於簡單性及清晰之目的且本身並不規定所論述之各種實施例及/或組態之間的關係。
此外，本文中可出於描述簡易性起見而使用空間相對術語(諸如「下面」、「下方」、「下部」、「上方」、「上部」及其類似者)以如諸圖所說明而描述一個元件或構件與另外元件或構件之關係。相似地，本文中可使用諸如「前側」及「背側」之術語以更容易地識別各別組件，且該等術語可識別出彼等組件(例如)位於另一組件之對置側上。除了諸圖所描繪之定向以外，空間相對術語亦意欲涵蓋使用或操作中之裝置之不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且可同樣相應地解譯本文中所使用之空間相對描述符。
本文中所論述之實施例可在特定上下文(即，用於可穿戴式裝置或結構之封裝結構)中予以論述。封裝結構可包括扇出或扇入封裝。詳言之，封裝結構可包括於諸如以下各者之可穿戴式裝置中：電子紡 織品(有時被稱作智慧型服裝)、可穿戴式電腦、活動追蹤器、智慧型手錶、智慧型眼鏡、全球定位系統(GPS)裝置、醫療裝置、擴增實境裝置、虛擬實境耳機、智慧型連接產品，或其類似者。此外，本揭露之教示適用於包括具有一或多個感測器之一或多個積體電路晶粒的任何封裝結構。其他實施例預期其他應用，諸如對於熟習此項技術者而言在閱讀本揭露後就將容易顯而易見之不同封裝類型或不同組態。應注意，本文中所論述之實施例可未必說明結構中可存在之每一組件或構件。舉例而言，諸如在對一個組件之論述可足以傳達實施例之態樣時，可自圖省略多個組件。此外，本文中所論述之方法實施例可被論述為以特定次序而執行；然而，其他方法實施例可以任何邏輯次序而執行。
圖1至圖3、圖4A至圖4B、圖5至圖24及圖25A至圖25B說明根據一些實施例之在用於形成封裝結構之製程期間之中間步驟的視圖。圖1至圖3、圖4A、圖5至圖24及圖25A為剖面圖，圖4B及圖25B為俯視圖。圖1說明載體基板100及形成於載體基板100上之離型層(release layer)102。說明分別用於形成第一封裝及第二封裝之第一封裝區300及第二封裝區302。
載體基板100可為玻璃載體基板、陶瓷載體基板或其類似者。載體基板100可為晶圓，使得可同時地在載體基板100上形成多個封裝。離型層102可由聚合物基材料形成，其可連同載體基板100一起自將在後續步驟中形成之上覆結構被移除。在一些實施例中，離型層102為在經加熱時失去其黏著性質之環氧樹脂基熱離型材料，諸如光-熱轉換(Light-to-Heat-Conversion；LTHC)離型塗層。在其他實施例中，離型層102可為在暴露於紫外線(UV)光時失去其黏著性質之UV膠。離型層102可被施配為液體且固化，可為層壓至載體基板100上之層壓膜，或可為其類似者。離型層102之頂部表面可被調平且可具有高度共面 性。
在圖2中，形成金屬化圖案106。如圖2所說明，在離型層102上形成介電質層104。介電質層104之底部表面可與離型層102之頂部表面接觸。在一些實施例中，介電質層104係由諸如聚苯并唑(PBO)、聚醯亞胺、苯環丁烯(BCB)或其類似者之聚合物形成。在其他實施例中，介電質層104係由以下各者形成：諸如氮化矽之氮化物；諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG)或其類似者之氧化物；或其類似者。介電質層104可藉由諸如旋塗、化學氣相沈積(CVD)、層壓、其類似者或其組合之任何可接受的沈積製程予以形成。
金屬化圖案106形成於介電質層104上。作為用以形成金屬化圖案106之實例，將晶種層(未圖示)形成於介電質層104上方。在一些實施例中，晶種層為金屬層，其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中，晶種層包含鈦層及在鈦層上方之銅層。晶種層可使用(例如)PVD或其類似者予以形成。接著，在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者予以形成，且可暴露於光以供圖案化。光阻劑之圖案對應於金屬化圖案106。圖案化形成通過光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及晶種層之暴露部分上。導電材料可藉由諸如電鍍或無電式電鍍之鍍覆或其類似者予以形成。導電材料可包含金屬，比如銅、鈦、鎢、鋁或其類似者。接著，移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝除製程(諸如使用氧電漿或其類似者)來移除光阻劑。一旦移除光阻劑，就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層及導電材料之剩餘部分形成金屬化圖案106。
在圖3中，在金屬化圖案106及介電質層104上形成介電質層 108。在一些實施例中，介電質層108係由聚合物形成，該聚合物可為可使用微影遮罩而圖案化之光敏材料，諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中，介電質層108係由以下各者形成：諸如氮化矽之氮化物；諸如氧化矽、PSG、BSG、BPSG之氧化物；或其類似者。介電質層108可藉由旋塗、層壓、CVD、其類似者或其組合予以形成。接著，圖案化介電質層108以形成用以暴露金屬化圖案106之部分之開口。圖案化可藉由可接受的製程，諸如藉由在介電質層為光敏材料時將介電質層108暴露於光，或藉由使用(例如)非等向性蝕刻進行蝕刻。
介電質層104及108以及金屬化圖案106可被稱作背側重佈結構。如所說明，背側重佈結構包括兩個介電質層104及108以及一個金屬化圖案106。在其他實施例中，背側重佈結構可包括任何數目個介電質層、金屬化圖案及通路。可藉由重複用於形成金屬化圖案106及介電質層108之製程而在背側重佈結構中形成一或多個額外金屬化圖案及介電質層。可在金屬化圖案之形成期間藉由在下伏介電質層之開口中形成金屬化圖案之晶種層及導電材料來形成通路。因此，通路可互連及電耦合各種金屬化圖案。
進一步在圖3中，形成貫穿通路112。作為用以形成貫穿通路112之實例，在背側重佈結構(例如，如所說明之介電質層108及金屬化圖案106之暴露部分)上方形成晶種層。在一些實施例中，晶種層為金屬層，其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中，晶種層包含鈦層及在鈦層上方之銅層。晶種層可使用(例如)PVD或其類似者予以形成。在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者予以形成，且可暴露於光以供圖案化。光阻劑之圖案對應於貫穿通路。圖案化形成通過光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及晶種層之暴露部分上。導 電材料可藉由諸如電鍍或無電式電鍍之鍍覆或其類似者予以形成。導電材料可包含金屬，比如銅、鈦、鎢、鋁或其類似者。移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝除製程(諸如使用氧電漿或其類似者)來移除光阻劑。一旦移除光阻劑，就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層及導電材料之剩餘部分形成貫穿通路112。
在圖4A及圖4B中，積體電路晶粒114藉由黏著劑116而黏著至介電質層108。圖4B為圖4A中之結構的俯視圖，其中圖4A中之結構沿著圖4B之線A-A。如圖4B所說明，四個積體電路晶粒114(114-1、114-2、114-3及114-4)黏著於第一封裝區300及第二封裝區302中之每一者中，且在其他實施例中，更多或更少積體電路晶粒可黏著於每一區中。亦如圖4B所說明，積體電路晶粒114可為不同大小，且在其他實施例中，積體電路晶粒114可為相同大小。
在黏著至介電質層108之前，可根據適用製造製程來處理積體電路晶粒114以在積體電路晶粒114中形成積體電路。舉例而言，積體電路晶粒114各自包含一半導體基板118，諸如經摻雜或無摻雜之矽，或絕緣體上半導體(semiconductor-on-insulator；SOI)基板之主動層。半導體基板可包括：諸如鍺之其他半導體材料；包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦之合成半導體；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP之合金半導體；或其組合。亦可使用諸如多層或梯度基板之其他基板。諸如電晶體、二極體、電容器、電阻器等等之裝置可形成於半導體基板118中及/或上，且可藉由互連結構120而互連以形成積體電路，互連結構120係藉由(例如)半導體基板118上之一或多個介電質層中之金屬化圖案予以形成。
積體電路晶粒114進一步包含進行外部連接之墊122，諸如鋁墊。 墊122位於可被稱作積體電路晶粒114之各別主動側的側上。鈍化膜124位於積體電路晶粒114上且位於墊122之部分上。開口通過鈍化膜124而至墊122。晶粒連接器126(諸如導電柱(例如，包含諸如銅之金屬))位於通過鈍化膜124之開口中且機械及電耦合至各別墊122。晶粒連接器126可藉由(例如)鍍覆或其類似者予以形成。晶粒連接器126電耦合積體電路晶粒114之各別積體電路。
介電質材料128位於積體電路晶粒114之主動側上，諸如位於鈍化膜124及晶粒連接器126上。介電質材料128側向地封裝晶粒連接器126，且介電質材料128與各別積體電路晶粒114側向地毗連。介電質材料128可為諸如PBO、聚醯亞胺、BCB或其類似者之聚合物；諸如氮化矽或其類似者之氮化物；諸如氧化矽、PSG、BSG、BPSG或其類似者之氧化物；其類似者，或其組合，且可(例如)藉由旋塗、層壓、CVD或其類似者予以形成。
黏著劑116位於積體電路晶粒114之背側上且將積體電路晶粒114黏著至背側重佈結構110，諸如說明中之介電質層108。黏著劑116可為任何適合黏著劑、環氧樹脂、晶粒附接膜(DAF)或其類似者。可將黏著劑116施加至積體電路晶粒114之背側(諸如至各別半導體晶圓之背側)，或可施加於載體基板100之表面上方。積體電路晶粒114可諸如藉由鋸切或切割予以單粒化，且使用(例如)取置工具藉由黏著劑116而黏著至介電質層108。
積體電路晶粒114可為邏輯晶粒(例如，中央處理單元、微控制器等等)、記憶體晶粒(例如，動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等等)、功率管理晶粒(例如，功率管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(DSP)晶粒)、前端晶粒(例如，類比前端(AFE)晶粒)、其類似者，或其組合。作為一實 例，一AFE為一組類比訊號調節電路系統，其使用(例如)用於感測器及其他電路之運算放大器、濾波器及/或特殊應用積體電路來提供可組態且靈活之電子功能區塊以將多種感測器介接至類比-數位轉換器或在一些狀況下介接至微控制器。舉例而言，在一實施例中，積體電路晶粒114-1為AFE晶粒，積體電路晶粒114-2為PMIC晶粒，積體電路晶粒114-3為訊號處理晶粒，且積體電路晶粒114-4為微控制器(MCU)晶粒。
在圖5中，將封裝物130形成於各種組件上。封裝物130可為模塑料、環氧樹脂或其類似者，且可藉由壓縮成型、轉移成型或其類似者予以施加。在固化之後，封裝物130可經受研磨製程以暴露貫穿通路112及晶粒連接器126。貫穿通路112、晶粒連接器126及封裝物130之頂部表面在研磨製程之後共面。在一些實施例中，舉例而言，若貫穿通路112及晶粒連接器126已經被暴露，則可省略研磨。
在圖6至圖16中，形成前側重佈結構160。如將在圖16中所說明，前側重佈結構160包括介電質層132、140、148及156以及金屬化圖案138、146及154。
在圖6中，將介電質層132沈積於封裝物130、貫穿通路112及晶粒連接器126上。在一些實施例中，介電質層132係由聚合物形成，該聚合物可為可使用微影遮罩而圖案化之光敏材料，諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中，介電質層132係由以下各者形成：諸如氮化矽之氮化物；諸如氧化矽、PSG、BSG、BPSG之氧化物；或其類似者。介電質層132可藉由旋塗、層壓、CVD、其類似者或其組合予以形成。
在圖7中，接著圖案化介電質層132。圖案化形成開口以暴露貫穿通路112及晶粒連接器126之部分。圖案化可藉由可接受的製程，諸如藉由在介電質層132為光敏材料時將介電質層132暴露於光，或藉由 使用(例如)非等向性蝕刻進行蝕刻。若介電質層132為光敏材料，則可在暴露之後顯影介電質層132。
在圖8中，在介電質層132上形成具有通路之金屬化圖案138。作為用以形成金屬化圖案138之實例，將晶種層(未圖示)形成於介電質層132上方及通過介電質層132之開口中。在一些實施例中，晶種層為金屬層，其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中，晶種層包含鈦層及在鈦層上方之銅層。晶種層可使用(例如)PVD或其類似者予以形成。接著，在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者予以形成，且可暴露於光以供圖案化。光阻劑之圖案對應於金屬化圖案138。圖案化形成通過光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及晶種層之暴露部分上。導電材料可藉由諸如電鍍或無電式電鍍之鍍覆或其類似者予以形成。導電材料可包含金屬，比如銅、鈦、鎢、鋁或其類似者。接著，移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝除製程(諸如使用氧電漿或其類似者)來移除光阻劑。一旦移除光阻劑，就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層及導電材料之剩餘部分形成金屬化圖案138及通路。通路形成於通過介電質層132之開口中而至(例如)貫穿通路112及/或晶粒連接器126。
在圖9中，將介電質層140沈積於金屬化圖案138及介電質層132上。在一些實施例中，介電質層140係由聚合物形成，該聚合物可為可使用微影遮罩而圖案化之光敏材料，諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中，介電質層140係由以下各者形成：諸如氮化矽之氮化物；諸如氧化矽、PSG、BSG、BPSG之氧化物；或其類似者。介電質層140可藉由旋塗、層壓、CVD、其類似者或其組合予以形成。
在圖10中，接著圖案化介電質層140。圖案化形成開口以暴露金屬化圖案138之部分。圖案化可藉由可接受的製程，諸如藉由在介電質層為光敏材料時將介電質層140暴露於光，或藉由使用(例如)非等向性蝕刻進行蝕刻。若介電質層140為光敏材料，則可在暴露之後顯影介電質層140。
在圖11中，在介電質層140上形成具有通路之金屬化圖案146。作為用以形成金屬化圖案146之實例，將晶種層(未圖示)形成於介電質層140上方及通過介電質層140之開口中。在一些實施例中，晶種層為金屬層，其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中，晶種層包含鈦層及在鈦層上方之銅層。晶種層可使用(例如)PVD或其類似者予以形成。接著，在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者予以形成，且可暴露於光以供圖案化。光阻劑之圖案對應於金屬化圖案146。圖案化形成通過光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及晶種層之暴露部分上。導電材料可藉由諸如電鍍或無電式電鍍之鍍覆或其類似者予以形成。導電材料可包含金屬，比如銅、鈦、鎢、鋁或其類似者。接著，移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝除製程(諸如使用氧電漿或其類似者)來移除光阻劑。一旦移除光阻劑，就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層及導電材料之剩餘部分形成金屬化圖案146及通路。通路形成於通過介電質層140之開口中而至(例如)金屬化圖案138之部分。
在圖12中，將介電質層148沈積於金屬化圖案146及介電質層140上。在一些實施例中，介電質層148係由聚合物形成，該聚合物可為可使用微影遮罩而圖案化之光敏材料，諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中，介電質層148係由以下各者形成：諸如 氮化矽之氮化物；諸如氧化矽、PSG、BSG、BPSG之氧化物；或其類似者。介電質層148可藉由旋塗、層壓、CVD、其類似者或其組合予以形成。
在圖13中，接著圖案化介電質層148。圖案化形成開口以暴露金屬化圖案146之部分。圖案化可藉由可接受的製程，諸如藉由在介電質層為光敏材料時將介電質層148暴露於光，或藉由使用(例如)非等向性蝕刻進行蝕刻。若介電質層148為光敏材料，則可在暴露之後顯影介電質層148。
在圖14中，在介電質層148上形成具有通路之金屬化圖案154。作為用以形成金屬化圖案154之實例，將晶種層(未圖示)形成於介電質層148上方及通過介電質層148之開口中。在一些實施例中，晶種層為金屬層，其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中，晶種層包含鈦層及在鈦層上方之銅層。晶種層可使用(例如)PVD或其類似者予以形成。接著，在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者予以形成，且可暴露於光以供圖案化。光阻劑之圖案對應於金屬化圖案154。圖案化形成通過光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及晶種層之暴露部分上。導電材料可藉由諸如電鍍或無電式電鍍之鍍覆或其類似者予以形成。導電材料可包含金屬，比如銅、鈦、鎢、鋁或其類似者。接著，移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝除製程(諸如使用氧電漿或其類似者)來移除光阻劑。一旦移除光阻劑，就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層及導電材料之剩餘部分形成金屬化圖案154及通路。通路形成於通過介電質層148之開口中而至(例如)金屬化圖案146之部分。
在圖15中，將介電質層156沈積於金屬化圖案154及介電質層148 上。在一些實施例中，介電質層156係由聚合物形成，該聚合物可為可使用微影遮罩而圖案化之光敏材料，諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中，介電質層156係由以下各者形成：諸如氮化矽之氮化物；諸如氧化矽、PSG、BSG、BPSG之氧化物；或其類似者。介電質層156可藉由旋塗、層壓、CVD、其類似者或其組合予以形成。
在圖16中，接著圖案化介電質層156。圖案化形成開口以暴露金屬化圖案154之部分。圖案化可藉由可接受的製程，諸如藉由在介電質層為光敏材料時將介電質層156暴露於光，或藉由使用(例如)非等向性蝕刻進行蝕刻。若介電質層156為光敏材料，則可在暴露之後顯影介電質層156。
作為一實例而展示前側重佈結構160。更多或更少介電質層及金屬化圖案可形成於前側重佈結構160中。若將形成更少介電質層及金屬化圖案，則可省略上文所論述之步驟及製程。若將形成更多介電質層及金屬化圖案，則可重複上文所論述之步驟及製程。熟習此項技術者將容易理解將省略或重複哪些步驟及製程。
在圖17中，在前側重佈結構160之外部側上形成可被稱作凸塊下金屬層(under bump metallurgy；UBM)之墊162。在所說明實施例中，墊162被形成為貫穿通過介電質層156之開口而至金屬化圖案154。作為用以形成墊162之實例，在介電質層156上方形成晶種層(未圖示)。在一些實施例中，晶種層為金屬層，其可為單一層或包含由不同材料形成之複數個子層的複合層。在一些實施例中，晶種層包含鈦層及在鈦層上方之銅層。晶種層可使用(例如)PVD或其類似者予以形成。接著，在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋塗或其類似者予以形成，且可暴露於光以供圖案化。光阻劑之圖案對應於墊162。圖案化形成通過光阻劑之開口以暴露晶種層。導電材料形成於光阻劑 之開口中及晶種層之暴露部分上。導電材料可藉由諸如電鍍或無電式電鍍之鍍覆或其類似者予以形成。導電材料可包含金屬，比如銅、鈦、鎢、鋁或其類似者。接著，移除光阻劑及未形成有導電材料的晶種層之部分。可藉由可接受的灰化或剝除製程(諸如使用氧電漿或其類似者)來移除光阻劑。一旦移除光阻劑，就諸如藉由使用可接受的蝕刻製程(諸如藉由濕式或乾式蝕刻)來移除晶種層之暴露部分。晶種層及導電材料之剩餘部分形成墊162。
在圖18中，執行載體基板脫接以將載體基板100自背側重佈結構(例如，介電質層104)拆離(脫接)。根據一些實施例，脫接包括將諸如雷射光或UV光之光投影於離型層102上，使得離型層102在光之熱下分解且可移除載體基板100。接著，將結構翻轉並置放於膠帶170上。
在圖19中，通過介電質層104形成開口以暴露金屬化圖案106之部分。舉例而言，可使用雷射鑽孔、蝕刻或其類似者來形成開口。
在圖20中，藉由沿著切割道區(例如，在鄰近區300及302之間)進行鋸切184來執行單粒化製程。鋸切184將第一封裝區300自第二封裝區302單粒化。圖21說明所得的經單粒化結構。單粒化引起封裝200被單粒化，封裝200可來自第一封裝區300或第二封裝區302中之一者。封裝200亦可被稱作整合式扇出(integrated fan-out；InFO)封裝200。
在圖22中，說明基板402，其中凹槽404位於基板402之至少一部分上方。基板402可為半導體基板，諸如經摻雜或無摻雜之矽，或SOI基板之主動層。基板402可包括：諸如鍺之其他半導體材料；包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦之合成半導體；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP之合金半導體；或其組合。亦可使用諸如多層或梯度基板之其他基板。在一些實施例中，基板402係基於諸如玻璃纖維強化樹脂核心之絕緣核心。一種實例核心材料為諸如FR4之玻璃纖維樹脂。核 心材料之替代例包括雙順丁烯二醯亞胺-三嗪(bismaleimide-triazine；BT)樹脂，或替代地，其他印刷電路板(PCB)材料或膜。諸如味之素累積膜(Ajinomoto build-up film；ABF)之累積膜或其他層壓物可用於基板402。基板402可被稱作封裝基板402。
基板402可包括主動及被動裝置(圖22中未圖示)。熟習此項技術者將認識到，諸如電晶體、電容器、電阻器、此等者之組合及其類似者的多種裝置可用以產生用於封裝之設計之結構及功能要求。裝置可使用任何適合方法予以形成。
基板402亦可包括金屬化層及通路(未圖示)。金屬化層及通路可形成於主動及被動裝置上方且經設計以連接各種裝置以形成功能電路系統。金屬化層可由交替之介電質(例如，低介電係數材料)層與導電材料(例如，銅)層形成(其中通路互連導電材料層)，且可經由任何適合製程(諸如沈積、鑲嵌、雙鑲嵌或其類似者)予以形成。在一些實施例中，基板402實質上無主動及被動裝置。
可藉由圖案化基板402來形成凹槽404。可藉由(例如)蝕刻製程來執行圖案化。在一些實施例中，基板具有厚度H1，其中凹槽具有小於厚度H1之深度H2。在一些實施例中，深度H2在厚度H1之約10%至約50%之範圍內，諸如厚度H1之約30%。
在圖23中，接點區域406形成於基板402上之凹槽404中。在所說明實施例中，接點區域406形成於凹槽404之底部上。在一些實施例中，接點區域406為接合墊。接合墊406可形成於基板402上方。在一些實施例中，藉由在基板402之凹槽404中形成通向介電質層(未圖示)之凹槽(未圖示)來形成接合墊406。凹槽可經形成以允許將接合墊406嵌入至介電質層中。在其他實施例中，在接合墊406可形成於介電質層上方時省略凹槽。接合墊406將基板402(包括基板402中之金屬化層)電及/或實體耦合至隨後接合之第二封裝200(參見圖24)。在一些 實施例中，接合墊406包括由銅、鈦、鎳、金、錫、其類似者或其組合製成之薄晶種層(未圖示)。接合墊406之導電材料可沈積於薄晶種層上方。導電材料可藉由電化學電鍍製程、CVD、ALD、PVD、其類似者或其組合予以形成。在一實施例中，接合墊406之導電材料為銅、鎢、鋁、銀、金、錫、其類似者或其組合。
在圖24中，將封裝200置放於基板402之凹槽404內，使得運用導電連接器408將封裝200耦合至接合墊406。在一些實施例中，運用(例如)取置工具將封裝200置放於凹槽404內。在一實施例中，包括墊162的封裝200之表面可與基板402之表面水平。在一些實施例中，包括墊162的封裝200之表面可位於基板402之表面上方或下方。
導電連接器408可為焊球、金屬柱、控制塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微凸塊、無電式鍍鎳-無電式鍍鈀-浸金技術(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)成形凸塊，或其類似者。導電連接器408可包括諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似者或其組合之導電材料。在導電連接器408為焊料凸塊的實施例中，藉由最初經由諸如蒸鍍、電鍍、印刷、焊料轉移、植球或其類似者之此等常用方法形成焊料層來形成導電連接器408。一旦已在結構上形成焊料層，就可執行回焊以便將材料塑形成所要凸塊形狀。在另一實施例中，導電連接器408為藉由濺鍍、印刷、電鍍、無電式電鍍、CVD或其類似者而形成之金屬柱(諸如銅柱)。金屬柱可為無焊料的且具有實質上垂直側壁。在一些實施例中，金屬帽層(未圖示)形成於金屬柱連接器408之頂部上。金屬帽層可包括鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、其類似者或其組合，且可藉由鍍覆製程予以形成。
在一些實施例中，導電連接器408可經回焊以將封裝200附接至 接合墊406。導電連接器408將基板402(包括基板402中之金屬化層)電及/或實體耦合至第二封裝200。導電連接器408允許使感測器420及封裝200與基板402電耦合。
導電連接器408可在其上形成有環氧助焊劑(未圖示)，之後其運用在將封裝200附接至基板402之後剩餘的環氧助焊劑之環氧部分之至少一些進行回焊。此剩餘環氧部分可充當底膠以縮減應力且保護由回焊導電連接器408引起之接頭。在一些實施例中，底膠(未圖示)可形成於封裝200與基板402之間的凹槽404中且環繞導電連接器408。底膠可在附接封裝200之後藉由毛細流動製程予以形成，或可在附接封裝200之前藉由適合沈積方法予以形成。
在圖25A及圖25B中，將感測器420附接至基板402及封裝200。圖25B為圖25A中之結構的俯視圖，其中圖25A中之結構沿著圖25B之線A-A。如圖25B所說明，存在附接至包括封裝200及基板402之結構的四個感測器420(420-1、420-2、420-3及420-4)，且在其他實施例中，可將更多或更少感測器附接至包括封裝200及基板402之結構。在一些實施例中，凹槽404具有長度L1及寬度W1。在一些實施例中，長度L1在約5毫米(mm)至約10mm之範圍內，諸如約7.6mm。在一些實施例中，寬度W1在約5mm至約10mm之範圍內，諸如約8mm。
亦在圖25B中所說明，感測器420可為不同大小，使得其在凹槽404及基板402上方覆蓋不同量之區域，且在其他實施例中，感測器420可為相同大小。如圖25A所說明，感測器420可具有不同高度H3及H4，且在其他實施例中，感測器420可具有相同高度。在一些實施例中，感測器420-2之高度H3在基板之厚度H1之約80%至約120%的範圍內，諸如厚度H1之約90%。在一些實施例中，感測器420-4之高度H4在基板之厚度H1之約80%至約120%的範圍內，諸如厚度H1之約110%。
進一步在圖25B中所說明，感測器420中之至少一者可附接至封裝200及基板402兩者(參見圖25B中之420-2及420-3以及圖25A中之420-2)。此等感測器可「橋接」封裝200與基板402。「橋接」封裝200與基板402之感測器在平行於積體電路晶粒114之背側之平面中延伸超出第一封裝200及凹槽404之側向邊界(參見圖25A及圖25B)。另外，至少一個感測器420可僅附接至封裝200(參見420-1及420-4)，且至少一個感測器可僅附接至基板402。
感測器420可包括心跳速率監測器、環境光感測器、紫外線光感測器、環境溫度感測器、加速度計、陀螺儀、磁力計、氣壓感測器、血氧定量感測器、全球定位系統(GPS)感測器、膚電傳導感測器(有時被稱作皮膚電流回應感測器)、膚溫感測器、血液葡萄糖監測器、其類似者，或其組合。
感測器420藉由導電連接器424、接點區域422、接點區域410及墊162而耦合至基板402及封裝200。導電連接器424可相似於上文所描述之導電連接器408，且本文中不重複描述，但導電連接器408及424無需相同。在一些實施例中，接點區域422及410為接合墊。接合墊410及422可相似於所描述之接合墊406，且本文中不重複描述，但接合墊406、410及422無需相同。
藉由將封裝200嵌入於基板402之凹槽404內，可增加感測器420之數目及感測器420之大小。此允許封裝結構之組態及設計之較大靈活性。舉例而言，此封裝結構允許大於封裝200之面積(例如，包括由封裝200覆蓋之凹槽404之基板402在俯視圖中之總表面積)的總感測器面積(例如，包括由感測器420覆蓋之凹槽404之基板402在俯視圖中之總表面積)。
圖26、圖27A至圖27B、圖28至圖32及圖33A至圖33B為根據另一實施例之在用於形成封裝結構之製程期間之中間步驟的視圖。圖26、 圖27A、圖28至圖32及圖33A為剖面圖，圖27B及33B為俯視圖。此實施例相似於圖1至圖3、圖4A至圖4B、圖5至圖24及圖25A至圖25B之先前實施例，惟如下情形除外：在此實施例中，封裝200(例如，InFO封裝200)藉由導電元件(參見圖33A中之430)而非導電連接器(參見圖25A中之408)電耦合至基板402。此外，在此實施例中，可省略封裝200中之貫穿通路112。本文中將不重複相似於先前所描述之實施例之細節的關於此實施例之細節。
在圖26中，載體基板100包括在載體基板上方之離型層102，其中黏著劑103在離型層102上方。先前已描述載體基板100及離型層102且本文中不重複描述。黏著劑103形成於離型層102上方且可為任何適合黏著劑、環氧樹脂、晶粒附接膜(DAF)或其類似者。
在圖27A及圖27B中，將積體電路晶粒114置放於黏著劑103上。圖27B為圖27A中之結構的俯視圖，其中圖27A中之結構沿著圖27B之線A-A。在一些實施例中，可將另一黏著劑(未圖示)施加至積體電路晶粒114之背側，諸如至各別半導體晶圓之背側(參見圖4A中之116)。積體電路晶粒114可諸如藉由鋸切或切割予以單粒化，且使用(例如)取置工具予以置放。
如圖27B所說明，四個積體電路晶粒114(114-1、114-2、114-3及114-4)黏著於第一封裝區300及第二封裝區302中之每一者中，且在其他實施例中，更多或更少積體電路晶粒可黏著於每一區中。亦如圖27B所說明，積體電路晶粒114可為不同大小，且在其他實施例中，積體電路晶粒114可為相同大小。先前已描述積體電路晶粒114且本文中不重複描述。
在圖28中，將封裝物130形成於各種組件上。封裝物130可為模塑料、環氧樹脂或其類似者，且可藉由壓縮成型、轉移成型或其類似者予以施加。在固化之後，封裝物130可經受研磨製程以暴露晶粒連 接器126。晶粒連接器126及封裝物130之頂部表面在研磨製程之後共面。在一些實施例中，舉例而言，若晶粒連接器126已經被暴露，則可省略研磨。
在圖29中，將前側重佈結構160形成於積體電路晶粒114及封裝物130上方。前側重佈結構160之金屬化圖案138、146及154以及墊162經由晶粒連接器126電耦合至積體電路晶粒114。先前已在圖6至圖16中描述前側重佈結構160之形成且本文中不重複描述。
在圖30中，執行載體基板脫接以將載體基板100自積體電路晶粒114結構之背側(例如，黏著劑103)拆離(脫接)。根據一些實施例，脫接包括將諸如雷射光或UV光之光投影於離型層102上，使得離型層102在光之熱下分解且可移除載體基板100。接著，將結構翻轉並置放於膠帶170上。
在圖31中，藉由沿著切割道區(例如，在鄰近區300及302之間)進行鋸切184來執行單粒化製程。鋸切184將第一封裝區300自第二封裝區302單粒化。圖32說明所得的經單粒化結構。單粒化引起封裝500被單粒化，封裝500可來自第一封裝區300或第二封裝區302中之一者。封裝500亦可被稱作InFO封裝500。
進一步在圖32中，將封裝500置放於基板402之凹槽404內，使得運用黏著劑103將封裝500黏著至基板402。在一些實施例中，運用(例如)取置工具將封裝500置放於凹槽404內。在一實施例中，包括墊162的封裝500之表面可與基板402之表面水平。在一些實施例中，包括墊162的封裝500之表面可位於基板402之表面上方或下方。
在圖33A及圖33B中，將感測器420附接至基板402及封裝500。圖33B為圖33A中之結構的俯視圖，其中圖33A中之結構沿著圖33B之線A-A。如圖33B所說明，存在附接至包括封裝500及基板402之結構的四個感測器420(420-1、420-2、420-3及420-4)，且在其他實施例中， 可將更多或更少感測器附接至包括封裝500及基板402之結構。先前已描述感測器420及基板402且本文中不重複描述。
在此實施例中，存在藉助於墊162及接點區域410將封裝500耦合至基板402之導電元件430。導電元件430允許使感測器420及封裝500與基板402電耦合。
如圖33B所說明，感測器420中之至少一者可附接至封裝500及基板402兩者(參見圖33B中之420-2及420-3以及圖33A中之420-2)。此等感測器可「橋接」封裝500與基板402。另外，至少一個感測器420可僅附接至封裝500(參見420-1及420-4)且至少一個感測器可僅附接至基板402。
導電元件430可為導電導線、可撓性電路或其類似者，其中一個端耦合至基板402之接點區域410且另一端耦合至封裝500之墊162中之一者。在導電導線接合實施例中，可藉由在接點區域410上形成球狀接合且在封裝500之墊162上形成縫補接合來形成導電元件430。
圖34為根據另一實施例之封裝結構的剖面圖。此實施例相似於圖26、圖27A至圖27B、圖28至圖32及圖33A至圖33B中之實施例，惟如下情形除外：此實施例包括耦合至封裝500且鄰接於基板402之至少一部分的組件602。本文中將不重複相似於先前所描述之實施例之細節的關於此實施例之細節。
組件602運用接點區域622及導電連接器624而耦合至封裝500。接點區域622及導電連接器624可分別相似於上文所描述之接點區域422及導電連接器424，且本文中不重複描述，但接點區域422及622以及導電連接器424及624無需相同。
在一實施例中，組件602為熱電產生器(有時被稱作熱電產生器收集器)。在組件602為熱電產生器的一個實施例中，表面604A及604B中之至少一者能夠與穿戴包括圖34之封裝結構的裝置(例如，智慧型 手錶)之人員的皮膚進行直接接觸，使得熱電產生器602可將來自該人員之熱轉換成電能以輔助供電給該裝置。舉例而言，在此實施例中，經轉換電能可直接地供電給該裝置，或其可儲存於該裝置中之電池(未圖示)中。在組件602為熱電產生器的另一實施例中，至少表面606與基板402接觸，且基板402能夠與穿戴包括圖34之封裝結構的裝置之人員的皮膚進行直接接觸，使得該人員之熱可經由基板402轉移至熱電產生器602之表面606，熱電產生器602可將所轉移熱轉換成電能以輔助供電給該裝置。
如圖34所說明，組件602具有在封裝500上方延伸之高度H5且可嵌入於基板402內達深度H6。在一些實施例中，深度H5在基板之厚度H1之約10%至約40%的範圍內，諸如厚度H1之約25%。在一些實施例中，深度H6在基板之厚度H1之約10%至約40%的範圍內，諸如厚度H1之約25%。
藉由將封裝200嵌入於基板402之凹槽404內，可增加感測器420之數目及感測器420之大小。此允許封裝結構之組態及設計之較大靈活性。舉例而言，此封裝結構允許大於封裝200之面積(例如，包括由封裝200覆蓋之凹槽404之基板402在俯視圖中之總表面積)的總感測器面積(例如，包括由感測器420覆蓋之凹槽404之基板402在俯視圖中之總表面積)。
前述內容概述若干實施例之特徵，使得熟習此項技術者可更佳地理解本揭露之態樣。熟習此項技術者應瞭解，其可容易使用本揭露作為設計或修改用於實行本文中所介紹之實施例之相同目的及/或達成本文中所介紹之實施例之相同優點的其他製程及結構之基礎。熟習此項技術者亦應認識到，此等等效構造並不脫離本揭露之精神及範疇，且其可在不脫離本揭露之精神及範疇的情況下在本文中作出各種改變、替換及變更。

Claims (9)

  1. 一種封裝結構形成方法，其包含：形成一第一接合墊於一第一基板之一凹槽的一底部表面上；在形成該第一接合墊後，將一第一封裝置放於該第一基板之該凹槽的該底部表面上，該第一封裝包含一第一晶粒，其中在將該第一封裝置放於該第一基板之該凹槽的該底部表面上後，該凹槽的該底部表面實體支撐該第一封裝，及其中在將該第一封裝置放於該凹槽的該底部表面上前，該凹槽被完整地圖案化在該第一基板，該第一封裝運用一第一導電連接器而電耦合至該第一基板之該第一接合墊，其中該第一導電連接器被設置在該第一封裝面向該凹槽的該底部表面的一表面上；及將一第一感測器附接至該第一封裝及該第一基板，該第一感測器電耦合至該第一封裝及該第一基板。
  2. 如請求項1之方法，其中該第一感測器包含一心跳速率監測器、一環境光感測器、一紫外線光感測器、一環境溫度感測器、一加速度計、一陀螺儀、一磁力計、一氣壓感測器、一血氧定量感測器、一全球定位系統(GPS)感測器、一膚電傳導感測器、一膚溫感測器、一血液葡萄糖監測器，或其一組合。
  3. 如請求項1之方法，其進一步包含：在該第一基板之一第一表面上形成一第二接合墊，該第一表面在該第一基板之該凹槽外部，該第一封裝運用一第二導電連接器而電耦合至該第一基板之該第二接合墊。
  4. 如請求項1之方法，其進一步包含：在將該第一封裝置放於該第一基板之該凹槽的該底部表面上後，將一第二感測器附接至該第一封裝，該第二感測器電耦合 至該第一封裝，其中該第一感測器和該第二感測器皆直接接合至該第一封裝的一表面，及其中該第一感測器和該第二感測器更直接接合至該第一基板的一第二表面，該第二表面高於並實質上平行於該第一基板之該凹槽的該底部表面。
  5. 如請求項4之方法，其進一步包含：將一第三感測器附接至該第一封裝及該第一基板，該第三感測器電耦合至該第一封裝及該第一基板。
  6. 如請求項1之方法，其進一步包含：形成該第一封裝，該形成該第一封裝包含：運用一封裝物至少側向地封裝該第一晶粒，其中該封裝物的至少一部分被設置在該凹槽；及在該第一晶粒及該封裝物上方形成一第一重佈結構，該第一感測器電耦合至該第一重佈結構。
  7. 如請求項6之方法，其進一步包含：在該第一基板之該凹槽中形成一第三接合墊；且其中該形成該第一封裝進一步包含：形成自該第一重佈結構至該第一晶粒之一背側延伸通過該封裝物的一貫穿通路，該第一晶粒之一主動側耦合至該第一重佈結構，該主動側與該背側相對，該第一封裝之該貫穿通路運用一第一導電連接器而電耦合至該第一基板之該第三接合墊。
  8. 一種封裝結構形成方法，其包含：形成一第一接合墊於一第一基板之一凹槽的一底部表面上；形成一第一封裝，該形成該第一封裝包含：運用一封裝物至少側向地封裝一第一晶粒，該第一晶粒具有一主動側及一背側，該背側與該主動側相對； 在該第一晶粒及該封裝物上方形成一第一重佈結構，該第一重佈結構耦合至該第一晶粒之該主動側；及形成自該第一重佈結構延伸通過該封裝物至該第一晶粒之該背側的一水平的一貫穿通路；在形成該第一接合墊後，將該第一封裝耦合至一第一基板，該第一封裝之至少一部分在該第一基板中之一凹槽內延伸，其中在將該第一封裝耦合至該第一基板前，該凹槽被圖案化在該第一基板，及其中該凹槽延伸高於該封裝物，該第一封裝的該貫穿通路被運用一第一導電連接器電耦合至該第一基板的該第一接合墊，該第一導電連接器被設置為直接接觸該第一導電墊；及將一第一感測器接合至該第一封裝及該第一基板，該第一感測器電耦合至該第一封裝及該第一基板。
  9. 一種封裝結構，其包含：一第一封裝，其在一第一基板之一凹槽中，該第一封裝包含一第一晶粒；及一第一感測器，其電耦合至該第一封裝及該第一基板，該第一感測器具有直接地在該第一基板之該凹槽上方的一第一部分及直接地在該第一基板之位於該凹槽外部之一部分上方的一第二部分。
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