CN113838840A - 半导体封装及制造半导体封装的方法 - Google Patents

半导体封装及制造半导体封装的方法 Download PDF

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CN113838840A
CN113838840A CN202110037312.XA CN202110037312A CN113838840A CN 113838840 A CN113838840 A CN 113838840A CN 202110037312 A CN202110037312 A CN 202110037312A CN 113838840 A CN113838840 A CN 113838840A
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die
interposer
protective layer
molding material
substrate
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曾淑容
李福仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在本发明实施例中，一种半导体封装包括中介件、管芯、保护层、多个第一电连接件及第一模制材料。管芯包括第一表面及与第一表面相对的第二表面，且管芯通过第一表面结合到中介件。保护层设置在管芯的第二表面上。第一电连接件设置在管芯旁边。第一模制材料设置在管芯、保护层及第一电连接件旁边。

Description

半导体封装及制造半导体封装的方法
技术领域
本发明实施例涉及一种半导体封装及制造半导体封装的方法。
背景技术
近年来，由于各种电子器件(例如，晶体管、二极管、电阻器、电容器等)的集成密度不断提高，半导体行业已经历快速增长。在很大程度上，集成密度的此种提高来自于最小特征尺寸(minimum feature size)的连续减小，此使得更多的器件能够整合到给定的区域中。
这些更小的电子器件还需要比先前的封装占据更少面积的更小的封装。有前景的半导体封装之一是用于面向云计算、数据中心及超级计算机应用的先进产品的“衬底上晶片上芯片(chip on wafer on substrate，CoWoS)”结构。尽管现有的半导体封装对于其预期目的来说一般是足够的，然而其尚未在所有方面都完全令人满意。
发明内容
本发明实施例的一种半导体封装包括中介件、管芯、保护层、多个第一电连接件及第一模制材料。管芯包括第一表面及与第一表面相对的第二表面，且管芯通过第一表面结合到中介件。保护层设置在管芯的第二表面上。第一电连接件位于管芯旁边。第一模制材料设置在管芯、保护层及第一电连接件旁边。
本发明实施例的一种半导体封装包括中介件、管芯及具有电路结构的衬底。管芯结合到且电连接到中介件，且管芯上具有保护层。中介件结合到且电连接到具有电路结构的衬底，且管芯设置在中介件与具有电路结构的衬底之间且通过中介件电连接到具有电路结构的衬底。
本发明实施例的一种制造半导体封装的方法包括以下步骤。将管芯结合到中介件上以电连接到中介件，其中管芯上具有保护层，且管芯设置在保护层与中介件之间。在中介件之上形成第一模制材料以包封管芯，其中第一模制材料覆盖保护层。在管芯由保护层保护的同时，对第一模制材料进行薄化。
附图说明
图1A到图1D是根据一些实施例的形成管芯的方法中的各种阶段的示意性剖视图。
图2A到图2H是根据一些实施例的制造半导体封装的方法中的各种阶段的示意性剖视图。
图3是根据一些实施例的半导体封装的示意性俯视图。
图4示出根据一些实施例的制造半导体封装的方法。
图5是根据一些实施例的半导体封装的示意性剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。为简化本公开，下文阐述组件及布置的具体实例。当然，这些仅为实例而非旨在进行限制。例如，以下说明中将第二特征形成在第一特征“之上”或第一特征“上”可包括其中第二特征与第一特征被形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成有附加特征、进而使得所述第二特征与所述第一特征可能不直接接触的实施例。另外，本公开可能在各种实例中重复使用参考编号和/或字母。此种重复使用是出于简明及清晰的目的，且自身并不表示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“顶部(top)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”及类似用语等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。除图中所绘示的取向以外，所述空间相对性用语旨在还囊括器件在使用或操作中的不同取向。装置可被另外取向(旋转90度或处于其他取向)，且本文所使用的空间相对性描述语可同样相应地作出解释。
也可包括其他特征及工艺。例如，可包括测试结构，以帮助对三维(three-dimensional，3D)封装或三维集成电路(3D integrated circuit，3DIC)器件进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试垫，以使得能够对3D封装或3DIC进行测试、对探针和/或探针卡(probe card)进行使用以及进行类似操作。可对中间结构以及最终结构实行验证测试。另外，本文所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法来使用，以提高良率(yield)并降低成本。
图1A到图1D是根据一些实施例的形成管芯的方法中的各种阶段的示意性剖视图。
参照图1A，提供半导体晶片20。在一些实施例中，半导体晶片20包括任意数目的管芯22。半导体晶片20可包括块状半导体衬底(bulk semiconductor substrate)、绝缘体上半导体(semiconductor-on-insulator，SOI)衬底或类似物。半导体晶片20的半导体材料可为：硅、锗；化合物半导体，包括硅锗、碳化硅、镓砷、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或者其组合。也可使用例如多层式衬底或梯度衬底等其他衬底。半导体晶片20可为经掺杂的或未经掺杂的。半导体晶片20可包括可用于产生管芯22的设计的所期望结构及功能要求的各种各样的有源器件及无源器件(例如电容器、电阻器、电感器及类似物)。可使用任何合适的方法将有源器件及无源器件形成在半导体晶片20内或者形成在半导体晶片20的有源表面20a上。
在有源表面20a上形成包括一个或多个介电层及相应金属化图案的内连线结构24。介电层中的金属化图案可例如通过使用通孔和/或迹线在器件之间路由电信号，且还可包含各种电器件(例如电容器、电阻器、电感器或类似物)。所述各种器件及金属化图案可进行内连以实行一个或多个功能。所述功能可包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路系统或类似物。
在一些实施例中，将结合垫26电连接到内连线结构24，且形成电连接件28且将电连接件28电连接到结合垫26，以提供到电路系统及器件的外部电连接。在一些实施例中，利用电连接件28将管芯22结合到其他结构。电连接件28可为受控塌陷芯片连接(controlledcollapse chip connection，C4)凸块、例如球栅阵列(ball grid array，BGA)等焊球、金属柱、无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion goldtechnique，ENEPIG)形成的凸块或类似物。电连接件28包含例如焊料、铜、铝、金、镍、银、钯、锡、类似物或其组合等导电材料。在电连接件28是焊料凸块的实施例中，通过例如蒸发、电镀、印刷、焊料转移、植球或类似方法等各种方法最初在结合垫26上形成焊料层来形成电连接件28。在此实施例中，一旦已在结合垫26上形成焊料层，就实行回流(reflow)以将所述材料造型成所期望的凸块形状。在另一实施例中，电连接件28是通过溅镀、印刷、电镀、化学镀覆、化学气相沉积(chemical vapor deposition，CVD)或类似方法形成的金属柱(例如铜柱)。在实施例中，金属柱是无焊料的，且具有实质上垂直的侧壁。在一些实施例中，在金属柱电连接件28的顶部上形成金属顶盖层(metal cap layer)(未示出)。在一些实施例中，金属顶盖层包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金、类似物或其组合，且通过镀覆工艺形成所述金属顶盖层。所属领域中的普通技术人员将理解，以上实例是出于例示目的而提供。对于给定的应用，可适当地使用其他电路系统。
参照图1B，对半导体晶片20的表面20b实行薄化工艺(thinning process)以将半导体晶片20薄化。表面20b与有源表面20a相对设置。有源表面20a可为前侧表面，且表面20b可为背侧表面。薄化工艺可包括蚀刻工艺、研磨工艺、类似工艺或其组合。在一些实施例中，在薄化工艺之后，半导体晶片20、内连线结构24及电连接件28具有介于约100μm到约300μm范围内的组合厚度。
参照图1C，在半导体晶片20的表面20b上形成保护材料30。在一些实施例中，保护材料30完全覆盖半导体晶片20的表面20b。保护材料30可为例如胶水、粘合剂、类似物或其组合等电绝缘材料。保护材料30的材料可包括环氧树脂、酚醛树脂、丙烯酸橡胶、二氧化硅填料、类似物或其组合。保护材料30可与晶片的表面20b直接接触(例如，与晶片的半导体材料直接接触)。可通过涂布工艺(coating process)、叠层工艺(lamination process)、类似工艺或其组合来形成保护材料30。
参照图1D，将其上具有保护材料30的半导体晶片20单体化成各别的管芯22及各别的保护层32。单体化可包括锯切(sawing)、切割(dicing)或类似工艺。通常，尽管管芯22可具有不同的电路系统，然而管芯22包含例如器件及金属化图案等相同的电路系统。管芯22中的每一者可包括一个或多个逻辑管芯(例如，中央处理器(central processing unit)、图形处理单元(graphics processing unit)、系统芯片(system-on-a-chip)、现场可编程门阵列(field-programmable gate array，FPGA)、微控制器或类似物)、存储器管芯(例如，动态随机存取存储器(dynamic random access memory，DRAM)管芯、静态随机存取存储器(static random access memory，SRAM)管芯或类似物)、电源管理管芯(例如，电源管理集成电路(power management integrated circuit，PMIC)管芯、射频(radio frequency，RF)管芯、传感器管芯、微机电系统(micro-electro-mechanical-system，MEMS)管芯、信号处理管芯(例如，数字信号处理(digital signal processing，DSP)管芯)、前端管芯(例如，模拟前端(analog front-end，AFE)管芯)、类似物或其组合。此外，在一些实施例中，管芯22为不同的尺寸(例如，不同的高度和/或表面积)，且在其他实施例中，管芯22为相同的尺寸(例如，相同的高度和/或表面积)。
管芯22具有有源表面22a及与有源表面22a相对的表面22b。有源表面22a可为前侧表面，且表面22b可为背侧表面。每一管芯22在表面22b上具有保护层32。保护层32的尺寸对管芯22的尺寸的比率可介于约1.1到约0.95范围内。在实施例中，保护层32的尺寸是在中介件102(interposer，如图2C中所示)上的投影面积，且管芯22的尺寸是在中介件102(如图2C中所示)上的投影面积。在实施例中，在管芯22的整个表面22b上形成保护层32。在此种实施例中，保护层32的侧壁与管芯22的侧壁实质上齐平。在一些实施例中，管芯22在其表面22b上具有保护层32，且因此防止管芯22的表面22b被损坏。
图2A到图2H是根据一些实施例的制造半导体封装的方法中的各种阶段的示意性剖视图。图3是根据一些实施例的半导体封装的示意性俯视图。为例示简明及清晰起见，在图3所示俯视图中仅示出几个元件。在一些实施例中。图2G是沿着图3所示的线I-I截取的半导体封装的剖视图。
参照图2A，提供中介件102。中介件102可包括衬底104、多个穿孔106及重布线结构108、110。在一些实施例中，衬底104由例如硅、锗、金刚石或类似物等元素半导体制成。在其他实施例中，衬底104由例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、类似物或其组合等化合物半导体制成。在实施例中，衬底104是绝缘体上硅(silicon-on-insulator，SOI)衬底。一般来说，SOI衬底包括由例如外延硅、锗、硅锗、SOI、绝缘体上硅锗(silicon germanium on insulator，SGOI)或其组合等半导体材料形成的层。在替代实施例中，衬底104由预浸料(其包含环氧树脂、树脂、二氧化硅填料和/或玻璃纤维)、味之素增层膜(Ajinomoto Buildup Film，ABF)、树脂涂布式铜箔(resin coated copper foil，RCC)、聚酰亚胺、感光成像介电质(photo image dielectric，PID)、陶瓷芯、玻璃芯、模制化合物、类似物或其组合制成。
穿孔106穿透衬底104。在一些实施例中，穿孔106是由例如铝、钛、铜、镍、钨、其合金、类似物或其组合等导电材料制成。在衬底104的两侧上设置重布线结构108、110，且将重布线结构108、110电连接到穿孔106。将重布线结构108、110形成为连接各种器件以形成功能电路系统。重布线结构108、110包括交替堆叠的多个介电层与多个导电图案化层。介电层可包含氮化硅、碳化硅、氧化硅、低介电常数介电质(low-k dielectric)(例如碳掺杂氧化物)、极低介电常数介电质(extremely low-k dielectric)(例如多孔碳掺杂二氧化硅)、聚合物(例如环氧树脂、聚酰亚胺、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzoxazole，PBO))、类似物或其组合。在一些实施例中，通过化学气相沉积(CVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)、旋涂介电质工艺(spin-on-dielectric process)、类似工艺或其组合来沉积介电层。导电图案化层可包含金属或金属合金(包括铜、铝、钨、类似物或其组合)。在一些实施例中，通过沉积、镶嵌、双镶嵌(dual damascene)或类似工艺来形成导电图案化层。
在一些实施例中，中介件102是包含至少一个功能器件或集成电路器件的有源中介件。在一些实例中，此种有源中介件被称为“含器件中介件(device-containinginterposer)”。在一些实施例中，功能器件包括有源器件、无源器件或其组合。功能器件可包括晶体管、电容器、电阻器、二极管、光电二极管、熔丝器件、类似物或其组合。在一些实施例中，功能器件包括栅极介电层、栅电极、源极/漏极区、间隔件及类似物。在替代性实施例中，中介件102是无源中介件，其缺少功能器件或集成电路器件。在一些实例中，此种无源中介件被称为“无器件中介件(device-free interposer)”。
在一些实施例中，在中介件102上形成一个或多个表面器件120。可通过电连接件122及结合垫112将表面器件120安装到重布线结构108上。结合垫112将随后结合的表面器件120电耦合到重布线结构108。在一些实施例中，结合垫112包括例如通过PVD、CVD、ALD、类似工艺或其组合沉积在中介件102之上的薄晶种层(seed layer)(未示出)。晶种层是由铜、钛、镍、金、类似物或其组合制成。在一些实施例中，在薄晶种层之上沉积结合垫112的导电材料。在一些实施例中，通过电化学镀覆工艺、CVD、ALD、PVD、类似工艺或其组合来形成导电材料。在实施例中，结合垫112的导电材料是铜、钨、铝、银、金、类似物或其组合。
在实施例中，结合垫112是凸块下金属(under bump metallurgy，UBM)，且包括三个导电材料层(例如钛层、铜层及镍层)。然而，用于形成UBM的材料及层的许多合适的布置方式在本公开的设想范围内。例如，此种布置包括合适的铬/铬-铜合金/铜/金布置方式、钛/钛钨/铜布置方式、铜/镍/金布置方式或类似布置方式。此外，可用于UBM的任何合适的材料或材料层也在本申请的设想范围内。
在形成结合垫112之后，通过电连接件122及结合垫112将具有电连接件122的表面器件120结合到中介件102的表面102a。表面器件120可用于向要形成的封装结构提供附加的功能性(functionality)或程序设计(programming)。在实施例中，表面器件120包括表面安装器件(surface mount device，SMD)或集成无源器件(integrated passive device，IPD)，且IPD包括例如期望连接到封装结构且与封装结构结合使用的电阻器、电感器、电容器、跨接线(jumper)、类似物或其组合等无源器件。表面器件120可具有不同的尺寸(例如高度、宽度或其组合)。在实施例中，如图2A中所示，具有较大尺寸的表面器件120设置在中介件102的中心区上，且由具有较小尺寸的表面器件120环绕。然而，本公开不限于此。
将电连接件122结合到表面器件120上的接触件或电极。电连接件122可为受控塌陷芯片连接(C4)凸块、例如球栅阵列(BGA)等焊球、金属柱、无电镀镍钯浸金技术(ENEPIG)形成的凸块或类似物。电连接件122包含例如焊料、铜、铝、金、镍、银、钯、锡、类似物或其组合等导电材料。在电连接件122是焊料凸块的实施例中，通过例如蒸发、电镀、印刷、焊料转移、植球或类似方法等各种方法最初在结合垫112上形成焊料层来形成电连接件122。在此实施例中，一旦已在结合垫112上形成焊料层，就实行回流以将所述材料造型成所期望的凸块形状。在一些实施例中，表面器件120与中介件102之间的结合是焊料结合。在实施例中，通过回流工艺将表面器件120结合到中介件102。在此回流工艺期间，电连接件122与结合垫112及表面器件120接触，以将表面器件120物理耦合到及电耦合到中介件102。
在放置表面器件120之后，在表面器件120上及表面器件120周围模制模制材料130。模制材料130填充表面器件120之间的间隙。在实施例中，形成模制材料130，且模制材料130填充表面器件120与重布线结构108之间的间隙。在一些实施例中，模制材料130是由模制化合物、模制底部填充胶、环氧树脂、树脂、类似物或其组合制成。在一些实施例中，提供模具槽(mold chase)(未示出)，且模具槽在施加及固化模制材料130的期间对模制材料130进行保持及造型。例如，模具槽具有用于在施加模制材料130时保持模制材料130的边界或其他特征。模具槽可包括释放膜(release film)，以帮助将模具槽与模制材料130分开。例如，在模制材料130是环氧树脂或树脂的实施例中使用释放膜，以防止模制化合物材料粘合到模具槽表面。可基于模具槽以及表面器件120的高度来调整模制材料130的厚度。在实施例中，模制材料130具有在约700μm到约800μm之间的厚度。在一些实施例中，模制材料130的表面130a高于表面器件120的表面120a。即，模制材料130可覆盖表面器件120的表面120a。
参照图2B，将模制材料130部分移除到所需厚度。在实施例中，实行例如研磨工艺等薄化工艺以将模制材料130薄化，直到获得所需厚度为止而不暴露出表面器件120的表面120a。模制材料130可覆盖表面器件120的表面120a。在一些实施例中，模制材料130通过压力板(pressure plate)或模具(未示出)经历压力模制工艺(pressure molding process)，以对模制材料130进行造型。在一些实施例中，在薄化工艺之后，模制材料130所具有的厚度介于400μm到500μm范围内。
参照图2C，将其之上具有表面器件120及模制材料130的中介件102上下翻转。然后，将其之上具有保护层32的管芯22结合到中介件102。在一些实施例中，将图1D所示管芯22拾取且放置到中介件102的表面102b上。通过电连接件28及结合垫114将管芯22结合到中介件102。结合垫114将随后结合的管芯22电耦合到重布线结构110。在一些实施例中，将结合垫116形成为将随后结合的电连接件146(如图2G中所示)电耦合到重布线结构110。在实施例中，同时形成结合垫116与结合垫114。尽管结合垫112、114及116未必相同，然而结合垫114、116可相似于上述结合垫112，且本文中不再予以赘述。
在一些实施例中，管芯22与中介件102之间的结合是焊料结合或直接金属对金属结合(例如铜对铜结合或锡对锡结合)。在实施例中，通过回流工艺将管芯22结合到中介件102。在此回流工艺期间，电连接件28与结合垫114及管芯22接触，以将管芯22物理耦合到及电耦合到中介件102。
在一些实施例中，保护层32的尺寸(例如，在中介件102上的投影面积)对中介件102的尺寸(例如，中介件102的表面102b的面积)的比率介于约0.5到约0.9范围内。在此种实施例中，如图3中所示，保护层32的面积等于保护层32的宽度W1与长度L1的乘积，且中介件102的表面102b的面积等于中介件102的宽度W2与长度L2的乘积。在一些实施例中，在中介件102的表面102b的中心区上设置管芯22。即，管芯22的第一侧壁S1及中介件102的第一侧壁S1’之间的水平距离d1与管芯22的和第一侧壁S1相对的第二侧壁S2及中介件102的和第一侧壁S1’相对的第二侧壁S2’之间的水平距离d1’实质上相同。相似地，管芯22的第三侧壁S3及中介件102的第三侧壁S3’之间的水平距离d2与管芯22的和第三侧壁S3相对的第四侧壁S4及中介件102的和第三侧壁S3’相对的第四侧壁S4’之间的水平距离d2’实质上相同。然而，本公开不限于此。
管芯22具有厚度t1，且保护层32具有厚度t2。厚度t1可为管芯22的厚度(如图2C中所示)或者管芯22与其上的电连接件28的总厚度。在一些实施例中，保护层32的厚度t2对管芯22的厚度t1的比率介于约5％到约50％范围内。在实施例中，厚度t1不大于80μm，厚度t2不大于30μm。在实施例中，管芯22的厚度t1介于约100μm到约300μm范围内，且厚度t2介于约5μm到约50μm范围内。
参照图2D，在结合管芯22之后，在管芯22上及管芯22周围模制模制材料140。模制材料140包封管芯22且填充电连接件28之间的间隙。在实施例中，形成模制材料140，且模制材料140填充管芯22与重布线结构110之间的间隙。在一些实施例中，模制材料140是由模制化合物、模制底部填充胶、环氧树脂、树脂、类似物或其组合制成。尽管模制材料130与140未必相同，然而模制材料140可相似于上述模制材料130，且本文中不再予以赘述。可基于模具槽以及管芯22的高度来调整模制材料140的厚度。在实施例中，模制材料140具有在约400μm到约500μm之间的厚度。在一些实施例中，模制材料140的表面140a高于保护层32的表面32a。换句话说，模制材料140覆盖保护层32的表面32a。
参照图2E，将模制材料140部分移除以暴露出保护层32。在实施例中，实行例如研磨工艺等薄化工艺以将模制材料140薄化，直到模制材料140的表面140a与保护层32的表面32a实质上共面为止。在实施例中，保护层32实质上没有通过薄化工艺移除，在薄化工艺之后模制材料140所具有的厚度实质上等于管芯22的厚度t1与保护层32的厚度t2的总和。在替代性实施例中，保护层32通过薄化工艺被部分移除，而管芯22保持完整而没有被移除。在薄化工艺期间，管芯22由保护层32保护而免受损坏。因此，防止由薄化工艺导致在管芯22的表面22b上形成研磨痕迹(grinding mark)，且增强了管芯强度。
参照图2F，在模制材料140中形成多个开口142以暴露出结合垫116。在一些实施例中，通过激光烧蚀或钻孔工艺(laser ablation or drilling process)、蚀刻工艺、类似工艺或其组合来形成开口142。开口142可具有不垂直及不平行于中介件102的表面102b的侧壁144，且侧壁144可彼此不同。
参照图2G，在开口142中形成多个电连接件146，以电连接到结合垫116。在实施例中，尽管可替代地使用任何合适的材料，然而电连接件146是包含例如焊料等共晶材料(eutectic material)的球栅阵列(BGA)。在电连接件146是焊料凸块的实施例中，使用例如直接落球工艺(direct ball drop process)等落球方法来形成电连接件146。在另一实施例中，通过例如蒸发、电镀、印刷、焊料转移等任何合适的方法最初形成锡层、且然后实行回流以便将所述材料造型成所期望的凸块形状来形成焊料凸块。在一些实施例中，电连接件146从模制材料140突出。例如，电连接件146的表面146a高于保护层32的表面32a。在替代性实施例中，通过多个步骤来形成电连接件146。详细来说，在结合垫116上形成第一电连接件(未示出)，且形成模制材料140并将模制材料140图案化以暴露出第一电连接件。然后，在第一电连接件上形成第二电连接件，且通过回流工艺将第二电连接件与第一电连接件接合以形成电连接件146。
参照图2H，进一步将图2G所示结构贴合到具有电路结构的衬底200，以形成半导体封装10。在一些实施例中，通过电连接件146将图2G所示结构结合到具有电路结构的衬底200。具有电路结构的衬底200可为封装衬底、另一管芯/晶片、印刷电路板、高密度内连线或类似物。具有电路结构的衬底200可包括衬底202、穿孔204、重布线结构206、208及电连接件210。穿孔204穿透衬底202。重布线结构206、208设置在衬底202的相对两侧上，且重布线结构206、208通过穿孔204彼此电连接。电连接件210相对于衬底202与中介件102相对设置，且可转而连接到另一衬底(未示出)。
在一些实施例中，具有电路结构的衬底200包括空腔212，进而使得管芯22延伸到形成在下伏的具有电路结构的衬底200中的空腔212中。在一些实施例中，在保护层32与具有电路结构的衬底200之间形成间隙214。由于具有空腔212，防止保护层32与具有电路结构的衬底200接触。在此种实施例中，由于电连接件146的尺寸不再需要大于管芯22与保护层32的总厚度，因此电连接件146的尺寸可能小于使用不具有空腔的衬底时的电连接件146的尺寸。因此，更薄的总体封装是可能的。然而，本公开不限于此。在替代性实施例中，由于保护层32是不导电的，因此保护层32与具有电路结构的衬底200接触，即不在管芯22与具有电路结构的衬底200之间形成间隙。在省略空腔的替代性实施例中，电连接件146具有更大的高度，以维持具有电路结构的衬底200与管芯22之间的间隙。
在一些实施例中，在薄化工艺期间，管芯22的表面22b由保护层32保护以免被暴露出和/或损坏。因此，防止由薄化工艺导致在管芯22上形成研磨痕迹，且增强了管芯强度。因此，当实行例如回流工艺等热工艺和/或施加外力时，管芯22免于开裂。
图4示出根据一些实施例的制造半导体封装的方法。尽管所述方法被示出和/或阐述为一系列动作或事件，然而应理解，所述方法不限于所示出的次序或动作。因此，在一些实施例中，所述动作以与所示出的次序不同的次序来施行和/或同时施行。此外，在一些实施例中，所示出的动作或事件被细分成多个动作或事件，这些动作或事件可在分开的时间施行或者与其他动作或子动作同时施行。在一些实施例中，省略一些所示出的动作或事件，且包括其他未示出的动作或事件。
在动作302处，将管芯结合到中介件上以电连接到中介件，其中管芯上具有保护层，且管芯设置在保护层与中介件之间。图2A示出对应于动作302的一些实施例的剖视图。
在动作304处，在中介件之上形成模制材料以包封管芯，其中第一模制材料覆盖保护层。图2D示出对应于动作304的一些实施例的剖视图。
在动作306处，在管芯由保护层保护的同时，对模制材料进行薄化。图2E示出对应于动作306的一些实施例的剖视图。
在一些实施例中，还包括将中介件结合到具有电路结构的衬底上，其中管芯设置在中介件与具有电路结构的衬底之间。图2H示出对应于此动作的一些实施例的剖视图。
图5所示半导体封装10可相似于图2H所示半导体封装10，且其之间的不同之处在于，图2C中的保护层32是在对模制材料140实行薄化工艺之前形成，而图5中的保护层32是在对模制材料140实行薄化工艺之后形成。在此种实施例中，对模制材料140进行薄化，直到模制材料140的表面140a与管芯22的表面22b实质上共面为止。在薄化工艺之后，在管芯22的表面22b上形成保护层32。因此，保护层32的表面32a从模制材料140的表面140a突出。在此种实施例中，通过涂布工艺、叠层工艺、类似工艺或其组合来形成保护层32。在一些实施例中，当实行例如回流工艺等热工艺和/或施加外力时，保护层32保护管芯22免于开裂。
在一些实施例中，管芯的背侧表面由保护层保护以免被暴露出和/或损坏。因此，防止由薄化工艺导致在管芯上形成研磨痕迹，且增强了管芯强度。因此，当实行例如回流工艺等热工艺和/或施加外力时，管芯免于开裂。因此，包括管芯的半导体封装可具有良好的性能。
根据本公开的一些实施例，一种半导体封装包括中介件、管芯、保护层、多个第一电连接件及第一模制材料。管芯包括第一表面及与第一表面相对的第二表面，且管芯通过第一表面结合到中介件。保护层设置在管芯的第二表面上。第一电连接件位于管芯旁边。第一模制材料设置在管芯、保护层及第一电连接件旁边。
在一些实施例中，所述第一模制材料的表面与所述保护层的表面实质上共面。
在一些实施例中，所述保护层从所述第一模制材料突出。
在一些实施例中，所述第一电连接件从所述第一模制材料突出。
在一些实施例中，所述保护层的材料不同于所述第一模制材料的材料。
在一些实施例中，所述半导体封装进一步包括至少一个表面安装器件，其中所述至少一个表面安装器件相对于所述中介件与所述管芯相对设置。
在一些实施例中，所述半导体封装进一步包括包封及覆盖所述至少一个表面安装器件的第二模制材料。
在一些实施例中，所述管芯包括位于所述第一表面上的多个第二电连接件，且所述管芯通过所述第二电连接件结合到且电连接到所述中介件。
根据本公开的一些实施例，一种半导体封装包括中介件、管芯及具有电路结构的衬底。管芯结合到且电连接到中介件，且管芯上具有保护层。中介件结合到且电连接到具有电路结构的衬底，且管芯设置在中介件与具有电路结构的衬底之间且通过中介件电连接到具有电路结构的衬底。
在一些实施例中，所述保护层设置在所述管芯与所述具有电路结构的衬底之间，且所述保护层通过间隙与所述具有电路结构的衬底分离。
在一些实施例中，所述半导体封进一步包括至少一个表面安装器件，其中所述至少一个表面安装器件相对于所述中介件与所述管芯相对设置。
在一些实施例中，所述半导体封装进一步包括包封所述管芯的第一模制材料及相对于所述中介件与所述第一模制材料相对设置的第二模制材料，其中所述第一模制材料的侧壁与所述第二模制材料的侧壁实质上齐平。
在一些实施例中，所述管芯设置在所述具有电路结构的衬底的空腔中，而不与所述具有电路结构的衬底直接接触。
在一些实施例中，所述保护层的侧壁与所述管芯的侧壁实质上齐平。
在一些实施例中，所述管芯通过多个第一电连接件结合到所述中介件，所述中介件通过多个第二电连接件结合到所述具有电路结构的衬底，且所述第二电连接件环绕所述第一电连接件。
根据本公开的一些实施例，一种制造半导体封装的方法包括以下步骤。将管芯结合到中介件上以电连接到中介件，其中管芯上具有保护层，且管芯设置在保护层与中介件之间。在中介件之上形成第一模制材料以包封管芯，其中第一模制材料覆盖保护层。在管芯由保护层保护的同时，对第一模制材料进行薄化。
在一些实施例中，所述第一模制材料的表面与所述保护层的表面实质上共面。
在一些实施例中，所述方法进一步包括在所述第一模制材料中形成多个电连接件以环绕所述管芯。
在一些实施例中，所述方法进一步包括将所述中介件结合到具有电路结构的衬底上，其中所述管芯设置在所述中介件与所述具有电路结构的衬底之间。
在一些实施例中，所述方法进一步包括：将至少一个表面安装器件结合到所述中介件上，其中所述至少一个表面安装器件相对于所述中介件与所述管芯相对设置；以及在所述中介件之上形成第二模制材料以包封所述至少一个表面安装器件。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文所介绍的实施例相同的目的和/或实现与本文所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，此种等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (10)

1.一种半导体封装，包括：
中介件；
管芯，包括第一表面及与所述第一表面相对的第二表面，所述管芯通过所述第一表面结合到所述中介件；
保护层，设置在所述管芯的所述第二表面上；
多个第一电连接件，位于所述管芯旁边；以及
第一模制材料，设置在所述管芯、所述保护层及所述第一电连接件旁边。
2.根据权利要求1所述的半导体封装，其中所述第一模制材料的表面与所述保护层的表面实质上共面。
3.根据权利要求1所述的半导体封装，其中所述保护层从所述第一模制材料突出。
4.根据权利要求1所述的半导体封装，其中所述第一电连接件从所述第一模制材料突出。
5.根据权利要求1所述的半导体封装，其中所述保护层的材料不同于所述第一模制材料的材料。
6.根据权利要求1所述的半导体封装，进一步包括至少一个表面安装器件，其中所述至少一个表面安装器件相对于所述中介件与所述管芯相对设置。
7.一种半导体封装，包括：
中介件；
管芯，结合到且电连接到所述中介件，所述管芯上具有保护层；以及
具有电路结构的衬底，其中所述中介件结合到且电连接到所述具有电路结构的衬底，且所述管芯设置在所述中介件与所述具有电路结构的衬底之间且通过所述中介件电连接到所述具有电路结构的衬底。
8.根据权利要求7所述的半导体封装，其中所述保护层设置在所述管芯与所述具有电路结构的衬底之间，且所述保护层通过间隙与所述具有电路结构的衬底分离。
9.一种制造半导体封装的方法，包括：
将管芯结合到中介件上以电连接到所述中介件，其中所述管芯上具有保护层，且所述管芯设置在所述保护层与所述中介件之间；
在所述中介件之上形成第一模制材料以包封所述管芯，其中所述第一模制材料覆盖所述保护层；以及
在所述管芯由所述保护层保护的同时，对所述第一模制材料进行薄化。
10.根据权利要求9所述的方法，其中所述第一模制材料的表面与所述保护层的表面实质上共面。
CN202110037312.XA 2020-10-21 2021-01-12 半导体封装及制造半导体封装的方法 Pending CN113838840A (zh)

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