CN112310049A - 集成电路封装 - Google Patents

集成电路封装 Download PDF

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Publication number
CN112310049A
CN112310049A CN201911022496.1A CN201911022496A CN112310049A CN 112310049 A CN112310049 A CN 112310049A CN 201911022496 A CN201911022496 A CN 201911022496A CN 112310049 A CN112310049 A CN 112310049A
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China
Prior art keywords
die
integrated circuit
redistribution
package
redistribution structure
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Pending
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CN201911022496.1A
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English (en)
Inventor
余振华
余国宠
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112310049A publication Critical patent/CN112310049A/zh
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Abstract

本发明实施例提供集成电路封装及其形成方法。一种集成电路封装包括多个集成电路、第一包封体、第一重布线结构、多个导电柱、第二重布线结构、第二包封体以及第三重布线结构。第一包封体包封集成电路。第一重布线结构设置在第一包封体之上且电连接到集成电路。导电柱设置在第一重布线结构之上。导电柱设置在第一重布线结构与第二重布线结构之间且电连接到第一重布线结构及第二重布线结构。第二包封体包封导电柱且设置在第一重布线结构与第二重布线结构之间。第三重布线结构设置在第二重布线结构之上且电连接到第二重布线结构，其中第三重布线结构的线宽度大于第二重布线结构的线宽度。

Description

集成电路封装
技术领域
本发明实施例涉及一种集成电路封装。
背景技术
近年来，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等) 的集成密度持续提高，半导体行业已经历快速成长。集成密度的这种提高在极 大程度上源自最小特征大小(minimum feature size)的连续减小，这使得更多 组件能够集成到给定区域中。
这些较小的电子组件也需要与先前的封装相比占据较小面积的较小的封 装。半导体的封装的类型的实例包括四方扁平封装(quad flat pack，QFP)、引 脚栅阵列(pingrid array，PGA)、球栅阵列(ball grid array，BGA)、倒装芯片 (flip chip，FC)、三维集成电路(three-dimensional integrated circuit，3DIC)封 装、晶片级封装(wafer levelpackage，WLP)以及叠层封装(package on package， PoP)装置。一些3DIC是通过将芯片放置在半导体晶片级上的芯片之上制备而 成。3DIC提供提高的集成密度及其他优点，例如更快的速度及更高的带宽，这 是因为堆叠的芯片之间的内连线的长度减小。然而，存在许多关于3DIC的挑 战。
发明内容
本发明实施例的一种集成电路封装包括多个集成电路、第一包封体、第一 重布线结构、多个导电柱、第二重布线结构、第二包封体以及第三重布线结构。 所述第一包封体包封所述集成电路。所述第一重布线结构设置在所述第一包封 体之上且电连接到所述集成电路。所述导电柱位于所述第一重布线结构之上。 所述第二包封体包封所述导电柱且设置在所述第一重布线结构与所述第二重布 线结构之间。所述第三重布线结构设置在所述第二重布线结构之上且电连接到 所述第二重布线结构，其中所述第三重布线结构的线宽度大于所述第二重布线 结构的线宽度。
附图说明
图1A到图1F是根据一些实施例的形成集成电路封装的方法的剖视图。
图2A到图2I是根据一些实施例的集成电路封装的剖视图。
图3是图2D到图2F的集成电路封装的俯视图。
图4是图2G到图2I的集成电路封装的俯视图。
图5是根据一些实施例的集成电路封装的俯视图。
图6是根据一些实施例的集成电路封装的剖视图。
图7是根据一些实施例的集成电路封装的剖视图。
图8A到图8D是根据一些实施例的形成集成电路封装的方法的剖视图。
图9是根据一些实施例的集成电路封装的剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或 实例。以下出于以简化的方式传达本发明的目的来阐述组件及布置的具体实例。 当然，这些仅为实例而非旨在进行限制。举例来说，在以下说明中，在第一特 征之上或第一特征上形成第二特征可包括其中第二特征与第一特征被形成为直 接接触的实施例，且也可包括其中第二特征与第一特征之间可形成附加特征从 而使得第二特征与第一特征可不直接接触的实施例。另外，在本发明的各种实 例中，相同的参考编号和/或字母可用于指代相同或相似的部件。这种对参考编 号的重复使用是出于简洁及清晰的目的，而不是自身指示所论述的各种实施例 和/或配置之间的关系。
此外，本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、 “下部的(lower)”、“在…上(on)”、“在…之上(over)”、“上覆在…上(overlying)”、 “在…上方(above)”、“上部的(upper)”等空间相对性用语来促进对如图中所 示的一个元件或特征与另一(其他)元件或特征的关系的说明。所述空间相对 性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设 备可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对 性描述语可同样相应地进行解释。
图1A到图1F是根据一些实施例的形成集成电路封装的方法的剖视图。
参照图1A，将封装结构100提供到载体衬底C上。在一些实施例中，将 封装结构100放置到载体衬底C上。载体衬底C可为玻璃载体。在一些实施例 中，在载体衬底C与封装结构100之间形成离形层(de-bonding layer)DB。离 形层DB例如是光热转换(light-to heat-conversion，LTHC)释放层。载体衬底 C的材料及离形层DB的材料在本发明中不受限制。
在一些实施例中，封装结构100包括多个集成电路110、120、包封体130、 重布线层结构140、衬底层150及多个导电柱160。在一些实施例中，集成电路 110设置在集成电路120之间，且集成电路110被集成电路120环绕。在一些 实施例中，集成电路110中的每一者包括逻辑管芯，例如应用处理器(application processor，AP)管芯、中央处理器(centralprocessing unit，CPU)管芯、通用 处理器(general processing unit，GPU)管芯、现场可编程门阵列(field programmable gate array，FPGA)管芯、应用专用集成电路(application-specific integrated circuit，ASIC)管芯、输入/输出(I/O)管芯、网络处理器(network processing unit，NPU)管芯、张量处理器(tensor processing unit，TPU)管芯、 人工智能(artificial intelligence，AI)引擎管芯及系统集成芯片(system onintegrated chips，SoIC)管芯。在一些实施例中，集成电路120中的每一者包括 存储器管芯，例如高带宽存储器(high bandwidth memory，HBM)管芯、静态 随机存取存储器(staticrandom access memory，SRAM)管芯、动态随机存取 存储器(dynamic random accessmemory，DRAM)管芯、宽I/O存储器管芯、 NAND型存储器(NAND memory)管芯、电阻式随机存取存储器(resistive random access memory，RRAM)管芯、相变随机存取存储器(phasechange random access memory，PRAM)管芯及磁性随机存取存储器(magnetic randomaccess memory，MRAM)管芯、系统芯片(system-on-chip，SoC)管芯、SoIC管芯、 管芯堆叠等。在一些实施例中，根据工艺要求，集成电路120的尺寸相似于或 不同于集成电路110的尺寸。所述尺寸可为高度、宽度、大小、俯视面积或其 组合。在一些实施例中，示出三个集成电路以代表多个集成电路，且本发明并 不仅限于此。举例来说，可存在两个集成电路或三个以上集成电路。
在一些实施例中，集成电路110不同于集成电路120。在一些实施例中， 集成电路110是逻辑管芯，且集成电路120分别是存储器管芯堆叠或三维(3D) 存储器立方体。在一些实施例中，集成电路120具有多个管芯122。管芯122 垂直地堆叠且通过例如管芯122的微凸块122a和/或穿孔122b连接。在一些实 施例中，集成电路110及集成电路120通过倒装芯片结合、混合结合、扇出型 重布线层(redistribution layer，RDL)和/或类似技术通过连接件112、124连接 到重布线层结构140。在一些实施例中，集成电路110、120中的每一者在其上 面具有多个连接件112、124且在连接件112、124旁边具有介电层114、126。 在一些实施例中，连接件112、124是铜柱或其他合适的金属柱。在一些实施例 中，介电层114、126是聚苯并恶唑(polybenzoxazole，PBO)层、聚酰亚胺 (polyimide，PI)层或其他合适的底部填充环氧聚合物。在一些替代实施例中， 介电层114、126由无机材料制成。在一些替代实施例中，集成电路120还包括 控制器。然而，集成电路110、120的结构仅用于例示，且本发明并不仅限于此。 举例来说，在一些替代实施例中，连接件112、124在上面具有焊料层(未示出)，或者省略介电层114、126。
在一些实施例中，包封体130包封集成电路110、120。包封体130形成在 集成电路110、120周围。具体来说，包封体130填充集成电路110、120中的 任何两个集成电路之间的间隙。在一些实施例中，包封体130包括模制化合物、 树脂等。在一些实施例中，包封体130包含聚合物材料，例如聚苯并恶唑(PBO)、 聚酰亚胺、苯并环丁烯(benzocyclobutene，BCB)、其组合等。在替代实施例 中，包封体130包含氧化硅、氮化硅或其组合。
在一些实施例中，将重布线层结构140连接到集成电路110的表面及集成 电路120的表面。重布线层结构140包括介电层142及嵌入介电层142的导电 特征144。导电特征144电连接到集成电路110、120的连接件112、124。在一 些实施例中，介电层142包含感光性材料(例如聚苯并恶唑(PBO)、聚酰亚胺 (PI)、苯并环丁烯(BCB))、氧化硅、其他无机电介质、其组合等。在一些实 施例中，介电层142包含其他介电材料。在一些实施例中，导电特征144包括 被配置成电连接到不同组件的金属线144a和/或金属通孔144b。在一些实施例 中，导电特征144包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施 例中，在每一导电特征144与介电层142之间设置晶种层和/或阻挡层。晶种层 可包含Ti/Cu。阻挡层可包含Ta、TaN、Ti、TiN、CoW、或其组合。在一些替 代实施例中，导电特征144经配置以形成重布线层结构，例如串行器/解串行器 (SerDes)重布线层结构。
在一些实施例中，在重布线层结构140之上形成衬底层150。在一些实施 例中，衬底层150包括半导体层(例如硅层)。在一些实施例中，衬底层150 的横向侧壁实质上与包封体130的横向侧壁及重布线层结构140的横向侧壁齐 平。衬底层150的厚度可介于从50μm到100μm的范围内。在一些替代实施 例中，可省略衬底层150。
然后，在衬底层150中及衬底层150上形成导电柱160以电连接重布线层 结构140。在一些实施例中，导电柱160是铜柱。在一些实施例中，在衬底层 150中形成暴露出导电特征144的多个开口，且然后分别在开口中及衬底层150 上形成导电柱160。导电柱160可通过沉积工艺、溅镀工艺、电镀工艺等以及 接续的图案化工艺形成。在一些实施例中，导电柱160的顶表面的形状是圆形、 正方形、矩形、椭圆形等。在一些实施例中，导电柱160穿透衬底层150且从 衬底层150突出。具体来说，导电柱160具有第一部分160a及连接到第一部分160a的第二部分160b，第一部分160a(例如，上部部分)设置在衬底层150 上，且第二部分160b(例如，下部部分)嵌入衬底层150中。在一些实施例中， 第一部分160a的宽度大于第二部分160b。在一些实施例中，导电柱160的第 一部分160a的特性宽度介于从约20μm到约50μm的范围内，且导电柱160 的第二部分160b的宽度介于从约5μm到约15μm的范围内。导电柱160的第 一部分160a的高度可介于从30μm到约300μm的范围内。第二部分160b的厚 度实质上等于衬底层150的厚度。在一些实施例中，在导电柱160的第一部分 160a之间形成间隙G。在一些实施例中，间隙G的宽度实质上相同，换句话说， 导电柱160被规则地布置。然而，本发明并不仅限于此。在一些替代实施例中， 导电柱160被不规则地布置。在一些实施例中，根据设计需要而定，间隙G的 宽度介于从50μm到8000μm的大范围内。
参照图1B，在封装结构100之上形成多个管芯170。在一些实施例中，在 将封装结构100设置在载体衬底C上之后，可将管芯170拾取并放置到衬底层 150上。在一些实施例中，在衬底层150上在导电柱160之间的间隙G中设置 管芯170。在一些实施例中，管芯170是集成无源装置(integrated passive device， IPD)管芯、集成电压调节器(integratedvoltage regulator，IVR)管芯、存储器 管芯、SerDes物理层(physical layer，PHY)管芯等。在一些实施例中，根据 设计需要而定，管芯170包括具有一种功能或多种不同功能的管芯、具有前述 相同大小或不同大小的管芯。在一些实施例中，管芯170包括设置在其上面且远离衬底层150延伸的连接件172。在一些替代实施例中，管芯170通过粘着 层(adhesivelayer)(未示出)(例如，管芯贴合膜(die attach film，DAF))安 装到衬底层150上。在一些替代实施例中，管芯170通过金属结合(未示出) (例如，倒装芯片结合)安装到衬底层150上。在此种实施例中，管芯170的 连接件172可朝向衬底层150延伸且通过导电柱160电连接到重布线层结构 140。在一些实施例中，管芯170与其上面的连接件172的总高度介于30μm到 300μm的范围内，且管芯170的宽度介于500μm到7500μm的范围内。在一 些实施例中，管芯170的连接件172的顶表面实质上与导电柱160的顶表面共 面。然而，在一些替代实施例中，管芯170的连接件172的顶表面低于或高于 导电柱160的顶表面。
参照图1C及图1D，在载体衬底C之上形成包封体180以包封封装结构100 及管芯170。在一些实施例中，如图1C中所示，在载体衬底C之上形成绝缘材 料180’以覆盖封装结构100及管芯170。在一些实施例中，绝缘材料180’包括 模制化合物，例如通过模制工艺形成的环氧模制化合物。在一些替代实施例中， 绝缘材料180’包括环氧树脂、树脂等。
然后，如图1D中所示，对绝缘材料180’进行研磨直到暴露出导电柱160 及管芯170的连接件172为止，以便形成包封体180。在一些实施例中，通过 平坦化工艺(例如，化学机械抛光工艺)对绝缘材料180’进行研磨。在一些实 施例中，在研磨之后，导电柱160的顶表面及连接件172的顶表面实质上与包 封体180的顶表面共面。在一些实施例中，包封体180包封包封体130的横向 侧壁、重布线层结构140的横向侧壁、衬底层150的横向侧壁、导电柱160的 横向侧壁、管芯170的横向侧壁及连接件172的横向侧壁。包封体180暴露出 导电柱160的顶表面及管芯170的连接件172的顶表面。换句话说，导电柱160 及管芯170嵌入具有被暴露的顶表面的包封体180中。在一些实施例中，导电 柱160及管芯170被包封体180包封且接触包封体180。导电柱160及连接件 172可设置在包封体180中且穿透包封体180。在一些替代实施例中，包封体 180通过层叠工艺(lamination process)形成。
参照图1E，在形成包封体180之后，在包封体180之上形成重布线层结构 190，且将重布线层结构190电连接到导电柱160及管芯170。在一些实施例中， 重布线层结构190包括多个介电层192及嵌入介电层192中的多个导电特征 194。应注意，出于例示的目的，示出导电特征194的层的数目，且本发明的范 围并不仅限于此。在一些实施例中，介电层192是多层式结构。在一些实施例 中，介电层192包含感光性材料，例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、 苯并环丁烯(BCB)、其组合等。在一些实施例中，介电层192包含其他介电材 料。在一些实施例中，导电特征194包括被配置成电连接到不同组件的金属线 194a和/或金属通孔194b。在一些实施例中，导电特征194包含Cu、Ti、Ta、 W、Ru、Co、Ni、其组合等。在一些实施例中，在每一导电特征194与介电层 192之间设置晶种层和/或阻挡层。晶种层可包含Ti/Cu。阻挡层可包含Ta、TaN、 Ti、TiN、CoW、或其组合。
在一些实施例中，介电层192的厚度介于10μm到30μm的范围内。在一 些实施例中，导电特征194的线宽度介于从2μm到10μm的范围内。在一些 替代实施例中，随着导电特征194变得更靠近重布线层结构200(如图1F中所 示)，导电特征194的线宽度增加。在一些替代实施例中，导电特征194的线宽 度实质上相同于或大于下伏导电特征194的线宽度。在一些实施例中，线宽度 被称为临界尺寸或节距。
参照图1F，在重布线层结构190之上形成重布线层结构200，且将重布线 层结构200电连接到导电柱160及管芯170。在一些实施例中，重布线层结构 200包括多个介电层202及嵌入介电层202中的多个导电特征204。在一些实施 例中，导电特征204包括被配置成电连接到不同组件的金属线204a和/或金属 通孔204b。应注意，出于例示的目的，示出导电特征204的层的数目，且本发 明的范围并不仅限于此。
在一些实施例中，重布线层结构200的主要功能是提供到导电端子的电连 接以及提供集成电路封装10的结构刚性。因此，用于制作重布线层结构200 的机器、方法及材料可与用于制作重布线层结构190的机器、方法及材料不同。 在一些实施例中，通过层叠工艺和/或涂布工艺在重布线层结构190上形成光刻 胶层。在图像图案化之后，通过电镀工艺形成金属线204a及金属通孔204b。 然后，通过干式蚀刻工艺和/或湿式蚀刻工艺移除光刻胶层以及移除不期望的晶 种层。为增强结构刚性，通过包封工艺施加经强化的包封体材料来包封金属线 及金属通孔。在一些实施例中，经强化的包封体材料是具有精细颗粒状的无机填料(0.5μm到2μm)且体积分数(volume fraction)为30％到80％的环氧系 聚合物。在一些实施例中，包封工艺包括晶片模制工艺、晶片分配(wafer dispensing)工艺、晶片层叠工艺等。在包封之后，应用平坦化工艺以移除多余 的包封体从而暴露出金属线。重复相同的步骤来形成重布线层结构200的多个 层。在一些实施例中，在重布线层结构190上形成厚的介电层，然后通过激光 直接成像(laser direct imaging，LDI)工艺一次形成金属通孔及金属线。在一 些实施例中，厚的介电层包含味之素构成膜(Ajinomoto Buildup Film，ABF)、聚酰亚胺等。对于金属层形成，首先通过无电镀覆工艺形成共形晶种层，然后 通过电镀形成金属通孔及金属线。最后，需要金属平坦化来移除金属覆盖层 (overburden)。在一些实施例中，金属层包含Cu、Ti、Ta、W、Ru、Co、Ni、 其组合等。在一些实施例中，金属平坦化包括化学机械抛光(chemical mechanical polish，CMP)方法、轮研磨(wheel grinding)方法、金刚石刀片快速切割(diamond blade fly cut)方法等。以此种方式，形成类似双镶嵌的重布线层。重复相同的 步骤以形成重布线层结构200的多个层。
在一些实施例中，导电特征204的线宽度大于导电特征194的线宽度。在 一些实施例中，导电特征204的线宽度为导电特征194的线宽度的至少1.5倍、 2倍、3倍、4倍、5倍、6倍、7倍、8倍、9倍或10倍。在一些实施例中，导 电特征204的线宽度介于20μm到50μm的范围内。在一些替代实施例中，随 着导电特征204变得更靠近导电端子210，导电特征204的线宽度增加。在一 些替代实施例中，导电特征204的线宽度实质上相同于或大于下伏导电特征204 的线宽度。举例来说，导电特征204的线宽度实质上相同于或大于下面的金属 通孔204b的线宽度。在一些实施例中，介电层202的厚度大于介电层192的厚 度。介电层202的厚度可介于50μm到150μm的范围内。在一些实施例中， 重布线层结构200为支撑提供高模量，例如介于1GPa到10GPa的范围内。
在一些实施例中，重布线层结构200通过例如通常用于制造印刷电路板(PrintedCircuit Board，PCB)的LDI等工艺形成，且因此重布线层结构200 具有良好的刚性。另外，制造重布线层结构200的成本及时间得以减少。此外， 与具有核心层的印刷电路板相比，重布线层结构200直接形成在封装结构100 及包封体180之上且集成到封装结构100及包封体180上，且因此不需要相似 于核心层的支撑衬底。因此，集成电路封装10的总厚度小于具有结合到印刷电 路板的封装结构的集成电路封装。此外，不需要例如封装结构与印刷电路板之 间的受控塌陷芯片连接(controlled collapse chip connection，C4)凸块等连接件。
在形成重布线层结构200之后，在重布线层结构200上形成多个导电端子 210。在一些实施例中，导电端子210是球栅阵列(ball grid array，BGA)连接 件、焊料球、金属柱和/或类似元件。在一些实施例中，导电端子210通过安装 工艺及回焊工艺形成。在一些实施例中，在导电端子210之下形成多个球下金 属(under-ball metallurgy，UBM)图案208以进行球安装。
在一些实施例中，在导电端子210之间在重布线层结构200上安装多个管 芯220。此时，完成集成电路封装10的制作。在一些实施例中，管芯220是IPD 管芯、IVR管芯、存储器管芯等。在一些实施例中，管芯220包括其上面的连 接件222。在一些实施例中，管芯220通过连接件222及焊料224安装到重布 线层结构200上。在一些实施例中，在管芯220与重布线层结构200之间提供 底部填充胶226以密封管芯220与重布线层结构200之间的区。然而，在一些 替代实施例中，管芯220是裸(未经封装的)管芯。
在一些实施例中，将集成电路封装10与载体衬底C分离。也就是说，移 除载体衬底C。在一些实施例中，以紫外(UV)激光辐照离形层DB，以从载 体衬底C剥离集成电路封装10。在一些替代实施例中，在形成导电端子210及 管芯220之后，执行单体化工艺以形成单个集成电路封装。在一些实施例中， 在高性能计算系统(high-performance computingsystem)中提供集成电路封装 10以提供高数据传输速率。在一些实施例中，集成电路封装10的尺寸大于40 mm×40mm。在一些实施例中，集成电路封装10是集成扇出型封装。
在一些实施例中，封装结构100通过导电柱160及导电柱160与导电端子 210之间的重布线层结构190、200连接到导电端子210。由于导电柱160及重 布线层结构190、200直接形成在封装结构100之上，因此不需要将封装结构 100结合到附加电路板以及在附加电路板与封装结构之间形成附加凸块(例如， C4凸块)。另外，管芯170(例如，IPD管芯、存储器管芯、SerDes管芯和/或 IVR管芯)设置在导电柱160之间且嵌入包封体180中，且因此集成电路封装 10的集成度得以提高。此外，在一些实施例中，对逻辑管芯与存储器管芯(例 如，3D存储器立方体)进行集成，以实现具有高计算效率、高带宽及低延迟的 近存储器内计算(in-memory computing，IMC)技术。
图2A到图2I是根据一些实施例的集成电路封装的剖视图。图3是图2D 到图2F的集成电路封装的俯视图。图4是图2G到图2I的集成电路封装的俯 视图。图5是根据一些实施例的集成电路封装的俯视图。图2A到图2I中所示 的半导体封装10A到半导体封装10I相似于图1F中所示的半导体封装10，因 此相同的参考编号用于指代相同及类似的部件，且本文中将省略其详细说明。 半导体封装10A到半导体封装10I与半导体封装10之间的不同之处在于集成电 路110的结构。在图2A到图2I中所示的实施例中，集成电路110是系统集成 芯片(SoIC)管芯。
详细来说，在图2A到图2C中所示的实施例中，集成电路110包括第一管 芯116a、多个第二管芯116b、多个导电柱116c及包封体116d。在一些实施例 中，第二管芯116b依序堆叠在第一管芯116a上以形成管芯堆叠。在一些实施 例中，第二管芯116b垂直地堆叠在第一管芯116a上且通过第二管芯116b的微 凸块(未示出)和/或穿孔(未示出)彼此连接。在一些实施例中，第一管芯116a 是逻辑管芯(例如，SoC管芯)，且第二管芯116b是存储器管芯(例如，SRAM 管芯)。在一些实施例中，第二管芯116b的管芯堆叠与集成电路120的管芯堆 叠不同，换句话说，封装结构100包括至少两个不同的存储器立方体。在一些 实施例中，导电柱116c设置在第一管芯116a上位于第二管芯116b旁边。包封 体116d形成在第一管芯116a上以包封第二管芯116b及导电柱116c。在一些实 施例中，导电柱116c设置在包封体116d中且穿透包封体116d。导电柱116c 是用于热扩散的导热柱、用于I/O通信的垂直内连件等。
在图2B及图2C中所示的实施例中，集成电路110还包括第三管芯116e。 在一些实施例中，第三管芯116e是逻辑管芯(例如，SoC管芯)。在一些实施 例中，第三管芯116e是存储器控制器逻辑、I/O逻辑、数字信号处理(digital signal processing，DSP)、IPD管芯及逻辑核心等。在一些实施例中，第三管芯116e 本身是由多个逻辑核心及I/O管芯等形成的堆叠管芯。在一些实施例中，第三 管芯116e本身是由多个堆叠的逻辑核心及I/O管芯等形成的SoIC管芯。在一 些实施例中，第三管芯116e具有与管芯116b相同的大小。在一些实施例中， 第三管芯116e具有与管芯116b不同的大小。详细来说，在图2B中所示的实施 例中，第三管芯116e设置在第一管芯116a与第二管芯116b之间，也就是说， 第三管芯116e相邻于第一管芯116a设置。然而，本发明并不仅限于此。在图 2C中所示的实施例中，第三管芯116e在第一管芯116a之上设置在第二管芯 116b上，换句话说，第三管芯116e与第一管芯116a设置于第二管芯116b的相 对两侧。
在图2D到图2I中所示的实施例中，集成电路110包括第一管芯116a、多 个第二管芯116b、附加管芯116f及包封体116d。附加管芯116f可为IPD管芯、 IVR管芯等。附加管芯116f可为安装在第一管芯116a的外围表面上的裸(未 经封装的)管芯。在一些实施例中，附加管芯116f通过面对面直接结合而结合 到第一管芯116a。在一些替代实施例中，在附加管芯116f与第一管芯116a之 间提供底部填充胶(未示出)以密封附加管芯116f与第一管芯116a之间的区。 在图2D到图2F及图3中所示的实施例中，附加管芯116f设置在第一管芯116a 上位于第二管芯116b旁边。包封体116d形成在第一管芯116a上以包封第二管 芯116b及附加管芯116f。在一些实施例中，如图2G到图2I及图4中所示，附 加管芯116f设置在第一管芯116a旁边且与第一管芯116-a隔开。在一些实施例 中，附加管芯116f透过管芯贴合膜以面朝上的方式配置，且使用垂直连接件(未 示出)连接到重布线层结构140。包封体116d被形成为包封第一管芯116a、第 二管芯116b及附加管芯116f。另外，在图2E、图2F、图2H及图2I中所示的 实施例中，第三管芯116e设置在第一管芯116a与第二管芯116b之间或者设置 在第一管芯116a之上位于第二管芯116b上。
在以上实施例中，示出一个集成电路110。然而，本发明并不仅限于此。 举例来说，在图5中所示的实施例中，多个集成电路110设置在集成电路120 之间。另外，集成电路110中的每一者可包括第一管芯116a、多个第二管芯116b 及多个附加管芯116f，且第二管芯116b及附加管芯116f设置在第一管芯116a 上。集成电路120可分别包括多个管芯122(即，管芯堆叠)。因此，如图5中 所示，第一管芯116a被管芯122(即，管芯堆叠)环绕，且第二管芯116b被 附加管芯116e环绕。在所述实施例中，第一管芯116a是逻辑管芯，管芯116b、 122是存储器管芯，且附加管芯116f是IPD管芯和/或IVR管芯。因此，逻辑 管芯可被存储器管芯环绕，且IPD管芯和/或IVR管芯可设置在存储器管芯之 间。
图6是根据一些实施例的集成电路封装的剖视图。图6中示出的半导体封 装10J相似于图1F中示出的半导体封装10，因此相同的参考编号用于指代相 同及类似的部件，且本文中将省略其详细说明。半导体封装10J与半导体封装 10之间的不同之处在于衬底层150。举例来说，在图1F中所示的实施例中，半 导体封装10包括衬底层150。然而，在图6中所示的实施例中，半导体封装10J 的导电柱160直接形成在重布线层结构140上，而在导电柱160与重布线层结 构140之间不存在衬底层150。在一些实施例中，集成电路110及集成电路120通过倒装芯片结合、混合结合、扇出型RDL和/或类似技术通过连接件112、124 连接到重布线层结构140。详细来说，如图6中所示，导电柱160具有与底部 宽度实质上相同的顶部宽度。在所述实施例中，导电柱160的横向侧壁完全被 包封体180包封。在一些实施例中，如果需要的话，重布线层结构190是串行 器/解串行器(SerDes)重布线层结构。另外，在一些替代实施例中，封装结构 100是图1F、图2A到图2I等的封装结构中的任何一者。
图7是根据一些实施例的集成电路封装的剖视图。图7中示出的半导体封 装10K相似于图6中示出的半导体封装10J，因此相同的参考编号用于指代相 同及类似的部件，且本文中将省略其详细说明。半导体封装10K与半导体封装 10J之间的不同之处在于集成电路110的结构。详细来说，在图7中所示的实 施例中，集成电路110包括第一管芯116a及多个第二管芯116b1、116b2。在一 些实施例中，第二管芯116b1、116b2结合在第一管芯116a的相对的表面上， 且通过管芯116a中的硅穿孔(through silicon via，TSV)(未示出)电连接到第一管芯116a。在一些实施例中，第二管芯116b1、116b2通过多个连接件117 及连接件117旁边的介电层118结合到第一管芯116a。第一管芯116a的尺寸可 大于第二管芯116b1、116b2中的每一者的尺寸。在一些实施例中，第一管芯 116a是逻辑管芯，且第二管芯116b1、116b2是存储器管芯。在一些实施例中， 管芯电路110本身是如图2A到图2I中所阐述的SoIC管芯。在一些实施例中， 第一管芯116a本身是如图2A到图2I中所阐述的SoIC管芯。另外，集成电路 120可为存储器管芯堆叠，且包括多个管芯122。因此，第二管芯116b1、116b2 在第一方向上设置在第一管芯116a的相对的表面处，且管芯122在实质上与第 一方向垂直的第二方向上设置在第一管芯116a的相对的横向侧壁处。因此，管 芯116a(例如，计算逻辑管芯)被浸入(immersed)管芯116b1、116b2、122 (例如，存储器管芯)中。在以上实施例中，示出一个集成电路110。然而， 本发明并不仅限于此。在一些实施例中，存在多个集成电路110，如图5中所 示。
在一些实施例中，集成电路110还包括多个导电柱116c1、116c2及多个包 封体116d1、116d2。在一些实施例中，第二管芯116b1旁边的导电柱116c1是 用于热扩散的导热柱，且第二管芯116b2旁边的导电柱116c2是用于电连接的 穿孔。在一些实施例中，导电柱116c1被设置于第一管芯116a上且导电柱116c1 通过导电柱116c1与第一管芯116a之间的多个导电层116g电连接到第一管芯 116a。在一些实施例中，导电柱116c2电连接到第一管芯116a及重布线层结构 140。包封体116d1包封第一管芯116a、第二管芯116b1及导电柱116c1。包封 体116d2包封第二管芯116b2及导电柱116c2。
图8A到图8D是根据一些实施例的形成集成电路封装的方法的剖视图。
参照图8A，提供封装结构100。封装结构100可为图1F、图2A到图2I 及图7等的封装结构100中的任何一者。然后，提供上面具有重布线层结构190、 200的载体衬底C。在一些实施例中，在载体衬底C之上形成离形层DB。然后， 在离形层DB之上依序形成重布线层结构200及重布线层结构190。重布线层 结构190、200的配置、材料及形成方法相似于图1E及1F中的重布线层结构 190、200的配置、材料及形成方法。在一些实施例中，如果需要的话，重布线 层结构190是串行器/解串行器(SerDes)重布线层结构。
在一些实施例中，在形成重布线层结构190、200之后，将多个管芯170 结合到重布线层结构190上。管芯170对应于相邻的导电柱160之间的间隙G 设置，且因此在载体衬底C之上将封装结构100结合到重布线层结构190之后， 可将管芯170设置在相邻的导电柱160之间。在一些实施例中，管芯170通过 管芯170的连接件172及连接件172上的焊料174安装到重布线层结构190上。 在一些实施例中，在管芯170与重布线层结构190之间提供底部填充胶176， 以密封管芯170与重布线层结构190之间的区。然而，在一些替代实施例中， 管芯170是裸(未经封装的)管芯。
参照图8B，在载体衬底C之上将封装结构100结合到重布线层结构190。 在一些实施例中，封装结构100通过导电柱160而倒装芯片结合到重布线层结 构190。在一些实施例中，在导电柱160与重布线层结构190的导电特征194 之间形成焊料区230。在一些实施例中，如图8A中所示，焊料区230形成在导 电柱160上。然而，在一些替代实施例中，焊料区230形成在重布线层结构190 上。在结合之后，可在封装结构100与重布线层结构190之间形成底部填充胶 232(也被称为包封体)以密封封装结构100与重布线层结构190之间的区。在一些实施例中，管芯170在导电柱160之间嵌入底部填充胶232中。在一些实 施例中，管芯170与重布线层结构190在实体上隔开。在一些实施例中，底部 填充胶232设置在管芯170与重布线层结构190之间。
参照图8C，在封装结构100之上形成散热件240。在一些实施例中，散热 件240是盖体(cover)。在一些实施例中，散热件240设置在重布线层结构190 的被底部填充胶232暴露的一部分上以完全覆盖封装结构100。在一些实施例 中，散热件240接触重布线层结构190的所述部分。在一些实施例中，散热件 240直接接触封装结构100的暴露的表面，例如集成电路110、120的表面及包 封体130的表面。在一些替代实施例中，散热件240与封装结构100在实体上 隔开且不接触封装结构100。
参照图8D，将图8C的结构与载体衬底C隔开。也就是说，移除载体衬底 C及离形层DB。然后，可将所述结构翻转，且可在重布线层结构200之上形成 多个导电端子210及多个管芯220以便电连接重布线层结构200。在一些实施 例中，管芯220是IPD管芯、IVR管芯、存储器管芯等。在一些实施例中，在 导电端子210之下形成多个球下金属(UBM)图案208以进行球安装。此时， 制作集成电路封装10L。在一些实施例中，管芯电路110本身是如图2A到图2I中所阐述的SoIC管芯。
在一些实施例中，封装结构100通过导电柱160结合到重布线层结构190、 200。因此，管芯170可设置在导电柱160之间形成的空间中。因此，不需要附 加空间。另外，由于载体衬底C直接用作用于形成重布线层结构190、200的 基础层，因此可省略相似于核心层的支撑衬底。另外，由于载体衬底C将接着 被移除，因此集成电路封装10L的总厚度小于具有结合到印刷电路板的封装结 构的集成电路封装。
图9是根据一些实施例的集成电路封装的剖视图。图9中示出的半导体封 装10M相似于图8D中示出的半导体封装10L，因此相同的参考编号用于指代 相同及类似的部件，且本文中将省略其详细说明。半导体封装10L与半导体封 装10M之间的不同之处在于集成电路110的结构及散热件240的移除。在图9 中所示的实施例中，集成电路110具有相似于图7中所示的集成电路110的结 构。在一些实施例中，集成电路110本身是如图2A到图2I中所阐述的SoIC 管芯。在一些实施例中，第一管芯116a本身是如图2A到图2I中所阐述的SoIC 管芯。在一些实施例中，封装结构100可包括夹置在管芯170与集成电路110 之间的衬底层150，如图1A到图2I中所示。在一些实施例中，封装结构100 及管芯170通过倒装芯片结合而结合到重布线层结构190。在一些替代实施例 中，在封装结构100的旁边还设置有散热件(未示出)。
在一些实施例中，通过导电柱及导电柱与导电端子之间的重布线层结构将 封装结构连接到导电端子。在封装结构或後续会被移除的载体衬底之上直接形 成重布线层结构，因此不需要将封装结构结合到附加电路板以及在附加电路板 与封装结构之间形成附加凸块(例如C4凸块)。另外，将用于制造PCB的技术 应用于制作具有大的线宽度的重布线层结构中。因此，重布线层结构的强度得 以提高，且可减少用于制造重布线层结构的成本及时间。此外，可将管芯(例 如，IPD管芯和/或IVR管芯)设置在导电柱之间且嵌入包封体中，且因此集成 电路封装的集成度得以提高。因此，逻辑管芯及存储器管芯(例如3D存储器立方体)可并排集成，以实现具有高计算效率、高带宽及低延迟的存储器内计 算(IMC)技术。
本发明预期到以上实例的许多变化。应理解，不同的实施例可具有不同的 优点，且不一定要求所有实施例都具有特定的优点。
根据本发明的一些实施例，一种集成电路封装包括多个集成电路、第一包 封体、第一重布线结构、多个导电柱、第二重布线结构、第二包封体以及第三 重布线结构。所述第一包封体包封所述集成电路。所述第一重布线结构设置在 所述第一包封体之上且电连接到所述集成电路。所述导电柱位于所述第一重布 线结构之上。所述第二包封体包封所述导电柱且设置在所述第一重布线结构与 所述第二重布线结构之间。所述第三重布线结构设置在所述第二重布线结构之 上且电连接到所述第二重布线结构，其中所述第三重布线结构的线宽度大于所 述第二重布线结构的线宽度。
根据本发明的一些实施例，所述第二包封体还包封所述第一包封体及所述 第一重布线结构。
根据本发明的一些实施例，所述第二包封体的横向侧壁实质上与所述第二 重布线结构的横向侧壁及所述第三重布线结构的横向侧壁齐平。
根据本发明的一些实施例，所述第二包封体是底部填充胶。
根据本发明的一些实施例，所述集成电路封装还包括位于所述第一重布线 结构与所述第二重布线结构之间的衬底层，其中所述导电柱设置在所述衬底层 上及所述衬底层中。
根据本发明的一些实施例，所述第三重布线结构的所述线宽度为所述第二 重布线结构的所述线宽度的至少2倍。
根据本发明的一些实施例，所述集成电路包括管芯及环绕所述管芯的多个 管芯堆叠。
根据本发明的一些实施例，所述集成电路中的一者包括第一管芯、依序堆 叠在所述第一管芯上的多个第二管芯以及在所述第一管芯上位于所述第二管芯 旁边的多个导热柱。
根据本发明的一些实施例，所述集成电路中的一者包括第一管芯、依序堆 叠在所述第一管芯上的多个第二管芯、以及位于所述多个第二管芯旁边的集成 电压调节器(IVR)管芯及集成无源装置(IPD)管芯中的至少一者。
根据本发明的替代实施例，一种集成电路封装包括封装结构、第二重布线 结构、至少一个第二管芯以及第二包封体。所述封装结构包括多个第一管芯、 包封所述第一管芯的第一包封体、位于所述第一包封体之上的第一重布线结构 以及位于所述第一重布线结构之上的多个导电柱。所述第二重布线结构设置在 所述封装结构之上，且通过所述导电柱电连接到所述封装结构。所述第二管芯 设置在所述导电柱之间且电连接到所述第二重布线结构。所述第二包封体包封 所述导电柱及所述至少一个第二管芯。
根据本发明的一些实施例，所述至少一个第二管芯是集成电压调节器管芯 或集成无源装置管芯。
根据本发明的一些实施例，所述至少一个第二管芯通过多个焊料区结合到 所述第二重布线结构上且与所述第一重布线结构在实体上隔开。
根据本发明的一些实施例，所述至少一个第二管芯粘着到所述第一重布线 结构。
根据本发明的一些实施例，所述集成电路封装还包括位于所述导电柱与所 述第二重布线结构之间的多个焊料区，其中所述封装结构通过所述导电柱及所 述焊料区结合到所述第二重布线结构上。
根据本发明的一些实施例，所述集成电路封装还包括散热件，所述散热件 设置在所述第二重布线结构之上以覆盖所述封装结构。
根据本发明的又一些替代实施例，一种制造集成电路封装的方法包括以下 步骤。提供封装结构，且所述封装结构包括多个第一管芯、包封所述第一管芯 的第一包封体、位于所述第一包封体之上的第一重布线结构以及位于所述第一 重布线结构之上的多个导电柱。在所述导电柱之间形成至少一个第二管芯。形 成第二包封体以包封所述导电柱及所述至少一个第二管芯。在所述第二包封体 之上形成第二重布线结构。形成第三重布线结构，其中所述第三重布线结构的 线宽度大于所述第二重布线结构的线宽度。对所述封装结构与所述第二重布线 结构进行电连接，其中所述第二重布线结构设置在所述封装结构与所述第三重 布线结构之间。
根据本发明的一些实施例，所述形成所述第二重布线结构及所述第三重布 线结构以及对所述封装结构与所述第二重布线结构进行电连接包括：将所述封 装结构提供到载体衬底上；在所述载体衬底之上在所述导电柱上形成所述第二 重布线结构，以对所述封装结构进行电连接；以及在所述第二重布线结构之上 形成所述第三重布线结构。
根据本发明的一些实施例，在形成所述第二重布线结构之前，将所述至少 一个第二管芯在所述导电柱之间放置在所述第一重布线结构之上。
根据本发明的一些实施例，所述形成所述第二重布线结构及所述第三重布 线结构以及对所述封装结构与所述第二重布线结构进行电连接包括：在载体衬 底之上形成所述第三重布线结构；在所述第三重布线结构之上形成所述第二重 布线结构；以及通过所述导电柱将所述封装结构结合到所述第二重布线结构上。
根据本发明的一些实施例，在将所述封装结构结合到所述第二重布线结构 上之前，将所述至少一个第二管芯结合到所述第二重布线结构上。
本发明还可包括其他特征及工艺。举例来说，可包括测试结构以帮助对3D 封装或3DIC装置进行验证测试。所述测试结构可包括例如在重布线层中或在 衬底上形成的测试焊盘，以使得能够对3D封装或3DIC进行测试、对探针和/ 或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。 另外，本文中所公开的结构及方法可结合包括对已知良好管芯(known good die) 进行中间验证的测试方法来使用，以提高良率并减少成本。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解 本发明的各个方面。所属领域中的技术人员应理解，他们可容易地使用本发明 作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的 目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还 应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离 本发明的精神及范围的条件下在本文中作出各种改变、代替及变更。

Claims (1)

1.一种集成电路封装，包括：
多个集成电路；
第一包封体，包封所述集成电路；
第一重布线结构，设置在所述第一包封体之上且电连接到所述集成电路；
多个导电柱，位于所述第一重布线结构之上；
第二重布线结构，其中所述导电柱设置在所述第一重布线结构与所述第二重布线结构之间且电连接到所述第一重布线结构及所述第二重布线结构；
第二包封体，包封所述导电柱且设置在所述第一重布线结构与所述第二重布线结构之间；以及
第三重布线结构，设置在所述第二重布线结构之上且电连接到所述第二重布线结构，其中所述第三重布线结构的线宽度大于所述第二重布线结构的线宽度。
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