US11195823B2 - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
- Publication number
- US11195823B2 US11195823B2 US16/264,711 US201916264711A US11195823B2 US 11195823 B2 US11195823 B2 US 11195823B2 US 201916264711 A US201916264711 A US 201916264711A US 11195823 B2 US11195823 B2 US 11195823B2
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- Prior art keywords
- encapsulant
- semiconductor
- semiconductor package
- electrically connected
- redistribution structure
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 195
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- 230000000149 penetrating effect Effects 0.000 claims description 7
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- 238000000034 method Methods 0.000 description 27
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- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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Definitions
- the present disclosure generally relates to a semiconductor package and a manufacturing method thereof, and particularly, to a three-dimensional semiconductor package and a manufacturing method thereof.
- a PoP package includes a stack of semiconductor packages, and can be regarded as a three-dimensional semiconductor package.
- a middle semiconductor package is interposed between a top semiconductor package and a bottom semiconductor package.
- signals sending between the middle and top semiconductor packages as well as signals sending between the middle and bottom semiconductor packages both have to go through a front-side redistribution layer (RDL) of the middle semiconductor package.
- RDL redistribution layer
- the present disclosure is directed to a PoP semiconductor package with improved reliability.
- the present disclosure is also directed to a manufacturing method of the PoP semiconductor package.
- a semiconductor package includes a semiconductor die, an encapsulant and a through encapsulant via.
- the semiconductor die includes a semiconductor substrate, an interconnection layer and a through semiconductor via (TSV).
- the semiconductor substrate has an active surface and a back surface opposite to the active surface.
- the interconnection layer is disposed over the active surface of the semiconductor substrate.
- the TSV penetrates through the semiconductor substrate from the back surface of the semiconductor substrate to the active surface of the semiconductor substrate.
- the encapsulant laterally encapsulates the semiconductor die.
- the through encapsulant via penetrates through the encapsulant.
- the semiconductor package further includes a front redistribution structure and a back redistribution structure.
- the front redistribution structure is disposed over the interconnection layer and a front surface of the encapsulant.
- the front redistribution is electrically connected with the interconnection layer and the through encapsulant via.
- the back redistribution structure is disposed over the back surface of the semiconductor substrate and a back surface of the encapsulant.
- the back surface of the encapsulant is opposite to the front surface of the encapsulant, and the back redistribution structure is electrically connected with the TSV and the through encapsulant via.
- the semiconductor package further includes front electrical connectors and back electrical connectors.
- the front electrical connectors are disposed over the front redistribution structure, and electrically connected with the front redistribution structure.
- the back electrical connectors are disposed over the back redistribution structure, and electrically connected with the back redistribution structure.
- a back surface of the encapsulant is substantially coplanar with the back surface of the semiconductor substrate.
- a front surface of the encapsulant is substantially coplanar with a front surface of the semiconductor die.
- the active surface of the semiconductor substrate faces toward the front surface of the semiconductor die, and the back surface of the semiconductor substrate faces away from the front surface of the semiconductor die.
- the semiconductor die includes a memory die.
- a semiconductor package stack includes the afore-mentioned semiconductor package, a bottom semiconductor package and a top semiconductor package.
- the bottom semiconductor package is attached to a bottom surface of the semiconductor package, and electrically connected with the interconnection layer and the through encapsulant via.
- the top semiconductor package is attached to a top surface of the semiconductor package, and electrically connected with the TSV and the through encapsulant via.
- the bottom semiconductor package includes a bottom semiconductor die, a bottom encapsulant and a bottom through encapsulant via.
- the bottom encapsulant encapsulates the bottom semiconductor die.
- the bottom through encapsulant via penetrates through the bottom encapsulant, and electrically connected with the through encapsulant via of the semiconductor package.
- a top surface of the bottom semiconductor die is buried in the bottom encapsulant.
- a bottom surface of the bottom semiconductor die is substantially coplanar with a bottom surface of the bottom encapsulant.
- the semiconductor package stack further includes a package substrate, attached to a bottom surface of the bottom semiconductor package.
- a manufacturing method of a semiconductor package includes: providing a semiconductor die, wherein the semiconductor die includes a semiconductor substrate, an interconnection layer and a TSV, the interconnection layer is disposed on an active surface of the semiconductor substrate, the TSV penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate; laterally encapsulating the semiconductor die with an encapsulant; and forming a through encapsulant via penetrating through the encapsulant.
- the manufacturing method of the semiconductor package further includes: attaching the semiconductor die onto a first carrier before forming the encapsulant.
- the back surface of the semiconductor substrate faces toward the first carrier, and the active surface of the semiconductor substrate faces away from the first carrier; and detaching the first carrier after forming the encapsulant and the through encapsulant via.
- the step of forming the through encapsulant via precedes the step of forming the encapsulant.
- the steps of forming the encapsulant, attaching the semiconductor die to the first carrier and forming the through encapsulant via includes: forming the through encapsulant via over a surface of the first carrier; attaching the semiconductor die onto the surface of the first carrier; and laterally encapsulating the semiconductor die and the through encapsulant via with the encapsulant.
- the step of forming the through encapsulant via follows the step of forming the encapsulant.
- the steps of attaching the semiconductor die to the first carrier, forming the encapsulant and forming the through encapsulant via includes: attaching the semiconductor die onto a surface of the first carrier; laterally encapsulating the semiconductor die with the encapsulant; removing a portion of the encapsulant to form a through hole; and filling the through hole with a conductive material, to form the through encapsulant via.
- the manufacturing method of the semiconductor package further includes: forming a front redistribution structure over the interconnection layer and a front surface of the encapsulant, wherein the front redistribution structure is electrically connected with the interconnection layer and the through encapsulant via; and forming front electrical connectors over the front redistribution structure, wherein the front electrical connectors are electrically connected with the front redistribution structure.
- the manufacturing method of the semiconductor package further includes: attaching a second carrier to surfaces of the encapsulant, the semiconductor die and the through encapsulant via that face away from the carrier.
- the manufacturing method of the semiconductor package further includes: forming a back redistribution structure over the back surface of the semiconductor substrate and a back surface of the encapsulant, wherein the back redistribution structure is electrically connected with the TSV and the through encapsulant via; forming back electrical connectors over the back redistribution structure, wherein the back electrical connectors are electrically connected with the back redistribution structure; and detaching the second carrier.
- a manufacturing method of a semiconductor package stack includes: the above mentioned manufacturing method of the semiconductor package; attaching a top semiconductor package to a top surface of the semiconductor package, wherein the top semiconductor package is electrically connected with the TSV and the through encapsulant via; and attaching a bottom semiconductor package to a bottom surface of the semiconductor package, wherein the bottom semiconductor package is electrically connected with the interconnection layer and the through encapsulant via.
- the semiconductor package of the present disclosure includes both of the through encapsulant via and the TSV.
- the through encapsulant via penetrates through the encapsulant that laterally surrounds the semiconductor die in the semiconductor package, whereas the TSV penetrates the semiconductor die from a back side of the semiconductor die to an active side of the semiconductor die.
- communications between the top semiconductor package and the bottom semiconductor package can be realized via the through encapsulant via.
- signals from the back side of the semiconductor die can be transmitted to the active side of the semiconductor die via the TSV without going through the through encapsulant via and the front redistribution structure disposed at the active side of the semiconductor die, and vice versa.
- transmission length of the signals transmitted between the back side of the semiconductor die and the active side of the semiconductor die is shortened.
- requirement on routing density of the front redistribution structure of the semiconductor package can be alleviated, and reliability of the semiconductor package can be improved.
- FIG. 1 is a process flow diagram illustrating a manufacturing method of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 2A through FIG. 2K are cross-sectional views of structures at various stages during the manufacturing method of the semiconductor package according to some embodiments of the present disclosure.
- FIG. 1 is a process flow diagram illustrating a manufacturing method of a semiconductor package according to some embodiments of the present disclosure.
- FIG. 2A through FIG. 2K are cross-sectional views of structures at various stages during the manufacturing method of the semiconductor package according to some embodiments of the present disclosure.
- step S 100 is performed, and a semiconductor die 100 is provided.
- the semiconductor die 100 may be a memory die, such as a dynamic random access memory (DRAM) die.
- the semiconductor die 100 includes a semiconductor substrate 102 and a device layer 104 disposed over the semiconductor substrate 102 .
- the semiconductor substrate 102 may be a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer.
- a semiconductor material of the semiconductor wafer or the SOI wafer may include an elemental semiconductor material, a semiconductor alloy or a semiconductor compound.
- the elemental semiconductor may include Si or Ge.
- the semiconductor alloy may include SiGe, SiGeC or the like, whereas the semiconductor compound may include SiC, a III-V semiconductor or a II-VI semiconductor.
- the semiconductor substrate 102 has an active surface AS and a back surface BS opposite to the active surface AS.
- the device layer 104 is formed over the active surface AS of the semiconductor substrate 102 . Some portions of semiconductor devices 106 may be formed in the device layer 104 , whereas other portions (not shown) of the semiconductor devices 106 may be embedded in the semiconductor substrate 102 .
- the semiconductor devices 106 may include memory devices.
- the semiconductor devices 106 may include transistors, capacitors, the like or combinations thereof.
- An interconnection layer 108 is disposed over the device layer 104 .
- a plurality of interconnection elements 110 are formed in the interconnection layer 108 , and are electrically connected with the underlying semiconductor devices 106 .
- the interconnection elements 110 may include conductive vias, conductive traces or a combination thereof.
- conductive pads 112 may be formed over the interconnection layer 108 .
- the conductive pads 112 are electrically connected with the interconnection elements 110 .
- at least one passivation layer 116 is formed over the conductive pads 112 , and has openings at least partially exposing front surfaces of the conductive pads 112 (i.e., top surfaces of the conductive pads 112 as shown in FIG. 2A ).
- Conductive pillars 114 may be formed on the passivation layer 116 , and extend into these openings of the passivation layer 116 , so as to be electrically connected with the conductive pads 112 .
- portions of the conductive pillars 114 protruded from the passivation layer 116 may be laterally surrounded by an insulating material 118 .
- a front surface of the insulating material 118 i.e., a top surface of the insulating material 118 as shown in FIG. 2A
- the front surfaces of the conductive pillars 114 are currently covered by the insulating material 118 , and will be exposed when a planarization process is performed on the semiconductor die 100 and the encapsulant (e.g., the encapsulant 124 as shown in FIG. 2D ) laterally surrounding the semiconductor die 100 in the following step (e.g., step S 108 ).
- the encapsulant e.g., the encapsulant 124 as shown in FIG. 2D
- the semiconductor die 100 also includes through semiconductor vias (TSVs) 120 .
- TSVs 120 penetrate through the semiconductor substrate 102 from the back surface BS of the semiconductor substrate 102 to the active surface AS of the semiconductor substrate 102 , and are electrically connected with the interconnection elements 110 formed in the interconnection layer 108 .
- the TSV 120 further penetrates through the device layer 104 , and is in contact with the interconnection layer 108 .
- formation of the semiconductor die 100 is based on a TSV-middle process. In other words, the TSVs 120 are formed after forming the device layer 104 , but before forming the interconnection layer 108 .
- signals from the back surface BS of the semiconductor substrate 102 can be transmitted to the semiconductor devices 106 at the active surface AS of the semiconductor substrate 102 via the TSVs 120 and the interconnection elements 110 .
- the semiconductor devices 106 are located within a central region of the semiconductor die 100
- the TSVs 120 are disposed within a peripheral region of the semiconductor die 100 .
- front surfaces of the TSVs 120 are substantially coplanar with the active surface AS of the semiconductor substrate 102 , and the TSVs 120 may be electrically connected with the interconnection elements 110 by contact plugs (not shown) extending from the front surfaces of the TSVs 120 to a front surface of the device layer 104 (i.e., a top surface of the device layer 104 as shown in FIG. 2A ).
- formation of the semiconductor die 100 is based on a TSV-first process. That is, formation of the TSVs 120 precedes the steps of forming the device layer 104 and the interconnection layer 108 .
- substantially the whole semiconductor die 100 is penetrated by the TSVs 120 .
- formation of the semiconductor die 100 is based on a TSV-last process, and the TSVs 120 are formed after forming the device layer 104 and the interconnection layer 108 .
- step S 102 is performed, and a first carrier CA 1 is provided.
- the first carrier CA 1 is a glass carrier.
- an adhesion layer (not shown) may be formed over a surface of the first carrier CA 1 to which the semiconductor dies 100 are attached in the following step.
- the adhesion layer may be a light-to-heat-conversion (LTHC) layer, a thermal release layer or the like.
- step S 104 is performed, and through encapsulant vias (also known as through interposer vias (TIVs)) 122 may be formed over the first carrier CA 1 .
- TIVs through interposer vias
- the adhesion layer would be located between the through encapsulant vias 122 and the first carrier CA 1 .
- the through encapsulant vias 122 may be conductive pillars.
- a formation method of the through encapsulant vias 122 includes globally forming a seed layer (not shown) on the first carrier CA 1 .
- a photoresist pattern (not shown) having openings defining locations and dimensions of the through encapsulant vias 122 is formed over the seed layer.
- a conductive material is then filled in the openings of the photoresist pattern by, for example, a plating process, so as to form the through encapsulant vias 122 .
- the photoresist pattern is removed by, for example, a stripping process or an ashing process.
- step S 106 is performed, and a plurality of the semiconductor dies 100 are attached onto the first carrier CA 1 .
- the attached semiconductor dies 100 face upward.
- back surfaces BS of the semiconductor substrates 102 face toward the first carrier CA 1
- active surfaces AS of the semiconductor substrates 102 face away from the first carrier CA 1 .
- the through encapsulant vias 122 are pre-formed on the first carrier CA 1 , and a spacing between some adjacent through encapsulant vias 122 may be sufficiently large to accommodate at least one of the semiconductor dies 100 . For instance, as shown in FIG.
- the semiconductor dies 100 are attached onto the first carrier CA 1 , and each 2 of the semiconductor dies 100 are located between adjacent through encapsulant vias 122 .
- those skilled in the art may adjust the amount of the semiconductor die(s) 100 attached onto the first carrier CA 1 as well as the arrangement of the through encapsulant vias 122 and the semiconductor dies 100 , the present disclosure is not limited thereto.
- the semiconductor dies 100 are attached onto the first carrier CA 1 by a pick-and-place (PNP) process.
- PNP pick-and-place
- the pre-formed through encapsulant vias 122 may be functioned as alignment references.
- step S 108 is performed, and the semiconductor dies 100 are encapsulated by an encapsulant 124 .
- a reconstructed wafer including the semiconductor dies 100 and the encapsulant 124 is formed.
- both of the through encapsulant vias 122 and the semiconductor dies 100 are encapsulated by the encapsulant 124 .
- the through encapsulant vias 122 can be regarded as penetrating the encapsulant 124 .
- the through encapsulant vias 122 and the semiconductor dies 100 may be over-molded by an encapsulant material, such that the through encapsulant vias 122 and the semiconductor dies 100 are buried in the encapsulant material. Thereafter, a planarization process may be performed on the encapsulant material to expose front surfaces of the through encapsulant vias 122 and the conductive pillars 114 of the semiconductor dies 100 (i.e., top surfaces of the through encapsulant vias 122 and the conductive pillars 114 as shown in FIG. 2D ), so as to form the encapsulant 124 .
- a front surface 124 a of the encapsulant 124 is substantially coplanar with the front surfaces of the through encapsulant vias 122 and the conductive pillars 114 .
- a back surface 124 b of the encapsulant 124 is substantially coplanar with bottom surfaces of the through encapsulant vias 122 and the back surfaces BS of the semiconductor dies 100 .
- the planarization process may include a chemical mechanical polishing (CMP) process or an etching process.
- the step of forming the encapsulant 124 precedes the step of forming the through encapsulant vias 122 (i.e., step S 104 ).
- the semiconductor dies 100 are encapsulated by the encapsulant 124 in step S 108 .
- step S 104 some portions of the encapsulant 124 are removed to form through holes in the encapsulant 124 , and a conductive material is filled in the through holes in the encapsulant 124 , so as to form the through encapsulant vias 122 .
- a material of the encapsulant 124 is a photosensitive material, and the through holes can be formed by a photolithography process. In other embodiments, the encapsulant 124 is non-photosensitive, and the through holes are formed by a photolithography process and an etching process.
- step S 110 is performed, and a front redistribution structure 126 is formed over the reconstructed wafer as shown in FIG. 2D .
- a front surface of this reconstructed wafer i.e., a top surface of this reconstructed wafer as shown in FIG. 2D
- the front redistribution structure 126 covers the front redistribution structure 126 .
- the front surface 124 a of the encapsulant 124 and the front surfaces of the conductive pillars 114 and the through encapsulant vias 122 are covered by the front redistribution structure 126 .
- the front redistribution structure 126 includes a stack of dielectric layers 128 (e.g. 4 dielectric layers 128 ) and redistribution elements 130 .
- dielectric layers 128 e.g. 4 dielectric layers 128
- redistribution elements 130 are formed in the stack of dielectric layers 128 .
- some of the redistribution elements 130 are electrically connected with the interconnection layers 108 of the semiconductor dies 100 through the conductive pillars 114 , whereas others of the redistribution elements 130 are electrically connected with the through encapsulant vias 122 .
- the redistribution elements 130 include conductive vias, conductive traces or a combination thereof.
- I/Os e.g., the conductive pillars 114
- the semiconductor dies 100 can be out-routed to the span of the reconstructed wafer in which the semiconductor dies 100 is laterally encapsulated by the encapsulant 124 .
- Step S 112 is performed, and front electrical connectors 132 are formed over the front redistribution structure 126 .
- the front electrical connectors 132 are electrically connected with the redistribution elements 130 located in the front redistribution structure 126 .
- the front electrical connectors 132 include controlled collapse chip connection (C4) bumps, solder bumps, ball grid array (BGA) balls, conductive pillars, the like or combinations thereof.
- a formation method of the front electrical connectors 132 may include patterning the outmost dielectric layer 128 of the front redistribution structure 126 . Thereafter, the front electrical connectors 132 are respectively formed in these openings.
- under bump metallization (UBM) layers 134 may be formed to respectively cover theses openings of the outmost dielectric layer 128 before forming the front electrical connectors 132 .
- the UBM layers 134 after forming the front electrical connectors 132 , respectively lie between the front electrical connectors 132 and the outmost redistribution elements 130 , and between the front electrical connectors 132 and the outmost dielectric layer 128 .
- step S 114 is performed, and a second carrier CA 2 is attached to a front surface of the current package structure (as shown in FIG. 2E ) that faces away from the first carrier CA 1 .
- the current structure is flipped over, and the first carrier CA 1 is detached from the package structure.
- the second carrier CA 2 is attached to the front electrical connectors 132 of the package structure.
- an adhesion layer 136 is pre-formed over a surface of the second carrier CA 2 to which front electrical connectors 132 are attached.
- the adhesion layer 136 lies between the front electrical connectors 132 and the second carrier CA 2 .
- the second carrier CA 2 is attached to the package structure via a lamination process, and the front electrical connectors 132 may be embedded into the adhesion layer 136 .
- a space between the front redistribution structure 126 and the second carrier CA 2 may be further filled by the adhesion layer 136 .
- the second carrier CA 2 is a glass carrier.
- the back surfaces BS of the semiconductor substrates 102 , the back surface 124 b of encapsulant 124 and back surfaces of the through encapsulant vias 122 and the TSVs 120 facing away from the second carrier CA 2 i.e., top surfaces of the through encapsulant vias 122 and the TSVs 120 as shown in FIG. 2F ) are exposed.
- an adhesion layer (not shown) such as a LTHC layer or a thermal release layer is pre-formed on the first carrier CA 1 , and the first carrier CA 1 with the adhesion layer is detached as the adhesion layer loses its adhesive property when exposed to light or heat.
- step S 116 is performed, and a back redistribution structure 138 is formed over the exposed surface of the current package structure as shown in FIG. 2F . That is, the back surfaces BS of the semiconductor substrates 102 , the back surface 124 b of the encapsulant 124 and the back surfaces of the through encapsulant vias 122 and the TSVs 120 facing away from the second carrier CA 2 are covered by the back redistribution structure 138 .
- the back redistribution structure 138 includes a stack of dielectric layers 140 (e.g. 4 dielectric layers 140 ) and redistribution elements 142 .
- the redistribution elements 142 are formed in the stack of dielectric layers 140 .
- some of the redistribution elements 142 are electrically connected with the TSVs 120 of the semiconductor dies 100 , whereas others of the redistribution elements 142 are electrically connected with the through encapsulant vias 122 .
- the TSV 120 is electrically connected between the interconnection layer 108 and the back redistribution structure 138
- the through encapsulant via 122 is electrically connected between the front and back redistribution structures 126 and 138 .
- the redistribution elements 142 include conductive vias, conductive traces or a combination thereof.
- Step S 118 is performed, and back electrical connectors 144 are formed over the back redistribution structure 138 .
- the back electrical connectors 144 are electrically connected with the redistribution elements 142 located in the back redistribution structure 138 .
- the back electrical connectors 144 include controlled collapse chip connection (C4) bumps, solder bumps, ball grid array (BGA) balls, conductive pillars, the like or combinations thereof.
- a formation method of the back electrical connectors 144 may include patterning the outmost dielectric layer 140 of the back redistribution structure 138 . Thereafter, the back electrical connectors 144 are respectively formed in these openings.
- under bump metallization (UBM) layers 146 may be formed to respectively cover theses openings of the outmost dielectric layer 140 before forming the back electrical connectors 144 .
- the UBM layers 146 after forming the back electrical connectors 144 , respectively lie between the back electrical connectors 144 and the outmost redistribution elements 142 , and between the back electrical connectors 144 and the outmost dielectric layer 140 .
- step S 120 is performed, and the second carrier CA 2 is detached.
- a front surface and a back surface of the current package structure are exposed.
- the front surface of the current package structure includes surfaces of the front electrical connectors 132 and the front redistribution structure 126
- the back surface of the current package structure includes surfaces of the back electrical connectors 144 and the back redistribution structure 138 .
- the adhesion layer 136 pre-formed on the second carrier CA 2 is a LTHC layer or a thermal release layer, and the second carrier CA 2 with the adhesion layer 136 is detached as the adhesion layer 136 loses its adhesive property when exposed to light or heat.
- the current package structure may be attached to a tape TP.
- the current package structure is flipped over, and the front electrical connectors 132 are attached to the tape TP.
- the tape TP is connected to a frame (not shown).
- step S 122 is performed, and a singulation process may be performed on the current package structure.
- the singulated package structures are respectively referred as a semiconductor package 10 .
- the semiconductor packages 10 respectively include at least one of the semiconductor dies 100 and the through encapsulant vias 122 located around the semiconductor die(s) 100 .
- the singulation process includes a sawing process, a laser ablation process, an etching process, the like or combinations thereof.
- step S 124 is performed, and the semiconductor package 10 is attached onto a bottom semiconductor package 150 .
- the bottom semiconductor package 150 includes a semiconductor die 152 , through encapsulant vias 154 and an encapsulant 156 .
- the through encapsulant vias 154 are located around the semiconductor die 152 .
- the semiconductor die 152 and the through encapsulant vias 154 are encapsulated by the encapsulant 156 .
- the semiconductor die 152 is a logic die, such as a controller die. The semiconductor die 152 may face down.
- an active surface (or referred as a front surface) AS 1 of the semiconductor die 152 faces away from overlying semiconductor package 10
- a back surface BS 1 of the semiconductor die 152 faces toward the semiconductor package 10
- the active surface AS 1 of the semiconductor die 152 is exposed by the encapsulant 156
- the back surface BS 1 of the semiconductor die 152 may be buried in the encapsulant 156 .
- the semiconductor die 152 has conductive pillars 153 , which are exposed at the active surface AS 1 of the semiconductor die 152 , and may be functioned as I/Os of the semiconductor die 152 .
- a front redistribution structure 158 may be disposed over the active surface AS 1 of the semiconductor die 152 , a front surface 156 a of the encapsulant 156 and front surfaces of the through encapsulant vias 154 facing away from the overlying semiconductor package 10 .
- the front redistribution structure 158 includes redistribution elements 160 and at least one dielectric layer 162 .
- the redistribution elements 160 are embedded in the dielectric layer(s) 162 , and are electrically connected with the I/Os (e.g., the conductive pillars 153 ) of the semiconductor die 152 and the through encapsulant vias 154 . It should be noted that, the redistribution elements 160 are schematically depicted in FIG.
- front electrical connectors 164 may be disposed over a surface of the front redistribution structure 158 (i.e., a bottom surface of the front redistribution structure 158 as shown in FIG. 2J ). The front electrical connectors 164 are electrically connected with the redistribution elements 160 formed in the front redistribution structure 158 .
- the front electrical connectors 164 may include C4 bumps, solder bumps, ball grid array (BGA) balls, the like or combinations thereof. Furthermore, in some embodiments, the front electrical connectors 164 are attached with a package substrate 166 . As such, the front electrical connectors 164 are connected between the front redistribution structure 158 and the package substrate 166 . In some embodiments, the package substrate 166 may be a printed circuit board (PCB), such as a core PCB or a coreless PCB.
- PCB printed circuit board
- a back redistribution structure 168 may be disposed over a back surface 156 b of the encapsulant 156 and back surfaces of the through encapsulant vias 154 facing toward the semiconductor package 10 .
- the back redistribution structure 168 includes redistribution elements 170 and at least one dielectric layer 172 .
- the redistribution elements 170 are embedded in the dielectric layer(s) 172 , and are electrically connected with the through encapsulant vias 154 .
- the redistribution elements 170 of the back redistribution structure 168 are not in direct electrical contact with the semiconductor die 152 , but may be electrically connected to the semiconductor die 152 by the through encapsulant vias 154 and the front redistribution structure 158 . It should be noted that, the redistribution elements 170 are schematically depicted in FIG. 2J , and may actually include conductive traces, conductive vias or a combination thereof.
- back electrical connectors 174 may be disposed over a surface of the back redistribution structure 168 (i.e., a top surface of the back redistribution structure 168 as shown in FIG. 2J ).
- the back electrical connectors 174 are electrically connected with the redistribution elements 170 formed in the back redistribution structure 168 .
- the electrical connection between the semiconductor package 10 and the bottom semiconductor package 150 is realized by bonding the front electrical connectors 132 of the semiconductor package 10 with the back electrical connectors 174 of the bottom semiconductor package 150 .
- the back electrical connectors 174 may include C4 bumps, solder bumps, ball grid array (BGA) balls, the like or combinations thereof.
- step S 126 is performed, and a top semiconductor package 180 is attached onto the semiconductor package 10 .
- the top semiconductor package 180 includes a stack of semiconductor dies 182 , a substrate 184 and an encapsulant 186 .
- the stack of the semiconductor dies 182 is disposed over the substrate 184 , and is encapsulated by the encapsulant 186 .
- the semiconductor dies 182 includes a logic die, a memory die (e.g., a low power memory die), the like or combinations thereof.
- Interconnection elements 188 may be formed in the substrate 184 , and semiconductor devices (not shown) in the semiconductor dies 182 may be electrically connected with the interconnection elements 188 through bonding wires 190 .
- electrical connectors 192 are disposed at a surface of the substrate 184 facing toward the semiconductor package 10 , and are electrically connected with the interconnection elements 188 in the substrate 184 .
- the electrical connection between the top semiconductor package 180 and the semiconductor package 10 is realized by bonding the electrical connectors 192 of the top semiconductor package 180 with the back electrical connectors 144 .
- the electrical connectors 192 may include C4 bumps, solder bumps, ball grid array (BGA) balls, the like or combinations thereof.
- a semiconductor package stack 20 including the middle semiconductor package (i.e., the semiconductor package 10 ), the bottom semiconductor package 150 and the top semiconductor package 180 is formed, and can be regarded as a package-on-package (PoP) structure.
- the semiconductor package 10 is stacked between the top semiconductor package 180 and the bottom semiconductor package 150 , and includes both of the through encapsulant vias 122 and the TSVs 120 .
- the through encapsulant via 122 penetrates through the encapsulant 124 that laterally surrounds the semiconductor die 100
- the TSV 120 penetrates the semiconductor die 100 from a back side of the semiconductor die 100 to an active side of the semiconductor die 100 .
- the through encapsulant via 122 is electrically connected to the top semiconductor package 180 via the back redistribution structure 138 and the back electrical connector 133 , and is electrically connected to the bottom semiconductor package 150 via the front redistribution structure 126 and the front electrical connectors 132 .
- signals from the back side of the semiconductor die 100 can be transmitted to the active side of the semiconductor die 100 via the back redistribution structure 138 and the TSV 120 without going through the through encapsulant via 122 and the front redistribution structure 126 disposed at the active side of the semiconductor die 100 , and vice versa.
- transmission length of the signals transmitted between the back side of the semiconductor die 100 and the active side of the semiconductor die 100 is shortened.
- requirement on routing density of the front redistribution structure 126 of the semiconductor package 10 can be alleviated, and reliability of the semiconductor package 10 can be improved.
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Abstract
Description
Claims (17)
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US20200251454A1 (en) | 2020-08-06 |
TW202030848A (en) | 2020-08-16 |
CN111524878A (en) | 2020-08-11 |
US11901344B2 (en) | 2024-02-13 |
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