CN116779556A

CN116779556A - Semiconductor package and method of forming the same

Info

Publication number: CN116779556A
Application number: CN202310568135.7A
Authority: CN
Inventors: 吴松岳; 廖仁骏; 张楙曮; 赖昱嘉; 黄见翎; 谢静华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-26
Filing date: 2023-05-18
Publication date: 2023-09-19

Abstract

An embodiment of the present invention provides a semiconductor package including a first package assembly including: an integrated circuit die; an encapsulant surrounding the integrated circuit die; a fan-out structure electrically connected to the integrated circuit die, wherein, in a cross-sectional view, the first opening extends completely through the fan-out structure and at least partially through the encapsulant, and, in a top view, the encapsulant at least completely surrounds the first opening. The semiconductor package further includes a package substrate bonded to the first package assembly. Embodiments of the present invention also provide a method of manufacturing a semiconductor package.

Description

Semiconductor package and method of forming the same

Technical Field

Embodiments of the present invention relate generally to the field of semiconductors, and more particularly, to semiconductor packages and methods of manufacturing the same.

Background

As the integration of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) continues to increase, the semiconductor industry has experienced a rapid increase. In most cases, the increase in integration is due to the iterative decrease in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices continues to grow, there is a need for smaller, more innovative semiconductor die packaging techniques. An example of such a packaging system is the package on package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and small package area on Printed Circuit Boards (PCBs).

Disclosure of Invention

An embodiment of the present invention provides a semiconductor package including: a first package assembly comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die; and a fan-out structure electrically connected to the integrated circuit die, wherein, in a cross-sectional view, a first opening extends completely through the fan-out structure and at least partially through the encapsulant, and in a top-down view, the encapsulant at least completely surrounds the first opening; and a package substrate bonded to the first package assembly.

Another embodiment of the present invention provides a semiconductor package including: a first package assembly comprising: a first integrated circuit die; a second integrated circuit die; an encapsulant surrounding the first and second integrated circuit dies; a fan-out structure electrically connecting the first integrated circuit die to the second integrated circuit die; an electrically conductive package assembly extending through the fan-out structure to the encapsulant, wherein the electrically conductive package assembly is a high thermal conductivity element, an EMI shielding element, or a combination thereof; and a package substrate bonded to the first package assembly.

Yet another embodiment of the present invention provides a method of manufacturing a semiconductor package, the method including: forming a first package assembly, the forming the first package assembly comprising: encapsulating the integrated circuit die in a molding compound; forming a redistribution structure over the molding compound and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die; patterning openings extending through the redistribution structure into the encapsulant after forming the redistribution structure; and bonding a package substrate to the first package assembly.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 to 14, 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 15I, 15J, 15K, 15L, 15M, 15N, 15O, 15P, 15Q, 15R, 15S, 15T, 16A, 16B, 17A, 17B, 17C, 18A, and 18B illustrate cross-sectional and top views of manufacturing a device package according to some embodiments.

Fig. 19, 20A, 20B, 20C, 20D, 20E, and 20F illustrate cross-sectional views of manufacturing a device package according to some embodiments.

Fig. 21, 22, 23A, 23B, 23C, 23D, 23E, and 23F illustrate cross-sectional views of manufacturing a device package according to some embodiments.

Fig. 24, 25A, 25B, 25C, 25D, 25E, and 25F illustrate cross-sectional views of manufacturing a device package according to some embodiments.

Detailed Description

The invention provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. Such as in the following description, forming the first component over or on the second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "below …," "below …," "lower," "above …," "upper" and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, one or more integrated circuit dies are electrically connected by a fan-out structure (e.g., a redistribution structure, interposer, local Silicon Interconnect (LSI), etc.), and the integrated circuit dies may be packaged for further packaging with other packaging components (e.g., a package substrate, etc.). One or more openings may be formed in the molding compound and/or the fan-out structure. Including an opening may provide the following non-limiting advantages. For example, the opening may facilitate heat dissipation from the semiconductor die through the opening. As another example, the openings may facilitate insertion of one or more advantageous components, such as heat dissipating components, electromagnetic interference (EMI) shielding, and the like. Furthermore, the openings may facilitate insertion of structural support elements (e.g., brackets, etc.) into the package. As a result, improved packaging performance and/or ease of manufacture may be achieved.

Fig. 1 illustrates a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 may be a logic die (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), an Application Processor (AP), a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front end die (e.g., an Analog Front End (AFE)) die, etc., or a combination thereof.

Integrated circuit die 50 may be formed in a wafer that may include various device regions that are singulated in subsequent steps to form a plurality of integrated circuit die. The integrated circuit die 50 may be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may comprise other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., the surface facing upward in fig. 1), sometimes referred to as the front surface, and a passive surface (e.g., the surface facing downward in fig. 1), sometimes referred to as the back surface.

Devices (represented by transistors) 54 may be formed on the front surface of semiconductor substrate 52. Device 54 may be an active device (e.g., transistor, diode, etc.), capacitor, resistor, etc. An interlayer dielectric (ILD) 56 is over the front surface of the semiconductor substrate 52. ILD 56 surrounds and may cover device 54.ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like.

Conductive plugs 58 extend through ILD 56 to electrically and physically connect members 54. For example, when device 54 is a transistor, conductive plugs 58 may connect the gate and source/drain regions of the transistor. Source/drain regions may refer to either source or drain, individually or collectively depending on the context. The conductive plugs 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or combinations thereof. Interconnect structure 60 is over ILD 56 and conductive plug 58. Interconnect structure 60 interconnects devices 54 to form an integrated circuit. Interconnect structure 60 may be formed by, for example, metallization patterns in various dielectric layers over ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 60 is electrically connected to device 54 through conductive plugs 58.

The integrated circuit die 50 also includes a pad 62, such as an aluminum pad, externally connected to the pad 62. Pads 62 are on the active side of integrated circuit die 50, such as in and/or on interconnect structure 60. One or more passivation films 64 are on the integrated circuit die 50, such as on portions of the interconnect structure 60 and the pads 62. The opening extends through passivation film 64 to pad 62. Die connectors 66, such as conductive posts (e.g., formed of a metal such as copper) extend through openings in passivation film 64 and are physically and electrically connected to respective ones of pads 62. The die connectors 66 may be formed by, for example, plating or the like. Die connectors 66 electrically connect respective integrated circuits of integrated circuit die 50.

Alternatively, solder regions (e.g., solder balls or solder bumps) may be provided on the pads 62. Solder balls may be used to perform Chip Probe (CP) testing on the integrated circuit die 50. CP tests may be performed on integrated circuit die 50 to determine if integrated circuit die 50 is a Known Good Die (KGD). Thus, only the integrated circuit die 50 that is KGD is processed and packaged later, while the die that fails the CP test is not packaged. After testing, the solder areas may be removed in a subsequent processing step.

Dielectric layer 68 may (or may not) be on the active side of integrated circuit die 50, such as on passivation film 64 and die attach 66. Dielectric layer 68 laterally encapsulates die connectors 66, and dielectric layer 68 is laterally co-terminal with integrated circuit die 50. Initially, dielectric layer 68 may bury die connectors 66 such that the topmost surface of dielectric layer 68 is above the topmost surface of die connectors 66. In embodiments where the solder regions are disposed on die attach 66, dielectric layer 68 may also bury the solder regions. Alternatively, the solder regions may be removed prior to forming dielectric layer 68.

Dielectric layer 68 may be: polymers such as PBO, polyimide, BCB, etc.; nitrides, such as silicon nitride and the like; oxides such as silicon oxide, PSG, BSG, BPSG, etc.; an analog or a combination thereof. Dielectric layer 68 may be formed, for example, by spin coating, lamination, chemical Vapor Deposition (CVD), and the like. In some embodiments, die connectors 66 are exposed through dielectric layer 68 during formation of integrated circuit die 50. In some embodiments, die connectors 66 remain buried and exposed during subsequent processes for packaging integrated circuit die 50. Exposing the die connectors 66 may remove any solder regions that may be present on the die connectors 66.

In some embodiments, integrated circuit die 50 is a stacked device that includes a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a Hybrid Memory Cube (HMC) module, a High Bandwidth Memory (HBM) module, or the like. In such an embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each semiconductor substrate 52 may (or may not) have an interconnect structure 60.

Fig. 2-15T illustrate cross-sectional views of intermediate steps during a process for forming the first package assembly 100, according to some embodiments. A first package region 100A and a second package region 100B are shown and one or more integrated circuit dies 50 are packaged to form an integrated circuit package in each package region 100A and 100B. Integrated circuit packages may also be referred to as integrated fan-out (InFO) packages.

In fig. 2, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer so that multiple packages may be formed simultaneously on the carrier substrate 102.

The release layer 104 may be formed of a polymer-based material that may be removed along with the carrier substrate 102 from the overlying structure to be formed in a later step. In some embodiments, the release layer 104 is an epoxy-based pyroelectric material that loses its adhesion when heated, such as a photo-thermal conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an Ultraviolet (UV) glue that loses its adhesive properties when exposed to ultraviolet light. The release layer 104 may be dispensed as a liquid and cured, may be a laminate film laminated to the carrier substrate 102, or the like. The top surface of the release layer 104 may be horizontal and may have a high degree of planarity.

In fig. 3, a backside redistribution structure 106 may be formed on the release layer 104. In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108, a metallization pattern 110 (sometimes referred to as a redistribution layer or redistribution line), and a dielectric layer 112. The backside redistribution structure 106 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed on the release layer 104 in place of the backside redistribution structure 106.

A dielectric layer 108 may be formed on the release layer 104. The bottom surface of the dielectric layer 108 may be in contact with the top surface of the release layer 104. In some embodiments, the dielectric layer 108 is formed from a polymer, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 108 is formed from: nitrides, such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), and the like; similar materials, etc. The dielectric layer 108 may be formed by any acceptable deposition process, such as spin-on, CVD, lamination, and the like, or combinations thereof.

A metallization pattern 110 may be formed on the dielectric layer 108. As an example of forming the metallization pattern 110, a seed layer is formed over the dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical Vapor Deposition (PVD) or the like. A photoresist (not shown) is then formed and patterned over the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of photoresist corresponds to the metallization pattern 110. Openings are patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, for example, by wet or dry etching. The remaining portion of the seed layer and the conductive material form a metallization pattern 110.

A dielectric layer 112 may be formed on the metallization pattern 110 and the dielectric layer 108. In some embodiments, the dielectric layer 112 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like that may be patterned using a photolithographic mask. In other embodiments, the dielectric layer 112 is formed of the following materials: nitrides, such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG, etc.; similar materials, etc. The dielectric layer 112 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 112 is then patterned to form openings 114 exposing portions of the metallization pattern 110. Patterning may be formed by acceptable processes, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material or by etching using, for example, anisotropic etching. If the dielectric layer 112 is a photosensitive material, the dielectric layer 112 may be developed after exposure.

For illustration purposes, fig. 3 shows a redistribution structure 106 having a single metallization pattern 110. In some embodiments, the backside redistribution structure 106 may include any number of dielectric layers and metallization patterns. The above steps and process may be repeated if more dielectric layers and metallization patterns are to be formed. The metallization pattern may include one or more conductive elements. The conductive elements may be formed during the formation of the metallization pattern by forming a seed layer of the metallization pattern and a conductive material in openings of the underlying dielectric layer and on the surface of the underlying dielectric layer, thereby interconnecting and electrically connecting the various wires.

In fig. 4, a through via 116 is formed in the opening 114 and extends away from the topmost dielectric layer (e.g., dielectric layer 112) of the backside redistribution structure 106. As an example of forming the through-holes 116, a seed layer (not shown) is formed over the backside redistribution structure 106, for example, on the dielectric layer 112 and the portions of the metallization pattern 110 exposed by the openings 114. In embodiments, the seed layer is a metal layer, which may be a single layer or a composite of multiple sub-layers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned over the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive via. Openings are patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, for example, by wet or dry etching. The seed layer and the remainder of the conductive material form a through hole 116.

In fig. 5, the integrated circuit die 50 (e.g., the first integrated circuit die 50A and the second integrated circuit die 50B) are adhered to the dielectric layer 112 by an adhesive 118. The desired type and number of integrated circuit die 50 are adhered in the package regions 100A and 100B, respectively. In the illustrated embodiment, the plurality of integrated circuit dies 50 are adhered adjacent to one another, including the first integrated circuit die 50A and the second integrated circuit die 50B in each of the first package region 100A and the second package region 100B. The first integrated circuit die 50A may be a logic device such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), a microcontroller, or the like. The second integrated circuit die 50B may be a memory device such as a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, a Hybrid Memory Cube (HMC) module, a High Bandwidth Memory (HBM) module, or the like. In some embodiments, integrated circuit dies 50A and 50B may be the same type of die, such as SoC die. The first integrated circuit die 50A and the second integrated circuit die 50B may be formed in the same technology node process or may be formed in different technology node processes. For example, the first integrated circuit die 50A may have a more advanced process node than the second integrated circuit die 50B. Integrated circuit dies 50A and 50B may have different dimensions (e.g., different heights and/or surface areas), or may have the same dimensions (e.g., the same height and/or surface area). The space available for the through-holes 116 in the first and second package regions 100A, 100B may be limited, particularly when the integrated circuit die 50 includes devices (e.g., socs) having a large footprint. The use of the backside redistribution structure 106 allows for improved interconnect placement when the first and second package regions 100A, 100B have limited space available for the through-holes 116.

Adhesive 118 is on the back side of integrated circuit die 50 and adheres integrated circuit die 50 to back side redistribution structure 106, for example to dielectric layer 112. Adhesive 118 may be any suitable adhesive, epoxy, die Attach Film (DAF), or the like. The adhesive 118 may be applied to the back side of the integrated circuit die 50, on the surface of the carrier substrate 102 if the back side redistribution structure 106 is not used, or on the upper surface of the back side redistribution structure 106 if applicable. For example, adhesive 118 may be applied to the back side of integrated circuit die 50 prior to singulation (singulation) to separate integrated circuit die 50.

In fig. 6, a sealant 120 is formed on and around the various components. After formation, encapsulant 120 encapsulates through-hole 116 and integrated circuit die 50. The encapsulant 120 may be a molding compound, an epoxy, or the like. The encapsulant 120 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 102 such that the through-holes 116 and/or the integrated circuit die 50 are buried or covered. The encapsulant 120 is also formed in the interstitial regions between the individual integrated circuit dies 50. The sealant 120 may be applied in liquid or semi-liquid form and then subsequently cured.

In fig. 7, a planarization process is performed on the encapsulant 120 to expose the through-holes 116 and the die connectors 66. The planarization process may also remove material of the through-holes 116, the dielectric layer 68, and/or the die connectors 66 until the die connectors 66 and the through-holes 116 are exposed. After the planarization process within the process variation tolerance, the top surfaces of the through-holes 116, die connectors 66, dielectric layer 68, and encapsulant 120 are substantially coplanar. The planarization process may be, for example, a Chemical Mechanical Polishing (CMP), a grinding process, or the like. In some embodiments, for example, if the through-holes 116 and/or die connectors 66 have been exposed, planarization may be omitted.

In fig. 8-11, a front side redistribution structure 122 is formed over the encapsulant 120, the through vias 116, and the integrated circuit die 50 (see fig. 11). The front side redistribution structure 122 includes: dielectric layers 124, 128, 132, and 136; the patterns 126, 130 and 134 are metallized. The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The front side redistribution structure 122 is shown as an example with a three-layer metallization pattern. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 122. Steps and processes discussed below may be omitted if fewer dielectric layers and metallization patterns are to be formed. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

In fig. 8, a dielectric layer 124 is deposited over encapsulant 120, through-holes 116, and die connectors 66. In some embodiments, the dielectric layer 124 is formed of a photosensitive material (such as PBO, polyimide, BCB) that can be patterned using a photolithographic mask. The dielectric layer 124 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The dielectric layer 124 is then patterned. Openings are patterned to expose portions of the through-holes 116 and die connectors 66. Patterning may be performed by an acceptable process, such as by exposing and developing the dielectric layer 124 when the dielectric layer 124 is a photosensitive material, or by etching using, for example, anisotropic etching.

A metallization pattern 126 is then formed. Metallization pattern 126 includes conductive elements that extend along a major surface of dielectric layer 124 and extend through dielectric layer 124 to physically and electrically connect to through vias 116 and integrated circuit die 50. As an example of forming metallization pattern 126, a seed layer is formed over dielectric layer 124 and in openings extending through dielectric layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned over the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of photoresist corresponds to metallization pattern 126. Openings are patterned through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and over the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and portions of the underlying seed layer forms a metallization pattern 126. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, for example, by wet or dry etching.

In fig. 9, a dielectric layer 128 is deposited over the metallization pattern 126 and the dielectric layer 124. Dielectric layer 128 may be formed in a similar manner to dielectric layer 124 and may be formed of a similar material to dielectric layer 124.

A metallization pattern 130 is then formed. The metallization pattern 130 includes portions on and extending along a major surface of the dielectric layer 128. The metallization pattern 130 also includes portions that extend through the dielectric layer 128 to physically and electrically connect the metallization pattern 126. The metallization pattern 130 may be formed in a similar manner and of a similar material as the metallization pattern 126. In some embodiments, the metallization pattern 130 has a different size than the metallization pattern 126. For example, the wires and/or vias of metallization pattern 130 may be wider or thicker than the wires and/or vias of metallization pattern 126. Further, the metallization pattern 130 may be formed with a larger pitch than the metallization pattern 126.

In fig. 10, a dielectric layer 132 is deposited over the metallization pattern 130 and the dielectric layer 128. Dielectric layer 132 may be formed in a similar manner to dielectric layer 124 and may be formed of a similar material to dielectric layer 124.

A metallization pattern 134 is then formed. The metallization pattern 134 includes portions on and extending along a major surface of the dielectric layer 132. The metallization pattern 134 also includes portions that extend through the dielectric layer 132 to physically and electrically connect the metallization pattern 130. The metallization pattern 134 may be formed in a similar manner and of a similar material as the metallization pattern 126. The metallization pattern 134 is the topmost metallization pattern of the front side redistribution structure 122. Thus, all intermediate metallization patterns (e.g., metallization patterns 126 and 130) of the front side redistribution structure 122 are disposed between the metallization pattern 134 and the integrated circuit die 50. In some embodiments, the metallization pattern 134 has a different size than the metallization patterns 126 and 130. For example, the conductive lines and/or vias of metallization pattern 134 may be wider or thicker than the conductive lines and/or vias of metallization patterns 126 and 130. In addition, the metallization pattern 134 may be formed with a larger pitch than the metallization pattern 130.

In fig. 11, a dielectric layer 136 is deposited over the metallization pattern 134 and the dielectric layer 132. Dielectric layer 136 may be formed in a similar manner to dielectric layer 124 and may be formed of a similar material to dielectric layer 124. Dielectric layer 136 is the topmost dielectric layer of front side redistribution structure 122. Thus, all of the metallization patterns (e.g., metallization patterns 126, 130, and 134) of the front side redistribution structure 122 are disposed between the dielectric layer 136 and the integrated circuit die 50. In addition, all of the intermediate dielectric layers (e.g., dielectric layers 124, 128, 132) of the front side redistribution structure 122 are disposed between the dielectric layer 136 and the integrated circuit die 50.

In fig. 12, carrier substrate debonding is performed to separate (or "debond") the carrier substrate 102 from the backside redistribution structure 106 (e.g., the dielectric layer 108). According to some embodiments, the debonding includes projecting light, such as laser or ultraviolet light, onto the release layer 104 such that the release layer 104 breaks down under the heat of the light and thus the carrier substrate 102 may be removed.

In fig. 13, conductive connection 152 is formed to extend through dielectric layer 108 to contact metallization pattern 110. An opening is formed through the dielectric layer 108 to expose a portion of the metallization pattern 110. For example, the openings may be formed using laser drilling, etching, or the like. Conductive connection 152 is formed in the opening. In some embodiments, the conductive connection 152 includes a flux and is formed in a flux dipping process. In some embodiments, the conductive connection 152 includes a conductive paste such as solder paste, silver paste, or the like, and is dispensed during the printing process. In some embodiments, the conductive connection 152 is formed in a similar manner to the conductive connection 150 and may be formed of a similar material to the conductive connection 150.

In fig. 14, the dicing process is performed by sawing along, for example, scribe line regions between the first package region 100A and the second package region 100B. Sawing separates the first package region 100A from the second package region 100B. The resulting singulated first package assembly 100 is from one of the first package region 100A and the second package region 100B. The cutting process may include any suitable process, such as laser ablation, mechanical drilling, mechanical grinding, and the like, or combinations thereof. As a result of the dicing process, each first package assembly 100 may have a total width W1 (e.g., measured between the outer sidewalls) in the range of 5mm to 300mm (see fig. 15A and 15B). Each first package assembly 100 may also have an overall height H1 (see fig. 15A and 15B) in the range of 0.1mm to 300 mm.

In fig. 15A through 15T, one or more openings 160 may be formed in each individual package assembly 100. Referring first to fig. 15A, the openings 160 may be formed to extend completely through the first package assembly 100, for example, through the front side redistribution structure 122, the encapsulant 120, and the back side redistribution structure 106. The openings 160 may be formed using any suitable process, such as by laser machining, mechanical drilling/routing, plasma etching/bombardment, or chemical etching. In embodiments where the openings 160 are formed using a chemical etching process, sacrificial material (not shown) may be formed in the front side redistribution structures 122, the encapsulant 120, and the back side redistribution structures 106. The location, size, shape, and shape of the sacrificial material may correspond to the location, size, and shape of the opening 160, and the sacrificial material may be formed of a material that may have etch selectivity relative to the material of the encapsulant 120 and the material of the dielectric layers 108, 112, 124, 128, 132, and 136. For example, the sacrificial material may include a conductive material, such as copper or similar material formed by one or more plating processes (e.g., along lines similar to the metallization patterns and the vias 116 in the redistribution structures 106, 122). In such embodiments, the chemical etch may use a chemistry that selectively removes the sacrificial material without significantly removing the encapsulant 120 or the dielectric layers 108, 112, 124, 128, 132, and 136.

The openings 160 may facilitate heat transfer from the integrated circuit die 50 by increasing the number of heat dissipation surfaces in the first package assembly 100. For example, the sidewalls of the opening 160 may provide additional heat dissipation surfaces in the first package assembly 100. In some embodiments, the opening 160 may further facilitate process integration by allowing subsequent components to be inserted into the opening 160. For example, in some embodiments, heat transfer structures, EMI shielding structures, mechanical standoffs, etc. may then be inserted into the openings 160 to improve the structural integrity and/or performance of the resulting semiconductor package. Each opening 160 may each have a maximum width W2 in the range of 0.05mm to 10 mm.

Fig. 15A shows the opening 160 extending completely through the first package assembly 100. In other embodiments, the opening 160 may extend only partially through the first package assembly 100. For example, fig. 15B illustrates an embodiment in which the openings 160 extend through the front side redistribution structure 122 and partially into the encapsulant 120. However, portions of the encapsulant 120 may remain below the openings 160, and the openings 160 may not extend into the back side redistribution structure 106. In other embodiments, the opening 160 may extend to different depths in the first package assembly 100.

Fig. 15C-15Q illustrate top views of different configurations of the opening 160 in an embodiment of the first package assembly 100. For ease of reference, the front side redistribution structure 122 is omitted from these figures.

The opening 160 may have any suitable shape. For example, referring to fig. 15C and 15D, the openings 160 may have a circular (e.g., circular) shape in top view, and the openings 160 may be disposed between adjacent integrated circuit dies 50. The first package assembly 100 may include any number of circular openings 160, such as a single opening 160 (see fig. 15C) or a plurality of openings 160 (see fig. 15D).

In other embodiments, referring to fig. 15E and 15F, the openings 160 may have a rectangular shape in top view, and the openings 160 may be disposed between adjacent integrated circuit dies 50. The first package assembly 100 may include any number of rectangular openings 160, such as a single opening 160 (see fig. 15E) or a plurality of openings 160 (see fig. 15F).

In other embodiments, referring to fig. 15G, the opening 160 may have an irregular shape. For example, the openings 160 may be configured as micro-channels having a zigzag channel shape disposed between adjacent integrated circuit dies 50. Other shapes of the opening 160 are also possible.

Fig. 15C-15G illustrate a first package assembly 100 having two integrated circuit dies 50. In other embodiments, the opening 160 may be integrated with a different number of integrated circuit dies 50. For example, as shown in fig. 15H and 15I, the first package assembly 100 may include a greater number of integrated circuit dies 50 (e.g., six). The openings 160 may be disposed at regular intervals between adjacent integrated circuit dies 50. Further, the openings 160 may be integrated with the through holes 116 (see fig. 15H), or the openings 160 may be provided in a different column from the through holes 116 (see fig. 15I). As another example, the first package assembly 100 may include a single integrated circuit die 50, and the opening 160 may be disposed in a corner region of the encapsulant 120. This configuration is shown in fig. 15J. Other configurations are also possible.

In fig. 15C to 15J, each opening 160 is provided inside the first package assembly 100 and is completely surrounded by the first package assembly 100 in a top view. For example, in a top view, each opening 160 may be surrounded by at least the material of the encapsulant 120. In other embodiments, the opening 160 may be provided at an edge of the first package assembly 100 such that the first package assembly 100 only partially surrounds the opening 160. In such an embodiment, the first package assembly 100 may have different widths in a top view. Fig. 15K-15M illustrate an embodiment in which the opening 160 is provided at an edge of the package assembly 100. In the embodiment of fig. 15K and 15M, the openings 160 may be formed simultaneously with the cutting process described above with respect to fig. 14. Alternatively, the edge openings 160 may be formed after the singulation process first defines the substantially rectangular first package assembly 100 using the processes described above (e.g., laser machining, mechanical drilling/routing, plasma etching/bombardment, or chemical etching). In fig. 15K, openings 160 are provided at regular intervals along the entire periphery of the first package assembly 100 to achieve a scalloped edge shape. In fig. 15L and 15M, the opening 160 may be patterned only in corner regions of the first package assembly 100 to achieve rounded corners. Fig. 15L shows a male opening 160, while fig. 15M shows a female opening 160.

In other embodiments, the edge openings 160 (e.g., as shown in fig. 15K-15M) may be combined with the interior openings 160 (e.g., as shown in fig. 15C-15L). Fig. 15N to 15Q illustrate an embodiment in which the opening 160 is provided at the edge and inside of the first package assembly 100. In particular, fig. 15N shows a first package assembly 100 having scalloped edges (e.g., a plurality of edge openings 160) and a single circular opening 160 located inside the encapsulant 120. Fig. 15O shows a first package assembly 100 having a scalloped edge (e.g., a plurality of edge openings 160) and a plurality of circular openings 160 located inside the encapsulant 120. Fig. 15P shows a first package assembly 100 having scalloped edges (e.g., a plurality of edge openings 160) and a single rectangular opening 160 located inside the encapsulant 120. Fig. 15Q illustrates a first package assembly 100 having scalloped edges (e.g., a plurality of edge openings 160) and a plurality of rectangular openings 160 positioned inside the encapsulant 120. Other combinations are also possible.

In fig. 15A and 15B, the opening 160 has a substantially uniform width W2 throughout the cross-sectional view. In other embodiments, the opening 160 may have a different width in cross-section. For example, fig. 15R shows an embodiment in which each opening 160 has an upper portion having the width W2 described above and a lower portion having the width W3. The width W3 is smaller than the width W2 and discrete steps are provided in the opening 160. Fig. 15S shows another embodiment in which each opening 160 has a different width. Specifically, each opening 160 may be tapered with sloped sidewalls that transition from the width W2 to a smaller width W4. The width W2 may be disposed on the top surface of the front side redistribution structure 122 and the width W4 may be disposed on the bottom surface of the back side redistribution structure 106. Fig. 15T shows another embodiment in which each opening 160 has a different width. Specifically, each opening 160 may be tapered with sloped sidewalls that transition from the width W2 to the smaller width W5 and back to the larger width W6. The width W2 may be disposed on the top surface of the front side redistribution structure 122; the width W5 may be disposed at a midpoint of the encapsulant 120 and the width W6 may be disposed at a bottom surface of the back side redistribution structure 106. The width W6 may be equal to or different from the width W2.

Fig. 16A and 16B illustrate the formation and implementation of a device stack according to some embodiments. The device stack is formed from an integrated circuit package formed in the first package assembly 100. The device stack may also be referred to as a package on package (PoP) structure. Fig. 16A corresponds to the embodiment of fig. 15A, wherein the opening 160 extends completely through the first package assembly 100, and fig. 16B corresponds to the embodiment of fig. 15B, wherein the opening 160 extends partially through the first package assembly 100. It should be appreciated that the description of fig. 16A and 16B may be applied to any of the embodiments of fig. 15C-15T described above.

In fig. 16A and 16B, the second package assembly 200 is connected to the first package assembly 100. The second package assembly 200 includes, for example, a substrate 202 and one or more stacked die 210 (e.g., 210A and 210B) connected to the substrate 202. Although a set of stacked dies 210 (210A and 210B) is shown, in other embodiments, multiple stacked dies 210 (each having one or more stacked dies) may be disposed side-by-side, connected to the same surface of the substrate 202. The substrate 202 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Further, the substrate 202 may be a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon Germanium On Insulator (SGOI), or a combination thereof. In an alternative embodiment, the substrate 202 is based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin, such as FR4. Alternatives to core materials include bismaleimide-triazine (BT) resins, or other Printed Circuit Board (PCB) materials or films. Laminated films such as flavoured laminated film (ABF) or other laminates may be used for the substrate 202.

The substrate 202 may include active and passive devices (not shown). Various devices, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to create the structural and functional requirements of the design of the second package assembly 200. These devices may be formed using any suitable method.

The substrate 202 may also include a metallization layer (not shown) and conductive vias 208. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layer may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting these conductive material layers, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the substrate 202 is substantially free of active and passive devices.

The substrate 202 may have bond pads 204 on a first side of the substrate 202 to connect to the stacked die 210 and bond pads 206 on a second side of the substrate 202 opposite the first side to connect to the conductive connections 152. In some embodiments, bond pads 204 and 206 are formed by forming grooves (not shown) in dielectric layers (not shown) on the first and second sides of substrate 202. The grooves may be formed such that bond pads 204 and 206 are embedded in the dielectric layer. In other embodiments, bond pad 204 and bond pad 206 may be formed on a dielectric layer, thus omitting a recess. In some embodiments, bond pad 204 and bond pad 206 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, or the like, or combinations thereof. The conductive material of bond pad 204 and bond pad 206 may be deposited on the thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, atomic Layer Deposition (ALD), PVD, the like, or combinations thereof. In one embodiment, the conductive material of bond pads 204 and 206 is copper, tungsten, aluminum, silver, gold, or the like, or a combination thereof.

In some embodiments, bond pad 204 and bond pad 206 are UBMs that include three layers of conductive material (e.g., titanium, copper, and nickel layers). Other arrangements of materials and layers, such as chrome/chrome-copper alloy/copper/gold, titanium/titanium-tungsten/copper arrangement, or copper/nickel/gold arrangement, may be used to form bond pads 204 and bond pads 206. Any suitable material or material layer that may be used for bond pads 204 and 206 is fully intended to be included within the current scope of application. In some embodiments, a conductive via 208 extends through the substrate 202 and connects the at least one bond pad 204 to the at least one bond pad 206.

In the illustrated embodiment, stacked die 210 is connected to substrate 202 by bonding wires 212, but other connections, such as conductive bumps, may be used. In an embodiment, stacked die 210 is a stacked memory die. For example, stacked die 210 may be a memory die such as a Low Power (LP) Double Data Rate (DDR) memory module (such as an LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc., memory module).

Stacked die 210 and bond wires 212 may be encapsulated by a molding material 214. The molding material 214 may be molded over the stacked die 210 and the bonding wires 212, for example, using compression molding. In some embodiments, the molding material 214 is a molding compound, a polymer, an epoxy, a silica filler material, or the like, or a combination thereof. A curing process may be performed to cure the molding material 214; the curing process may be thermal curing, UV curing, or the like, or a combination thereof.

In some embodiments, stacked die 210 and bond wires 212 are buried in molding material 214, and after molding material 214 is cured, a planarization step, such as grinding, is performed to remove excess portions of molding material 214 and provide a substantially planar surface for second package assembly 200.

After the second package assembly 200 is formed, the second package assembly 200 is mechanically and electrically bonded to the first package assembly 100 by the conductive connections 152 and the metallization pattern of the front side redistribution structure 122. In some embodiments, stacked die 210 may be connected to integrated circuit dies 50A and 50B by bonding wires 212, bonding pads 204 and 206, conductive connections 152, and front side redistribution structure 122.

The conductive connectors 152 may be Ball Grid Array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG) technology, or the like. The conductive connection 152 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection 152 is formed by initially evaporating, plating, printing, solder transfer, ball placement, etc. to form a solder layer. Once the solder layer is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 150 includes a metal pillar (e.g., copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process.

Conductive connection 152 may be formed to extend through dielectric layer 136 to contact metallization pattern 134. An opening is formed through dielectric layer 136 to expose a portion of metallization pattern 134. The openings may be formed, for example, using laser drilling, etching, or the like. Conductive connection 152 is formed in the opening. In some embodiments, the conductive connection 152 includes a flux and is formed in a flux dipping process. In some embodiments, the conductive connection 152 includes a conductive paste such as solder paste, silver paste, or the like, and is dispensed during the printing process.

In some embodiments, a solder resist (not shown) is formed on a side of the substrate 202 opposite the stacked die 210. The conductive connection 152 may be disposed in an opening in the solder resist to electrically and mechanically connect to a conductive feature (e.g., bond pad 206) in the substrate 202. Solder resist may be used to protect areas of the substrate 202 from external damage.

In some embodiments, the conductive connector 152 has an epoxy flux (not shown) formed thereon prior to reflowing the epoxy flux, at least some of the epoxy portion of the epoxy flux remaining after the conductive connector 152 and the second package assembly 200 are attached to the first package assembly 100.

In some embodiments, the underfill 220 is formed between the first package assembly 100 and the second package assembly 200 while surrounding the conductive connection 152. The underfill may reduce stress and protect the joint created by the reflow of the conductive connection 152. The underfill may be formed by a capillary flow process after the second package assembly 200 is attached, or may be formed by a suitable deposition method before the second package assembly 200 is attached. In embodiments where an epoxy flux is formed, the epoxy flux may act as an underfill. Although the underfill 220 is shown as being entirely over the opening 160, in other embodiments, the underfill 220 may extend partially to an upper portion of the opening 160.

As also shown in fig. 16A and 16B, each first package assembly 100 may then be mounted to a package substrate 300 using conductive connections 150. The conductive connection 150 may be formed to extend through the dielectric layer 108 to contact the metallization pattern 110. An opening is formed through the dielectric layer 108 to expose portions of the metallization pattern 110. The openings may be formed, for example, using laser drilling, etching, or the like. Conductive connection 150 is formed in the opening. In some embodiments, the conductive connection 150 includes a flux and is formed in a flux dipping process. In some embodiments, the conductive connection 150 includes a conductive paste such as solder paste, silver paste, or the like, and is dispensed during the printing process. In some embodiments, conductive connection 150 is formed from a similar material using a similar process as conductive connection 152.

Package substrate 300 includes a substrate core 302 and bond pads 304 over substrate core 302. The substrate core 302 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials of silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. In addition, the substrate core 302 may be an SOI substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 302 is based on an insulating core such as a glass fiber reinforced resin core. One example core material is fiberglass resin, such as FR4. Alternatives to the core material include bismaleimide-triazine BT resin, or other PCB materials or films. Laminated films such as ABF or other laminates may be used for substrate core 302.

The substrate core 302 may include active and passive devices (not shown). Various devices, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to create the structural and functional requirements of the device stack design. Any suitable method may be used to form the device.

The substrate core 302 may also include metallization layers and vias (not shown), with the bond pads 304 physically and/or electrically connected to the metallization layers and vias. Metallization layers may be formed over the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layer may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the layers of conductive material, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, substrate core 302 is substantially free of active and passive devices.

The package substrate 300 may further include external connections 310 on an Under Bump Metallization (UBM) 312. Conductive connection 310 is formed on UBM 312. The conductive connectors 310 may be Ball Grid Array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG) technology, and the like. The conductive connector 310 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection 310 is formed from a solder layer initially formed by evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 310 includes a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process. The conductive connector 310 may be used to attach the package substrate 300 to another package component, such as a Printed Circuit Board (PCB), motherboard, another package substrate, and the like.

In some embodiments, the conductive connection 150 is reflowed to attach the first package assembly 100 to the bond pad 304. The conductive connection 150 electrically and/or physically connects the package substrate 300 (including the metallization layer in the substrate core 302) to the first package assembly 100. In some embodiments, a solder resist 306 is formed on the substrate core 302. The conductive connection 150 may be disposed in an opening in the solder resist 306 to electrically and mechanically connect to the bond pad 304. Solder resist 306 may be used to protect areas of substrate 202 from external damage.

The conductive connection 150 has an epoxy flux (not shown) formed thereon prior to reflowing the epoxy flux, leaving at least some of the epoxy portion of the epoxy flux behind after the first package component 100 is attached to the package substrate 300. These remaining epoxy portions may be used as an underfill to reduce stress and protect the joint created by reflowing the conductive connection 150. In some embodiments, an underfill 308 may be formed between the first package assembly 100 and the package substrate 300 and around the conductive connection 150. The underfill 308 may be formed by a capillary flow process after the first package assembly 100 is attached, or may be formed by a suitable deposition method prior to the first package assembly 100 is attached.

In some embodiments, passive devices (e.g., surface Mount Devices (SMDs), not shown) may also be attached to the first package assembly 100 (e.g., to UBM 138) or to the package substrate 300 (e.g., to pads 304). For example, the passive devices may be bonded to the same surface of the first package assembly 100 or the package substrate 300 as the conductive connection 150. The passive devices may be attached to the first package assembly 100 before the first package assembly 100 is mounted to the package substrate 300, or may be attached to the package substrate 300 before or after the first package assembly 100 is mounted on the package substrate 300.

Other components and processes may also be included. For example, test structures may be included to provide assistance in the verification testing of 3D packages or 3DIC devices. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate, which allows for testing of the 3D package or 3DIC, use of probes and/or probe cards, and the like. Verification tests may be performed on intermediate structures and final structures. Furthermore, the structures and methods disclosed herein may be used in conjunction with intermediate validated test methods that include known good die to improve yield and reduce cost.

Thus, a complete semiconductor package 400 is provided that includes the first package assembly 100, the second package assembly 200, and the package substrate 300. The first package assembly 100 includes individual integrated circuit dies 50 electrically connected to each other by fan-out structures (specifically, redistribution structures 122 and 106). The first package assembly 100 may include one or more openings 160 disposed therein that facilitate heat transfer away from the integrated circuit die 50 in the first package assembly by increasing the number of heat dissipation surfaces in the first package assembly 100. For example, the sidewalls of the opening 160 may provide additional heat dissipation surface in the first package. As shown in fig. 16A, the opening 160 may extend entirely through the first package assembly 100, or the opening 160 may extend only partially through the first package assembly 100. As a result, the reliability of the semiconductor package 400 can be improved.

In some embodiments, the opening 160 may facilitate process integration by allowing additional components to be inserted into the opening 160. For example, fig. 17A-17C illustrate cross-sectional views of a semiconductor package 420 according to some embodiments. Semiconductor package 420 may be substantially similar to semiconductor package 400, wherein like reference numerals indicate like elements formed by like processes unless otherwise specified. Fig. 17A-17C correspond to the embodiment of fig. 15A, wherein the opening 160 extends completely through the first package assembly 100. It should be appreciated that the description of fig. 17A-17C may be applied to any of the embodiments of fig. 15C-15T described above.

As shown in fig. 17A, 17B, and 17C, a bracket 162 may be placed in the opening 160 to improve the structural integrity of the semiconductor package 420. In addition, to accommodate placement of the stand-offs 162, the second package assembly 200 may be omitted from the semiconductor package 420 above the first package assembly 100. In some embodiments, the stand-offs 162 may extend completely through the first package assembly 100 and the package substrate 300, as shown in fig. 17A and 17C. In such embodiments, one or more openings through the package substrate 300 may be formed, and the first package assembly 100 may be placed such that the openings 160 are aligned with the openings in the package substrate 300. The metal bracket 162 may then be inserted through the opening 160 and the opening in the package substrate 300. Further, an optional horizontal metal strip 164 may be provided between the first package assembly 100 and the package substrate 300 to increase stability, and a bracket 162 may extend through the metal strip 164, as shown in fig. 17C. In yet another embodiment, the stand-offs 162 may extend only partially through the package substrate 300, as shown in fig. 17B. In such embodiments, the holder 162 may be inserted directly into the package substrate 300 without the need for pre-forming an opening.

In some embodiments, the opening 160 may facilitate process integration by allowing additional components to be inserted into the opening 160. As another example, fig. 18A and 18B illustrate cross-sectional views of a semiconductor package 440 according to some embodiments. The semiconductor package 440 may be substantially similar to the semiconductor package 400, wherein like reference numerals designate like elements formed by like processes unless otherwise specified. Fig. 18A corresponds to the embodiment of fig. 15A, wherein the opening 160 extends completely through the first package assembly 100, and fig. 18B corresponds to the embodiment of fig. 15B, wherein the opening 160 extends partially through the first package assembly 100. It should be understood that the description of fig. 18A and 18B may be applied to any of the embodiments of fig. 15C through 15T described above. In fig. 18A and 18B, the encapsulation member 166 may be inserted into one or more openings 160. The packaging component 166 may be a high thermal conductivity material/assembly (e.g., including copper, aluminum nitride, heating tubes, cooling tubes, etc.), an EMI shielding material/assembly (e.g., including copper, aluminum, etc.), combinations thereof, and the like. The encapsulation member 166 may be formed by plating a conductive material in the opening 160, by adhering a preformed encapsulation member 166 into the opening 160, or the like. By incorporating additional packaging components, packaging performance may be improved. Further, due to the presence of the opening 160, the package assembly can be easily incorporated into the package 440. As a result, the opening 160 may advantageously improve process integration in the package 440.

Although fig. 1-18B illustrate the first package assembly 100 as having a particular configuration (e.g., as an integrated fan-out package), other configurations are possible. For example, fig. 19-20F illustrate a first package assembly 100' in which the fan-out structure for connecting the integrated circuit dies is an interposer, according to some embodiments. According to some embodiments, the first package assembly 100' may be combined with other package assemblies (e.g., package substrate 300) to provide a semiconductor package 550, 560, or 570. Packages 550, 560, and 570 may be substantially similar to packages 400, 420, and 440, respectively, unless otherwise indicated, wherein like reference numerals refer to like elements formed by like processes. However, in the packages 550, 560, and 570, the first package assembly 100' has a different configuration from the package assemblies of the packages 400, 420, and 440. Specifically, the package assembly 100 'includes individual integrated circuit dies 50 bonded to the interposer 500 and electrically interconnected through the interposer 500, and then the package assembly 100' is bonded to the package substrate 300 in a chip-on-wafer-on-substrate (CoWoS) configuration.

Fig. 19 illustrates an interposer 500 prior to bonding any integrated circuit die, in accordance with some embodiments. Interposer 500 may be formed as part of a larger wafer. Interposer 500 may be processed according to applicable manufacturing processes to form integrated circuits in interposer 500. For example, the interposer 500 may include a semiconductor substrate 502, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 502 may include other semiconductor materials: such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used. Active and/or passive devices such as transistors, diodes, capacitors, resistors, inductors, and the like may be formed in and/or on the semiconductor substrate 502. In some embodiments, interposer 500 is devoid of any active devices and only passive devices are formed in and/or on semiconductor substrate 502. In other embodiments, interposer 500 may be devoid of active and passive devices.

The devices may be interconnected by an interconnect structure 506, the interconnect structure 506 including a metallization pattern 506A, for example, in one or more dielectric layers 506B (also referred to as insulating material layers 506B) on the semiconductor substrate 502. Dielectric layer 506B may be formed of a dielectric material deposited by a CVD process and patterned using a damascene process (e.g., a single damascene process, a dual damascene process, etc.). As an example of a damascene process, dielectric layer 506B may be deposited and openings may be patterned (e.g., using photolithography and/or etching) in dielectric layer 506B. Subsequently, the openings in the dielectric layer 506B may be filled with a conductive material, and the excess conductive material may be removed by a planarization process (e.g., chemical Mechanical Polishing (CMP), etc.) to form the metallization pattern 506A. Interconnect structure 506 electrically connects devices on substrate 502 to form one or more integrated circuits. Although fig. 19 shows interconnect structure 506 as having a particular number of metallization pattern 506A layers, embodiments contemplate interconnect structure 506 having any number of metallization pattern layers.

Interposer 500 also includes via 501, which may be electrically connected to metallization pattern 506A in interconnect structure 506. The through-hole 501 may include a conductive material (e.g., copper, etc.) and may extend from the metallization pattern 506A into the substrate 502. One or more insulating barriers 503 may be formed around at least a portion of the through-holes 501 in the substrate 502. The insulating barrier 503 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and the like, and may be used to physically and electrically isolate the through holes 501 from each other and from the substrate 502. In a subsequent processing step, the substrate 502 may be thinned to expose the through-holes 501 (see fig. 20A to 20F). After thinning, the through via 501 provides an electrical connection from the back side of the substrate 502 to the front side of the substrate 502. In various embodiments, the back side of substrate 502 may refer to the side of substrate 502 opposite device and interconnect structures 506 and the front side of substrate 502 may refer to the side of substrate 502 on which device and interconnect structures 506 are disposed.

In an embodiment, interposer 500 further includes contact pads 508 that enable interconnection structures 506 and device connections to substrate 502. The contact pads 508 may include copper, aluminum (e.g., 28K aluminum), or other conductive material. The contact pads 508 are electrically connected to the metallization pattern 506A of the interconnect structure 506. One or more passivation films may be disposed on the interconnect structure 506 and the contact pads 508. For example, interconnect structure 506 may include passivation films 510 and 512. The passivation films 510 and 512 may include inorganic materials, such as silicon oxide, silicon oxynitride, silicon nitride, and the like, respectively. In some embodiments, the materials of the passivation films 510 and 512 may be the same or different from each other. In addition, the material of the passivation films 510 and 512 may be the same as or different from the material of the dielectric layer 506B. In some embodiments, the contact pads 508 extend over and cover the edges of the passivation film 510, and the passivation film 512 extends over and covers the edges of the contact pads 508.

UBM 514 is formed for external connection to one or more integrated circuit dies. UBM 514 has bump portions on and extending along a major surface of passivation film 512 and has via portions extending through passivation film 512 to physically and electrically connect contact pads 508. Accordingly, UBM 514 is electrically connected to metallization pattern 506A and through via 501.UBM 514 may be formed from the same materials and processes as metallization pattern 126 described above.

Interposer 500 may be formed as part of a larger wafer (e.g., connected to other interposers 500). In some embodiments, the interposer 500 may be separated from each other after packaging. Subsequently, as shown in the embodiments of fig. 20A-20F, the integrated circuit die 50 is attached to the interposer 500. The integrated circuit die 50 may be attached to the front side of the interposer 500 such that the interconnect structure 506 is disposed between the semiconductor substrate 502 and the integrated circuit die 50.

In the illustrated embodiment, the integrated circuit die 50 is attached to the interposer 500 with solder bonding (e.g., conductive connections 526 on UBM 528 of the integrated circuit die 50). The integrated circuit die 50 may be placed on the interposer 500 using, for example, a pick-and-place tool. Conductive connection 526 may be formed from similar materials and similar methods as described above for conductive connection 152 (see fig. 16A and 16B), and UBM 528 may be formed from similar materials and similar methods as described above with respect to UBM 514. Attaching the integrated circuit die 50 to the interposer 500 may include placing the integrated circuit die 50 on the interposer 500 and reflowing the conductive connections 526. Conductive connections 526 form joints between UBM 514 of interposer 500 and UBM 528 of integrated circuit die 50, thereby electrically connecting interposer 500 to integrated circuit die 50.

As also shown in fig. 20A-20F, an underfill 524 may be formed around the conductive connections 526 and between the interposer 500 and the integrated circuit die 50. The underfill 524 may reduce stress and protect the joint created by the reflowed conductive connection 526. The underfill 524 may be formed of similar materials and similar methods as the underfill 308 described above. An encapsulant 120 may then be formed around the integrated circuit die 50 and the underfill 524.

Subsequently, the back surface of the substrate 502 is thinned to expose the through-hole 501. The exposure of the through-hole 501 may be accomplished by a thinning process, such as a grinding process, chemical Mechanical Polishing (CMP), etchback, combinations thereof, and the like. In some embodiments (not separately shown), the thinning process for exposing the through-holes 501 includes CMP, and the through-holes 501 protrude at the back of the interposer 500 due to the dishing that occurs during CMP. In such an embodiment, an insulating layer (not separately shown) may optionally be formed on the back surface of the substrate 502, surrounding the protruding portion of the through-hole 501. The insulating layer may be formed of a silicon-containing insulator, for example, silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition method, such as spin coating, CVD, plasma Enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), or the like. After the substrate 502 is thinned, the exposed surfaces of the through-holes 501 and the insulating layer (if present) or substrate 502 are coplanar (over process variations) such that they are flush with each other and exposed at the back side of the interposer 500.

In fig. 16, a back side redistribution structure (not shown) and UBM 520 are formed on the exposed surfaces of the through via 501 and substrate 502. The backside redistribution structure may be formed from materials and processes similar to the interconnect structure 506 or the redistribution structure 122 described above (see fig. 16A and 16B). For example, the back side redistribution structure may include one or more metallization layers in an insulating material. In addition, UBM 520 may be formed from similar materials and processes as UBM 542 described above.

Conductive connection 522 is formed on UBM 520. Conductive connectors 522 may be Ball Grid Array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or the like. The conductive connection 522 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection 522 is formed by a layer of solder initially formed by evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 522 includes a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process.

The dicing process is performed by dicing along scribe line regions of the interposer 500. The cutting process may include sawing, cutting, and the like. For example, the dicing process may include sawing the encapsulant 120, the interconnect structure 506, and the substrate 502. The dicing process separates each package 100 'from adjacent packages 100'. The dicing process forms interposer 500 from diced portions of the interposer wafer. As a result of the singulation process, the interposer 500 (including the interconnect structure 506, passivation layers 510/512, and substrate 502) and the outer sidewalls of the encapsulant 120 are laterally co-faceted (within process variations). Further, in plan view, the encapsulant 120 may completely surround the integrated circuit die 50.

The package 100' is attached to the package substrate 300 by flip-chip bonding with conductive connections 522. The underfill 308 may be formed around the conductive connection 522 between the first package assembly 100 'and the package substrate 300, and the opening 160 may be formed through the package 100', thereby completing the formation of the integrated circuit package. The openings 160 may have any of the configurations described above with respect to fig. 15A-15T and/or be formed by any process. Fig. 20A and 20B illustrate an exemplary completed semiconductor package 550 with an opening 160 according to some embodiments. In some embodiments, as shown in fig. 20A, the opening 160 may extend through the first package assembly 100 and the underfill 308 to the top surface of the package substrate 300. In some embodiments, as shown in fig. 20B, in addition to the first package assembly 100, the opening 160 may also extend through the package substrate 300. Fig. 20C and 20D illustrate an exemplary completed semiconductor package 560 with an opening 160 according to some embodiments. In the package 560, the bracket 162 may be placed in the opening 160 for additional structural support. Fig. 20C shows an embodiment in which the opening 160/bracket 162 extends to the package substrate 300, and fig. 20D shows an embodiment in which the opening 160/bracket 162 extends through the package substrate 300. Fig. 20E and 20F illustrate an exemplary completed semiconductor package 570 with an opening 160 according to some embodiments. In the enclosure 570, an enclosure assembly 166 (e.g., a high thermal conductivity material/assembly, an EMI shielding material/assembly, combinations thereof, etc.) may be placed in the opening 160. Fig. 20E shows an embodiment in which the opening 160/package assembly 166 extends to the package substrate 300, and fig. 20F shows an embodiment in which the opening 160/package assembly 166 extends through the package substrate 300.

Fig. 19-20F illustrate integrated circuit dies 50 electrically interconnected by interposer 500. In other embodiments, interposer 500 may be replaced with another fan-out structure. For example, fig. 21-23F illustrate a first package assembly 100 "in accordance with some embodiments, wherein the fan-out structure is a redistribution structure 600. According to some embodiments, the first package assembly 100″ may be combined with other package assemblies (e.g., package substrate 300) to provide a semiconductor package 650, 660, or 670. Packages 650, 660, and 670 may be substantially similar to packages 550, 560, and 570, respectively, unless otherwise indicated, wherein like reference numerals designate like elements formed by like processes. However, in the packages 650, 660, and 670, the first package assembly 100″ has a different configuration from the package assemblies of the packages 550, 560, and 570. Specifically, the package assembly 100 "includes integrated circuit dies bonded to the redistribution structure 600 and electrically interconnected by the redistribution structure 600, and then the package assembly 100" is bonded to the package substrate 300 in a chip-on-wafer-on-redistribution-R (CoWoS-R) configuration on the substrate.

Referring first to fig. 21, a redistribution structure 600 may be formed on the release layer 104 over the carrier substrate 102. The redistribution structure 600 may include metallization patterns 604, 610, and 612 and dielectric layers 602, 606, and 608. The redistribution structure may be formed from materials and processes similar to the redistribution structure 122 described above (see fig. 16A and 16B). Specifically, each of the metallization patterns 604, 610, and 612 may be made of similar materials and processes as the metallization pattern 126, and each of the dielectric layers 602, 606, and 608 may be made of similar materials and processes as the dielectric layer 124. In some embodiments, the metallization pattern 612 may provide UBM for the redistribution structure 600.

In fig. 22, the integrated circuit die 50 is attached to the redistribution structure 600 with solder bonding (e.g., conductive connections 614 on UBM 616 of the integrated circuit die 50). The integrated circuit die 50 may be placed on the redistribution structure 600 using, for example, a pick-and-place tool. Conductive connection 614 may be formed from similar materials and similar methods as described above with respect to conductive connection 152 (see fig. 16A and 16B), and UBM 616 may be formed from similar materials and similar methods as described above with respect to UBM 514. Attaching the integrated circuit die 50 to the redistribution structure 600 may include placing the integrated circuit die 50 on the redistribution structure 600 and reflowing the conductive connections 614. The conductive connection 614 forms a joint between UBM 616 of the redistribution structure 600 and UBM 616 of the integrated circuit die 50, thereby electrically connecting the redistribution structure 600 to the integrated circuit die 50.

An underfill 620 may be formed around the conductive connections 614 between the redistribution structure 600 and the integrated circuit die 50. The underfill 620 may reduce stress and protect the joint created by the reflow of the conductive connection 614. The underfill 620 may be formed from similar materials and similar methods as described above with respect to the underfill 308. An encapsulant 120 may then be formed around the integrated circuit die 50 and the underfill 620 over the redistribution structure 600.

The dicing process is performed by dicing along scribe line regions of the redistribution structure 600. The cutting process may include sawing, cutting, and the like. For example, the dicing process may include sawing the encapsulant 120 and the redistribution structure 600. The dicing process separates each package 100 "from adjacent packages 100". The dicing process forms the redistribution structure 600 from the diced portions of the wafer. As a result of the dicing process, the outer sidewalls of the redistribution structure 600 and the encapsulant 120 are laterally co-terminal (within process variations). Further, in plan view, the encapsulant 120 may completely surround the integrated circuit die 50.

Conductive connection 622 and UBM 624 are formed extending through dielectric layer 602 to contact metallization pattern 604. An opening is formed through the dielectric layer 602 to expose a portion of the metallization pattern 604. The openings may be formed, for example, using laser drilling, etching, and the like. Conductive connection 622/UBM 625 is formed in the opening. Conductive connection 622/UBM 624 may be formed from similar materials and similar methods as described above with respect to conductive connection 150/UBM 514 (see fig. 16A and 16B).

The first package assembly 100 "is then attached to the package substrate 300 by flip chip bonding using the conductive connections 622. The underfill 308 may be formed around the conductive connection 622 between the first package assembly 100 "and the package substrate 300, and the opening 160 may be formed through the package 100", thereby completing the formation of the integrated circuit package. The openings 160 may have any of the configurations described above with respect to fig. 15A-15T and/or be formed by any process. Fig. 23A and 23B illustrate an exemplary completed semiconductor package 650 having an opening 160 according to some embodiments. In some embodiments, as shown in fig. 23A, the opening 160 may extend through the first package assembly 100 "and the underfill 308 to the top surface of the package substrate 300. In some embodiments, as shown in fig. 23B, the opening 160 may also extend through the package substrate 300 in addition to the first package assembly 100 ". Fig. 23C and 23D illustrate an exemplary completed semiconductor package 660 having an opening 160 according to some embodiments. In the package 660, the bracket 162 may be placed in the opening 160 to provide additional structural support. Fig. 23C shows an embodiment in which the opening 160/bracket 162 extends to the package substrate 300, and fig. 23D shows an embodiment in which the opening 160/bracket 162 extends through the package substrate 300. Fig. 23E and 23F illustrate an exemplary completed semiconductor package 670 with openings 160 in accordance with some embodiments. In the package 670, a package assembly 166 (e.g., high thermal conductivity material/assembly, EMI shielding material/assembly, combinations thereof, etc.) may be placed in the opening 160. Fig. 23E shows an embodiment in which the opening 160/package assembly 166 extends to the package substrate 300, and fig. 23F shows an embodiment in which the opening 160/package assembly 166 extends through the package substrate 300.

Fig. 19-23F illustrate individual integrated circuit dies 50 electrically interconnected by an interposer 500 or redistribution structure 600. In other embodiments, the interposer 500/redistribution structure may be replaced with another fan-out structure. For example, fig. 24-25F illustrate a first package assembly 100' "according to some embodiments, wherein the fan-out structure includes an LSI die (sometimes referred to as a bridge die). According to some embodiments, the first package assembly 100' "may be combined with other package components (e.g., package substrate 300) to provide a semiconductor package 750, 760, or 770. Packages 750, 760, and 770 may be substantially similar to packages 550, 560, and 570, respectively, unless otherwise indicated, wherein like reference numerals represent like elements formed by like processes. However, in the packages 750, 760, and 770, the first package assembly 100' "has a different configuration from the package assemblies of the packages 550, 560, and 570. Specifically, the package assembly 100 '"includes integrated circuit dies bonded and electrically interconnected by LSI dies, and then the package assembly 100'" is bonded to the package substrate 300 in a chip-on-wafer-on-substrate-less silicon substrate (CoWoS-L) configuration.

Referring first to fig. 24, a fan-out structure 700 is shown. The fan-out structure 700 may include an LSI die 702 packaged in an encapsulant 704 having through-holes 706. LSI die 702 may be formed of similar materials using similar processes as integrated circuit die 50. However, the LSI die 702 may be devoid of any active device and may also include TSVs 708 that provide electrical connection between the back side and the front side of the silicon substrate of the LSI die 702. The encapsulant 704 and the through-holes 706 may be formed of similar materials using a similar process as the encapsulant 120 and the through-holes 116, respectively (see fig. 16A and 16B). LSI die 702 may be electrically connected to redistribution structure 718, and redistribution structure 718 may be formed of a similar material using a similar process as front-side redistribution structure 122 described above (see fig. 16A and 16B). The redistribution structure 718 may further include UBM 724 and conductive connection 722. In some embodiments, conductive connection 722 may be formed from a similar material using a similar process to conductive connection 152 (see fig. 16A and 16B), and UBM 724 may be formed from a similar material using a similar process to UBM 514.

In fig. 24, integrated circuit die 50 is attached to fan-out structure 700 with solder bonding (e.g., conductive connections 712 on UBM 716 of integrated circuit die 50). The integrated circuit die 50 may be placed on the fan-out structure 700 using, for example, a pick-and-place tool. Conductive connection 712 may be formed from similar materials and similar methods as described above with respect to conductive connection 152 (see fig. 16A and 16B), and UBM 716 may be formed from similar materials and similar methods as described above with respect to UBM 514. Attaching the integrated circuit die 50 to the fan-out structure 700 may include placing the integrated circuit die 50 on the fan-out structure 700 and reflowing the conductive connection 712. Conductive connection 712 forms a joint between UBM 714 of fan-out structure 700 and UBM 716 of integrated circuit die 50, thereby electrically connecting fan-out structure 700 to integrated circuit die 50.LSI die 702 may include circuitry that provides routing between integrated circuit dies 50, and through vias 706/redistribution structures 718 may provide additional routing from integrated circuit die/LSI die 702 to conductive connections 722. UBM 716 may be formed of similar materials and similar methods as described above with respect to UBM 514, and UBM 716 may be formed directly over through-hole 706 in encapsulant 704 and TSV 708 of LSI die 702.

Next in fig. 25A to 25E, an underfill 730 may be formed around the conductive connection 712. The underfill 730 may reduce stress and protect the joint created by the reflow of the conductive connection 712. Underfill 730 may be formed in a similar manner and by a similar method as described above with respect to underfill 308. The encapsulant 120 may then be formed around the integrated circuit die 50 and the underfill 730 over the LSI die 702 and the encapsulant 704.

The dicing process is performed by dicing along scribe line areas of the fan-out structure 700. The cutting process may include sawing, cutting, and the like. For example, the dicing process may include sawing the encapsulant 120 and the fan-out structure 700. The dicing process divides each package 100 '"from an adjacent package 100'". The dicing process forms the fan-out structures 700 from the diced portions of the wafer. As a result of the dicing process, the outer sidewalls of the fan-out structure 700 and the encapsulant 120 are laterally co-terminal (within process variations). Further, in plan view, the encapsulant 120 may completely surround the integrated circuit die 50.

The first package assembly 100' "is then attached to the package substrate 300 by flip-chip bonding using the conductive connection 722. The underfill 308 may be formed around the conductive connection 722 between the first package assembly 100 '"and the package substrate 300, and the opening 160 may be formed through the package 100'" to complete the formation of the integrated circuit package. The openings 160 may have any of the configurations described above with respect to fig. 15A-15T and/or be formed by any process. In some embodiments, the opening 160 may be placed around the periphery of the integrated circuit die 50 to avoid the LSI die 702. Fig. 25A and 25B illustrate an exemplary completed semiconductor package 750 with openings 160 according to some embodiments. In some embodiments, as shown in fig. 25A, the opening 160 may extend through the first package assembly 100' "and the underfill 308 to the top surface of the package substrate 300. In some embodiments, as shown in fig. 25B, the opening 160 may extend through the package substrate 300 in addition to the first package assembly 100' ". Fig. 25C and 25D illustrate an exemplary completed semiconductor package 760 with openings 160 according to some embodiments. In package 760, bracket 162 may be placed in opening 160 for additional structural support. Fig. 25C shows an embodiment in which the opening 160/bracket 162 extends to the package substrate 300, and fig. 25D shows an embodiment in which the opening 160/bracket 162 extends through the package substrate 300. Fig. 25E and 25F illustrate an exemplary completed semiconductor package 770 having an opening 160 according to some embodiments. In the package 770, a package component 166 (e.g., a high thermal conductivity material/component, an EMI shielding material/component combination, etc.) may be placed in the opening 160. Fig. 25E illustrates an embodiment in which the opening 160/package assembly 166 extends to the package substrate 300, and fig. 25F illustrates an embodiment in which the opening 160/package assembly 166 extends through the package substrate 300.

According to some embodiments, one or more integrated circuit dies are electrically connected by a fan-out structure (e.g., a redistribution structure, interposer, local Silicon Interconnect (LSI), etc.), and the integrated circuit dies may be encapsulated for further packaging with other packaging components (e.g., a package substrate, etc.). One or more openings may be formed in the molding compound and/or the fan-out structure. The inclusion of the opening may facilitate heat dissipation from the semiconductor die through the opening. As another example, the opening may facilitate insertion of one or more beneficial components, such as heat dissipating components, electromagnetic interference (EMI) shielding, structural support (e.g., mechanical brackets), and the like. As a result, improved packaging performance and/or ease of manufacture may be achieved.

In some embodiments, a semiconductor package includes a first package assembly comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die; a fan-out structure electrically connected to the integrated circuit die, wherein the first opening extends completely through the fan-out structure and at least partially through the encapsulant in a cross-sectional view, and wherein the encapsulant at least completely surrounds the first opening. Open in a top down view. The semiconductor package further includes a package substrate bonded to the first package assembly. And (3) an assembly. Optionally, in some embodiments, the first opening extends completely through the first package assembly. Optionally, in some embodiments, the first opening extends completely through the package substrate. Optionally, in some embodiments, the second opening extends completely through the fan-out structure and at least partially through the encapsulant in a cross-sectional view, wherein the encapsulant only partially surrounds the second opening in a top view. Optionally, in some embodiments, the semiconductor package further comprises a standoff in the opening, wherein the standoff extends at least partially into the package substrate. Optionally, in some embodiments, the mechanical support extends completely through the package substrate. Optionally, in some embodiments, the fan-out structure comprises a redistribution structure. Optionally, in some embodiments, the fan-out structure includes an interposer. Optionally, in some embodiments, the fan-out structure comprises a Local Silicon Interconnect (LSI) die. Optionally, in some embodiments, the semiconductor package further comprises a via extending through the encapsulant.

In some embodiments, a semiconductor package includes a first package assembly comprising: a first integrated circuit die; a second integrated circuit die; an encapsulant surrounds the first integrated circuit die and the second integrated circuit die; a fan-out structure electrically connecting the first integrated circuit die to the second integrated circuit die; and an electrically conductive package assembly extending through the fan-out structure into the package body, wherein the electrically conductive package assembly is a high thermal conductivity element, an EMI shielding element, or a combination thereof. The semiconductor package further includes a package substrate bonded to the first package assembly. Optionally, in some embodiments, the conductive packaging component comprises copper or aluminum. Optionally, in some embodiments, the conductive encapsulation member extends only partially through the encapsulant. Optionally, in some embodiments, the conductive encapsulation member extends only entirely through the encapsulant.

In some embodiments, a method of manufacturing a semiconductor package includes forming a first package assembly, the forming the first package assembly including: packaging the integrated circuit die in a molding compound; forming a redistribution structure over the molding compound and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die; after forming the redistribution structure, openings extending through the redistribution structure into the encapsulant are patterned. The method also includes bonding the package substrate to the first package assembly. Optionally, in some embodiments, patterning the openings includes laser machining, mechanical drilling/routing, plasma etching/bombardment, or chemical etching. Optionally, in some embodiments, the method further comprises placing a mechanical mount in the opening, the mechanical mount securing the first package assembly to the package substrate. Optionally, in some embodiments, the method further comprises placing a package assembly in the opening, wherein the package assembly is a high thermal conductivity element, an EMI shielding element, or a combination thereof. Optionally, in some embodiments, a portion of the molding compound remains disposed directly below the opening after patterning the opening. Optionally, in some embodiments, patterning the opening includes patterning the opening with a molding compound.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising:

a first package assembly comprising:

an integrated circuit die;

an encapsulant surrounding the integrated circuit die; and

a fan-out structure electrically connected to the integrated circuit die, wherein, in a cross-sectional view, a first opening extends completely through the fan-out structure and at least partially through the encapsulant, and, in a top-down view, the encapsulant at least completely surrounds the first opening; and

a package substrate bonded to the first package assembly.

2. The semiconductor package of claim 1, wherein the first opening extends completely through the first package component.

3. The semiconductor package of claim 1, wherein the first opening extends completely through the package substrate.

4. The semiconductor package of claim 1, wherein in the cross-sectional view, a second opening extends completely through the fan-out structure and at least partially through the encapsulant, and in the top-down view, the encapsulant only partially surrounds the second opening.

5. A semiconductor package, comprising:

a first package assembly comprising:

a first integrated circuit die;

a second integrated circuit die;

an encapsulant surrounding the first and second integrated circuit dies;

a fan-out structure electrically connecting the first integrated circuit die to the second integrated circuit die;

an electrically conductive package assembly extending through the fan-out structure to the encapsulant, wherein the electrically conductive package assembly is a high thermal conductivity element, an EMI shielding element, or a combination thereof; and

a package substrate bonded to the first package assembly.

6. The semiconductor package of claim 5, wherein the conductive package assembly comprises copper or aluminum.

7. A method of manufacturing a semiconductor package, the method comprising:

forming a first package assembly, the forming the first package assembly comprising:

encapsulating the integrated circuit die in a molding compound;

forming a redistribution structure over the molding compound and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die;

patterning openings extending through the redistribution structure into the encapsulant after forming the redistribution structure; and

a package substrate is bonded to the first package assembly.

8. The method of claim 7, wherein patterning the opening comprises laser machining, mechanical drilling/routing, plasma etching/bombardment, or chemical etching.

9. The method of claim 7, further comprising: a mechanical mount is placed in the opening, the mechanical mount securing the first package component to the package substrate.

10. The method of claim 7, further comprising: a package assembly is placed in the opening, wherein the package assembly is a high thermal conductivity element, an EMI shielding element, or a combination thereof.