TWI578483B - Package-on-package assembly having through assembly vias of different sizes - Google Patents

Package-on-package assembly having through assembly vias of different sizes Download PDF

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Publication number
TWI578483B
TWI578483B TW105104841A TW105104841A TWI578483B TW I578483 B TWI578483 B TW I578483B TW 105104841 A TW105104841 A TW 105104841A TW 105104841 A TW105104841 A TW 105104841A TW I578483 B TWI578483 B TW I578483B
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TW
Taiwan
Prior art keywords
package
die
vias
molding
carrier
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Application number
TW105104841A
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Chinese (zh)
Other versions
TW201725687A (en
Inventor
施信益
吳鐵將
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美光科技公司
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Publication of TWI578483B publication Critical patent/TWI578483B/en
Publication of TW201725687A publication Critical patent/TW201725687A/en

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

包含不同尺寸的封裝穿孔的封裝上封裝構件Package-on-package component comprising package perforations of different sizes

本發明概括而言係關於半導體封裝領域,特別係關於一種包含不同尺寸的封裝穿孔的封裝上封裝構件,可用來將不同功能的晶片封裝至一封裝體中。SUMMARY OF THE INVENTION The present invention generally relates to the field of semiconductor packaging, and more particularly to an package-on-package component comprising package vias of different sizes that can be used to package different functional wafers into a package.

隨著日新月異的半導體製造技術,微電子組件的尺寸越來越小,其中的電路也越來越密集。為了進一步縮小尺寸,安裝在電路板的微電子組件封裝結構也必須更加緊密。With the ever-changing semiconductor manufacturing technology, the size of microelectronic components is getting smaller and smaller, and the circuits are becoming more and more dense. In order to further reduce the size, the microelectronic component package structure mounted on the circuit board must also be more compact.

3D封裝技術,例如封裝上封裝技術,可製作出具有較高集程度以及較緊密封裝接腳的封裝構件。一般而言,封裝上封裝構件包含一個位於頂部的半導體晶粒封裝體,接合到另一個位於底部的晶粒封裝體。習知的封裝上封裝構件,多是藉由位於周圍的錫球或穿模通孔,使頂部封裝體和底部封裝體電連接。3D packaging technologies, such as package-on-package technology, enable the fabrication of packaged components with higher levels of assembly and tighter package footprints. In general, the package-on-package component includes a semiconductor die package on top that is bonded to another die package at the bottom. Conventional package-on-package components are mostly electrically connected to the top package and the bottom package by surrounding solder balls or through-holes.

然而,習知的封裝上封裝構件,無法實現極緊密的堆疊結構。另外,習知的封裝上封裝構件體積較大並且容易發生翹曲的問題。因此,本技術領域仍要一個改良的封裝上封裝構件,包含利用不同尺寸的封裝穿孔,將不同功能的晶片安裝在一起,形成一個具有較緊密堆疊結構的封裝體。However, conventional packaged components on a package cannot achieve an extremely compact stack structure. In addition, the conventional packaged package has a large volume and is prone to warpage. Accordingly, there remains a need in the art for an improved package-on-package component that includes mounting differently sized wafers with different sized package vias to form a package having a tighter stack structure.

本發明主要目的為提供一改良的封裝上封裝構件,其中包含不同尺寸的通孔結構。SUMMARY OF THE INVENTION A primary object of the present invention is to provide an improved package-on-package component that includes through-hole structures of different sizes.

本發明一方面提供一種封裝上封裝構件,包含一底部封裝以及一疊設於該底部封裝上的頂部封裝。底部封裝包含一重佈線層結構,其中該重佈線層結構具有一第一面及相對該第一面的一第二面;至少一晶粒,設於該第一面上;一成型模料,設於該第一面並包覆該晶粒;複數個穿矽通孔,位於該晶粒中;複數個穿模通孔,設於一週邊區域且貫穿該第一面上的該成型模料,其中各該穿模通孔的孔徑大於各該穿矽通孔的孔徑。複數個焊錫凸塊或錫球,設於該第二面上。頂部封裝是經由該穿矽通孔(TSVs)與該穿模通孔(TMVs)與該底部封裝電連接。One aspect of the present invention provides a package-on-package component including a bottom package and a top package stacked on the bottom package. The bottom package includes a redistribution layer structure, wherein the redistribution layer structure has a first surface and a second surface opposite to the first surface; at least one die is disposed on the first surface; Forming the die on the first side; a plurality of through-holes are located in the die; a plurality of through-vias, the molding die disposed in a peripheral region and penetrating the first face, The aperture of each of the through-holes is larger than the aperture of each of the through-holes. A plurality of solder bumps or solder balls are disposed on the second surface. The top package is electrically connected to the bottom package via the through vias (TSVs) and the through vias (TMVs).

本發明另一方面提供一種重佈線層先製(RDL-first)的半導體元件製作方法,其中包含提供一載板,並於於該載板上形成一重佈線層結構。接著,於該重佈線層結構上形成一鈍化層。接著,在該重佈線層結構上形成凸塊,並於該重佈線層結構上安置一晶粒。該晶粒包含複數個穿矽通孔(TSVs),且該晶粒係透過該凸塊與該重佈線層結構電連接。接著,以一成型模料模封該晶粒,並研磨該成型模料與該晶粒,以顯露出各該穿矽通孔的一端面。接著,在該晶粒周圍的該成型模料中形成複數個穿模通孔(TMVs)。Another aspect of the present invention provides a method of fabricating a rewiring layer (RDL-first) semiconductor device, comprising: providing a carrier, and forming a redistribution layer structure on the carrier. Next, a passivation layer is formed on the redistribution layer structure. Next, a bump is formed on the redistribution layer structure, and a die is disposed on the redistribution layer structure. The die includes a plurality of through vias (TSVs) through which the die is electrically connected to the redistribution layer structure. Next, the die is molded with a molding die, and the molding die and the die are ground to reveal an end surface of each of the through holes. Next, a plurality of through-via vias (TMVs) are formed in the molding compound around the die.

本發明再另一方面提供一種晶片先製(chip-first)的半導體元件製作方法,其中包含提供一載板,於該第一載板上設置一晶粒,其中該晶粒包含複數個穿矽通孔。接著,以一成型模料模封該晶粒,並於該晶粒的一主動面上及該成型模料表面上形成一重佈線層結構。然後,於該重佈線層結構上形成一防銲層,並於該重佈線層結構上形成複數個焊錫凸塊或錫球。使該複數個焊錫凸塊或錫球貼合置一第二載板後,研磨該成型模料與該晶粒,以顯露出各該穿矽通孔的一端面。接著,在該晶粒周圍的該成型模料中形成複數個穿模通孔。According to still another aspect of the present invention, a chip-first semiconductor device manufacturing method includes providing a carrier on which a die is disposed, wherein the die includes a plurality of vias Through hole. Next, the die is molded with a molding die, and a redistribution layer structure is formed on an active surface of the die and the surface of the molding die. Then, a solder resist layer is formed on the redistribution layer structure, and a plurality of solder bumps or solder balls are formed on the redistribution layer structure. After the plurality of solder bumps or solder balls are placed on the second carrier, the molding compound and the crystal grains are ground to expose an end surface of each of the through holes. Next, a plurality of through-holes are formed in the molding die around the die.

無庸置疑的,該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後,均可了解本發明的目的。It will be apparent to those skilled in the art that the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

接下來的詳細敘述須參照相關圖式所示內容,用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節,可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內,可做結構、邏輯和電性上的修改應用在其他實施例上。The detailed description that follows is to be understood by reference to the accompanying drawings, These embodiments provide sufficient detail to enable those skilled in the art to fully understand and practice the invention. Structural, logical, and electrical modifications may be applied to other embodiments without departing from the scope of the invention.

因此,接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者,也應屬本發明涵蓋的範圍。Therefore, the following detailed description is not to be construed as limiting. The scope of the invention is defined by the claims. It is also within the scope of the present invention to have the same meaning as the claims of the present invention.

下面的描述須參照相關附圖內容以便徹底理解本發明,其中相同或類似的特徵通常以相同的附圖標記描述,描述的結構並不必然按比例繪製。The invention is described with reference to the accompanying drawings, in which the same or similar features are generally described with the same reference numerals, and the structures are not necessarily drawn to scale.

在本說明書中,“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意,可交替使用。In the present specification, "die", "semiconductor wafer" and "semiconductor die" have the same meaning and may be used interchangeably.

在本說明書中,“晶圓”、“基板”和“載板”意指任何包含一暴露面,可依據本發明實施例所示在其上沉積材料,製作積體電路結構的結構物,例如重佈線層。須了解的是“基板” 和“載板”包含半導體晶圓,但並不限於此。"基板"和“載板”在製程中也意指包含製作於其上的材料層的半導體結構物。In the present specification, "wafer", "substrate" and "carrier" mean any structure including an exposed surface on which a material can be deposited according to an embodiment of the present invention to fabricate an integrated circuit structure, for example. Redistribution layer. It should be understood that the "substrate" and "carrier" include semiconductor wafers, but are not limited thereto. "Substrate" and "carrier" are also used in the process to mean a semiconductor structure comprising a layer of material fabricated thereon.

首先,請參考第1圖和第2圖。第1圖為根據本發明一實施例的封裝上封裝構件1的示意性剖面圖,其中包含不同大小的封裝穿孔(TAVs)100。第2圖為第1圖所示實施例的封裝上封裝構件的封裝穿孔(TAVs)的設置和佈局的示意圖。First, please refer to Figure 1 and Figure 2. 1 is a schematic cross-sectional view of a package-on-package component 1 in accordance with an embodiment of the present invention, including package vias (TAVs) 100 of different sizes. Fig. 2 is a schematic view showing the arrangement and layout of package vias (TAVs) of the package-on-package members of the embodiment shown in Fig. 1.

如第1圖和第2圖所示,封裝上封裝構件1包含一底部封裝10以及一疊設於底部封裝10上的頂部封裝20。底部封裝10包含重佈線層結構400。重佈線層結構400包含第一面400a及相對於第一面400a的第二面400b。重佈線層結構400包含介電層412,以及位於介電層412中的至少一層金屬層414。介電層412可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者,但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似者,但不限於此。須了解的是,圖中所示金屬層414的配置和疊層僅為便於說明和描述的目的,並非本發明的限制。重佈線層結構400可另包含鈍化層413和鈍化層415。可選擇性的在鈍化層415上設置防焊層419。As shown in FIGS. 1 and 2, the package upper package member 1 includes a bottom package 10 and a top package 20 stacked on the bottom package 10. The bottom package 10 includes a redistribution layer structure 400. The redistribution layer structure 400 includes a first face 400a and a second face 400b relative to the first face 400a. The redistribution layer structure 400 includes a dielectric layer 412 and at least one metal layer 414 located in the dielectric layer 412. The dielectric layer 412 may comprise an organic material such as polyimide (PI), or an inorganic material such as tantalum nitride, hafnium oxide or the like, but is not limited thereto. The metal layer 414 may include aluminum, copper, tungsten, titanium, titanium nitride, or the like, but is not limited thereto. It is to be understood that the configuration and lamination of the metal layer 414 shown in the figures is for purposes of illustration and description only and is not a limitation of the invention. The redistribution layer structure 400 may further include a passivation layer 413 and a passivation layer 415. A solder resist layer 419 may be selectively disposed on the passivation layer 415.

半導體晶粒(晶粒)420安裝在重佈線層結構400第一面400a的晶片安裝區201內。晶粒420包含一直接面向重佈線層結構400的主動面420a。複數個凸塊(或微凸塊)104設置在主動面420a以及重佈線層結構400之間,用來將晶粒420與重佈線層結構400電連接。晶粒420中包含複數個穿矽通孔(TSVs)110,延伸於晶粒420的主動面420a與暴露的下表面420c 之間。穿矽通孔110可由習知的製程步驟製作。穿矽通孔110可沿著晶粒420的邊緣設置,但並不限於此。A semiconductor die (die) 420 is mounted within the wafer mounting region 201 of the first face 400a of the redistribution layer structure 400. The die 420 includes an active face 420a that directly faces the redistribution layer structure 400. A plurality of bumps (or microbumps) 104 are disposed between the active surface 420a and the redistribution layer structure 400 for electrically connecting the die 420 to the redistribution layer structure 400. The die 420 includes a plurality of through vias (TSVs) 110 extending between the active face 420a of the die 420 and the exposed lower surface 420c. The through-through vias 110 can be fabricated by conventional processing steps. The through-holes 110 may be disposed along the edges of the die 420, but are not limited thereto.

晶粒420的主動面420a上可包含複數個輸入/輸出(I/O)接墊(圖未示),分別與對應的凸塊104對準。雖然圖中並未特別標示,但該領域的技術人員應可理解在輸入/輸出接墊上可設有凸塊或柱狀體,例如銅柱。雖然第1圖中的底部封裝10僅繪示一個晶粒420,但在其他實施例中,也可包含複數個晶粒。The active surface 420a of the die 420 can include a plurality of input/output (I/O) pads (not shown) that are respectively aligned with the corresponding bumps 104. Although not specifically shown in the drawings, those skilled in the art will appreciate that bumps or posts, such as copper posts, may be provided on the input/output pads. Although the bottom package 10 in FIG. 1 shows only one die 420, in other embodiments, a plurality of crystal grains may be included.

成型模料500設於第一面400a上,包覆晶粒420並覆蓋住重佈線層結構400。根據本發明一實施例,可藉由一固化製程(curing process)使成型模料500固化。根據本發明一實施例,成型模料500可包含環氧樹脂(epoxy)和矽石填充物(silica fillers),但不限於此。晶粒420的下表面420c與成型模料500的上表面齊平。The molding die 500 is disposed on the first face 400a to cover the die 420 and cover the heavy wiring layer structure 400. According to an embodiment of the invention, the molding die 500 can be cured by a curing process. According to an embodiment of the present invention, the molding die 500 may include epoxy and silica fillers, but is not limited thereto. The lower surface 420c of the die 420 is flush with the upper surface of the molding die 500.

底部封裝10的週邊區域202中可包含複數個穿模通孔(TMVs)210。週邊區域202鄰近晶片安裝區201。穿模通孔210可沿著晶粒420的周圍排列,但不限於此。穿模通孔210貫穿成型模料500以及鈍化層413,與重佈線層結構400的金屬層414電連接。根據本發明一實施例,穿矽通孔110具有孔徑r 1,r 1小於穿模通孔210的孔徑r 2。在下文中,可將穿矽通孔110與穿模通孔210通稱為封裝穿孔(through assembly vias, TAVs) 100。 A plurality of through-mold vias (TMVs) 210 may be included in the peripheral region 202 of the bottom package 10. The peripheral region 202 is adjacent to the wafer mounting region 201. The die through holes 210 may be arranged along the circumference of the die 420, but are not limited thereto. The through via 210 penetrates the molding die 500 and the passivation layer 413 to be electrically connected to the metal layer 414 of the redistribution layer structure 400. According to an embodiment of the present invention, through silicon vias 110 having a pore diameter r 1, r 1 is less than the aperture through the through hole 210 of the die r 2. Hereinafter, the through-holes 110 and the through-holes 210 may be referred to as through assembly vias (TAVs) 100.

根據本發明一實施例,穿矽通孔110可用來傳遞信號,例如高頻的信號或類似者。穿模通孔210可用來傳遞功率或接地信號,但不限於此。According to an embodiment of the invention, the through-via vias 110 can be used to deliver signals, such as high frequency signals or the like. The die through via 210 can be used to transfer power or ground signals, but is not limited thereto.

在一些實施例中,穿模通孔210可以僅沿著晶粒420的邊緣420b的其中三邊設置。例如第3圖所示實施例,底部封裝10a的成型模料500中,包含兩個並排的晶粒,分別是晶粒420’以及晶粒420”。穿模通孔210可沿著底部封裝10a的週邊區域設置。第3圖中,穿模通孔210僅沿著晶粒420’以及晶粒420”個別的邊緣420b的其中三邊設置。須了解的是,第3圖所示的穿模通孔210的設置方式僅為說明和描述的目的,並非本發明的限制。穿模通孔210的配置與佈局須根據實際設計上的需求。In some embodiments, the through vias 210 may be disposed along only three of the edges 420b of the die 420. For example, in the embodiment shown in FIG. 3, the molding die 500 of the bottom package 10a includes two side-by-side crystal grains, which are respectively a die 420' and a die 420". The die-through via 210 may be along the bottom package 10a. Peripheral area setting. In Fig. 3, the through-mold via 210 is disposed only along three sides of the die 420' and the individual edges 420b of the die 420". It should be understood that the manner in which the through-holes 210 are shown in FIG. 3 is for illustrative purposes only and is not a limitation of the present invention. The configuration and layout of the through-holes 210 must be based on actual design requirements.

回到第1圖。頂部封裝20分別藉由焊錫凸塊(或錫球)250a和250b,與對應的穿矽通孔110和穿模通孔210電性連接。根據本發明一實施例,焊錫凸塊(或錫球)250a是與穿矽通孔110對準,焊錫凸塊(或錫球)250b是與穿模通孔210對準。頂部封裝20可包含一已模封的半導體晶片220。Go back to Figure 1. The top package 20 is electrically connected to the corresponding through vias 110 and through vias 210 by solder bumps (or solder balls) 250a and 250b, respectively. In accordance with an embodiment of the invention, the solder bumps (or solder balls) 250a are aligned with the through vias 110, and the solder bumps (or solder balls) 250b are aligned with the through vias 210. The top package 20 can include a molded semiconductor wafer 220.

請參考第4圖至第11圖,為根據本發明一實施例的製作方法的示意性剖面圖,可製得如第1圖所示,包含不同大小的封裝穿孔(TAVs)的封裝上封裝構件。Referring to FIG. 4 to FIG. 11 , which are schematic cross-sectional views showing a fabrication method according to an embodiment of the present invention, an package-on-package component including package vias (TAVs) of different sizes as shown in FIG. 1 can be obtained. .

首先,如第4圖所示,提供一預備好的載板300。載板300可為包含黏著層302的可卸式的基底材料,但不限於此。First, as shown in Fig. 4, a prepared carrier 300 is provided. The carrier 300 may be a detachable base material including the adhesive layer 302, but is not limited thereto.

接著,在載板300上形成重佈線層結構400。載板300的上表面形成至少一介電層或鈍化層415。鈍化層415可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者。Next, a redistribution layer structure 400 is formed on the carrier 300. At least one dielectric layer or passivation layer 415 is formed on the upper surface of the carrier 300. The passivation layer 415 may comprise an organic material such as polyimide (PI), or an inorganic material such as tantalum nitride, hafnium oxide or the like.

然後,在鈍化層415上形成至少一層介電層412和一層金屬層414。介電層412可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者,但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似者。根據本發明一實施例,金屬層414包含複數個自介電層412的上表面暴露出來的焊墊414a。Then, at least one dielectric layer 412 and one metal layer 414 are formed on the passivation layer 415. The dielectric layer 412 may comprise an organic material such as polyimide (PI), or an inorganic material such as tantalum nitride, hafnium oxide or the like, but is not limited thereto. Metal layer 414 can comprise aluminum, copper, tungsten, titanium, titanium nitride, or the like. In accordance with an embodiment of the invention, metal layer 414 includes a plurality of pads 414a exposed from the upper surface of self-dielectric layer 412.

然後,形成鈍化層413。鈍化層413覆蓋住介電層412和焊墊414a。鈍化層413可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者。Then, a passivation layer 413 is formed. The passivation layer 413 covers the dielectric layer 412 and the pad 414a. The passivation layer 413 may comprise an organic material such as polyimide (PI), or an inorganic material such as tantalum nitride, hafnium oxide or the like.

如第5圖所示,接著可在鈍化層413中形成開孔(圖未示),使個別的焊墊414a暴露出來。可利用例如習知的焊錫凸塊電鍍法,在暴露出來的個別的焊墊414a上形成凸塊416a,然後將覆晶晶片或晶粒420以主動面420a朝下面向重佈線層結構400的方位安裝至凸塊416a上,形成晶片對晶圓(chip-to-wafer, C2P)接合的堆疊結構。As shown in Fig. 5, openings (not shown) may then be formed in the passivation layer 413 to expose the individual pads 414a. The bumps 416a may be formed on the exposed individual pads 414a using, for example, conventional solder bump plating, and then the flip chip or die 420 may be oriented with the active surface 420a facing downward toward the redistribution layer structure 400. Mounted onto the bumps 416a to form a chip-to-wafer (C2P) bonded stack structure.

晶粒420的主動面420a上可包含複數個輸入/輸出(I/O)接墊421。輸入/輸出接墊421與凸塊416a對準。晶粒420可為具特定功能的主動積體電路晶片,例如,繪圖處理器(GPUs)、中央處理器(CPUs),記憶體晶片等,但不限於此。雖然未繪示於圖中,但熟習本領域技術者應可理解,可在輸入/輸出接墊421上形成凸塊或銅柱體,以供後續連接使用。A plurality of input/output (I/O) pads 421 may be included on the active surface 420a of the die 420. The input/output pads 421 are aligned with the bumps 416a. The die 420 may be a specific integrated active circuit chip such as graphics processing units (GPUs), central processing units (CPUs), memory chips, etc., but is not limited thereto. Although not shown in the drawings, it will be understood by those skilled in the art that bumps or copper posts can be formed on the input/output pads 421 for subsequent connections.

根據本發明一實施例,每個晶粒420可包含沿著晶粒420邊緣設置的穿矽通孔(TSVs)110。穿矽通孔110可以是沿著晶粒420的四邊420b設置,但不限於此。例如,在一些實施例中,穿矽通孔110可以僅沿著晶粒420的四邊420b其中的三邊設置。In accordance with an embodiment of the invention, each die 420 may include through vias (TSVs) 110 disposed along edges of the die 420. The through-holes 110 may be disposed along the four sides 420b of the die 420, but are not limited thereto. For example, in some embodiments, the through vias 110 may be disposed along only three of the four sides 420b of the die 420.

如第6圖所示,接著塗佈成型模料500。成型模料500覆蓋住晶粒420。可藉由一固化製程(curing process)使成型模料500固化。根據本發明一實施例,成型模料500可包含環氧樹脂(epoxy)和矽石填充物(silica fillers),但不限於此。As shown in Fig. 6, the molding die 500 is then applied. The molding die 500 covers the die 420. The molding die 500 can be cured by a curing process. According to an embodiment of the present invention, the molding die 500 may include epoxy and silica fillers, but is not limited thereto.

如第7圖所示,接著可以用研磨的方法,移除部分成型模料500的頂部,使每一個晶粒420的下表面420c暴露出來。在研磨成型模料500的過程中,晶片420的一部分也會被移除掉,使每一個穿矽通孔110的一端面暴露出來。此時,暴露出來的晶粒420的下表面420c與成型模料500的上表面齊平。As shown in Fig. 7, the top portion of the partially formed molding material 500 may be removed by grinding to expose the lower surface 420c of each of the crystal grains 420. During the process of grinding the molding die 500, a portion of the wafer 420 is also removed, exposing one end surface of each of the through-holes 110. At this time, the lower surface 420c of the exposed crystal grains 420 is flush with the upper surface of the molding die 500.

如第8圖所示,接著可在成型模料500和鈍化層413中形成複數個開孔510,連通重佈線層結構400的金屬層414。根據本發明一實施例,可藉由雷射鑽孔的方式形成開孔510,但不限於此。可在開孔510中填入例如金屬層,形成穿模通孔(TMVs)210。As shown in FIG. 8, a plurality of openings 510 may be formed in the molding die 500 and the passivation layer 413 to connect the metal layer 414 of the redistribution layer structure 400. According to an embodiment of the invention, the opening 510 may be formed by laser drilling, but is not limited thereto. For example, a metal layer may be filled in the opening 510 to form through-via vias (TMVs) 210.

接下來,如第9圖和第10圖所示,移除載板300和黏著層302,使鈍化層415的一表面暴露出來。剝離載板300的方法可利用例如雷射剝離法、紫外光照射法、研磨法或蝕刻法,但不限於此。剝離載板300後,可在鈍化層415暴露出來的表面上形成防焊層419。接著,在鈍化層415和防焊層419中形成開孔(圖未示),暴露出位於金屬層414中個別的焊墊(solder pad)。然後,可在暴露的個別的焊墊上形成焊錫凸塊或錫球520,供後續連接使用。接著,如第10圖所示,切割由上述步驟而製得的晶圓級封裝,得到個別的底部封裝10。Next, as shown in FIGS. 9 and 10, the carrier 300 and the adhesive layer 302 are removed to expose a surface of the passivation layer 415. The method of peeling off the carrier 300 can be, for example, a laser lift-off method, an ultraviolet light irradiation method, a polishing method, or an etching method, but is not limited thereto. After the carrier 300 is peeled off, a solder resist layer 419 may be formed on the exposed surface of the passivation layer 415. Next, openings (not shown) are formed in the passivation layer 415 and the solder resist layer 419 to expose individual solder pads in the metal layer 414. Solder bumps or solder balls 520 can then be formed on the exposed individual pads for subsequent connections. Next, as shown in FIG. 10, the wafer level package obtained by the above steps is cut to obtain individual bottom packages 10.

如第11圖所示,將包含已模封的半導體晶粒220的頂部封裝20疊設至底部封裝10上。頂部封裝20分別藉由焊錫凸塊250a和250b,與對應的穿矽通孔110和穿模通孔210電連接。As shown in FIG. 11, the top package 20 including the encapsulated semiconductor die 220 is stacked on the bottom package 10. The top package 20 is electrically connected to the corresponding through vias 110 and through vias 210 by solder bumps 250a and 250b, respectively.

請參考第12圖至第18圖。第12圖至第18圖為根據本發明另一實施例的製作方法的示意性剖面圖,可製得包含不同大小的封裝穿孔(TAVs)的封裝上封裝構件。Please refer to Figures 12 to 18. 12 to 18 are schematic cross-sectional views showing a fabrication method according to another embodiment of the present invention, which can produce package-on-package members including package vias (TAVs) of different sizes.

如第12圖所示,同樣的,先提供一預備好的載板300。載板300可為包含黏著層302的可卸式的基底材料,但不限於此。接著,將晶粒420以主動面420a朝下面向載板300和下表面420c朝上的方位,安裝至載板300上。As shown in Fig. 12, similarly, a prepared carrier 300 is provided first. The carrier 300 may be a detachable base material including the adhesive layer 302, but is not limited thereto. Next, the die 420 is mounted on the carrier 300 with the active surface 420a facing downward toward the carrier 300 and the lower surface 420c.

晶粒420的主動面420a上可包含複數個輸入/輸出(I/O)接墊421。晶粒420可為具特定功能的主動積體電路晶片,例如,繪圖處理器(GPUs)、中央處理器(CPUs),記憶體晶片等,但不限於此。根據本發明一實施例,每個晶粒420可包含沿著晶粒420邊緣設置的穿矽通孔(TSVs)110。A plurality of input/output (I/O) pads 421 may be included on the active surface 420a of the die 420. The die 420 may be a specific integrated active circuit chip such as graphics processing units (GPUs), central processing units (CPUs), memory chips, etc., but is not limited thereto. In accordance with an embodiment of the invention, each die 420 may include through vias (TSVs) 110 disposed along edges of the die 420.

如第13圖所示,接著塗佈成型模料500。成型模料500覆蓋住晶粒420以及黏著層302的上表面。可藉由一固化製程(curing process)使成型模料500固化。根據本發明一實施例,成型模料500可包含環氧樹脂(epoxy)和矽石填充物(silica fillers),但不限於此。接下來,移除載板300和黏著層302。As shown in Fig. 13, the molding die 500 is then applied. The molding die 500 covers the die 420 and the upper surface of the adhesive layer 302. The molding die 500 can be cured by a curing process. According to an embodiment of the present invention, the molding die 500 may include epoxy and silica fillers, but is not limited thereto. Next, the carrier 300 and the adhesive layer 302 are removed.

如第14圖所示,接著在暴露出來的晶粒420的主動面420a以及成型模料500的表面上,形成重佈線層結構400。重佈線層結構400包含至少一介電層412和一金屬層414。介電層412可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者,但不限於此。屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似者。金屬層414與個別晶粒420的輸入/輸出(I/O)接墊421電連接。As shown in Fig. 14, a redistribution layer structure 400 is then formed on the exposed surface 420a of the exposed die 420 and the surface of the molding die 500. The redistribution layer structure 400 includes at least one dielectric layer 412 and a metal layer 414. The dielectric layer 412 may comprise an organic material such as polyimide (PI), or an inorganic material such as tantalum nitride, hafnium oxide or the like, but is not limited thereto. The genus layer 414 can comprise aluminum, copper, tungsten, titanium, titanium nitride, or the like. Metal layer 414 is electrically coupled to input/output (I/O) pads 421 of individual die 420.

接下來,在重佈線層結構400上形成防焊層419。可在防焊層419中形成開孔(圖未示),使金屬層414中的個別的焊墊(solder pad)暴露出來。可在暴露出來的個別的焊墊上形成焊錫凸塊或錫球520,供後續連接使用。Next, a solder resist layer 419 is formed on the redistribution layer structure 400. Openings (not shown) may be formed in the solder mask layer 419 to expose individual solder pads in the metal layer 414. Solder bumps or solder balls 520 may be formed on the exposed individual pads for subsequent connections.

然後,如第15圖所示,藉由黏著層602,將錫球520貼合至另一載板600上。Then, as shown in Fig. 15, the solder ball 520 is attached to the other carrier 600 by the adhesive layer 602.

如第16圖所示,利用研磨的方法,移除部分成型模料500的頂部以及部分晶粒420,使得穿矽通孔110的一端面自晶粒420的下表面420c暴露出來。接著,可在成型模料500中形成複數個開孔510,連通重佈線層結構400的金屬層414。根據本發明一實施例,開孔510可藉由雷射鑽孔的方式形成,但不限於此。接著,可在開孔510中填入例如金屬層,形成穿模通孔(TMVs)210。As shown in FIG. 16, the top portion of the part of the molding die 500 and a portion of the die 420 are removed by grinding, so that one end face of the through-hole 110 is exposed from the lower surface 420c of the die 420. Next, a plurality of openings 510 may be formed in the molding die 500 to connect the metal layer 414 of the redistribution layer structure 400. According to an embodiment of the invention, the opening 510 may be formed by laser drilling, but is not limited thereto. Next, a metal layer may be filled in the opening 510 to form through-vias (TMVs) 210.

接著,如第17圖和第18圖所示,在移除載板600和黏著層602後,切割由上述步驟製得的晶圓級封裝,得到個別的底部封裝10b。然後,將包含已模封的半導體晶粒220的頂部封裝20疊設至底部封裝10b上。頂部封裝20分別藉由焊錫凸塊250a和250b,與對應的穿矽通孔110和穿模通孔210電連接。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。Next, as shown in FIGS. 17 and 18, after the carrier 600 and the adhesive layer 602 are removed, the wafer level package obtained by the above steps is cut to obtain individual bottom packages 10b. Then, the top package 20 including the encapsulated semiconductor die 220 is stacked on the bottom package 10b. The top package 20 is electrically connected to the corresponding through vias 110 and through vias 210 by solder bumps 250a and 250b, respectively. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1‧‧‧封裝上封裝構件1‧‧‧Package components

10、10a‧‧‧底部封裝10, 10a‧‧‧ bottom package

20‧‧‧頂部封裝20‧‧‧Top package

100‧‧‧封裝穿孔100‧‧‧Packing perforations

104‧‧‧凸塊104‧‧‧Bumps

110‧‧‧穿矽通孔110‧‧‧through through hole

201‧‧‧晶片安裝區201‧‧‧ wafer mounting area

202‧‧‧週邊區域202‧‧‧ surrounding area

210‧‧‧穿模通孔210‧‧‧through hole

220‧‧‧半導體晶粒220‧‧‧Semiconductor grain

250a、250b‧‧‧焊錫凸塊250a, 250b‧‧‧ solder bumps

300‧‧‧載板300‧‧‧ Carrier Board

302‧‧‧黏著層302‧‧‧Adhesive layer

400‧‧‧重佈線層結構400‧‧‧Rewiring layer structure

400a‧‧‧第一面400a‧‧‧ first side

400b‧‧‧第二面400b‧‧‧ second side

412‧‧‧介電層412‧‧‧ dielectric layer

414‧‧‧金屬層414‧‧‧metal layer

413、415‧‧‧鈍化層413, 415‧‧‧ Passivation layer

414a‧‧‧焊墊414a‧‧‧ pads

416a‧‧‧凸塊416a‧‧‧Bumps

419‧‧‧防焊層419‧‧‧ solder mask

420、420'、420"‧‧‧晶粒420, 420', 420" ‧ ‧ granules

420a‧‧‧主動面420a‧‧‧ active surface

420b‧‧‧四邊420b‧‧‧ four sides

420c‧‧‧下表面420c‧‧‧ lower surface

421‧‧‧輸入/輸出(I/O)接墊421‧‧‧Input/Output (I/O) pads

500‧‧‧成型模料500‧‧‧ molding materials

510‧‧‧開孔510‧‧‧Opening

520‧‧‧錫球520‧‧‧ solder balls

600‧‧‧載板600‧‧‧ Carrier Board

602‧‧‧黏著層602‧‧‧Adhesive layer

r1、r2‧‧‧ 孔徑 r 1 , r 2 ‧‧‧ aperture

第1圖為示意性剖面圖,說明根據本發明一實施例的封裝上封裝構件。    第2圖為說明如第1圖所示實施例的封裝上封裝構件中的封裝穿孔(TAVs)的設置和佈局的示意圖。    第3圖為說明另一實施例的封裝上封裝構件中的封裝穿孔(TAVs)的設置和佈局的示意圖。    第4圖至第11圖為示意性剖面圖,說明根據本發明一實施例,製作如第1圖所示,包含不同大小的封裝穿孔(TAVs) 的封裝上封裝構件的方法。    第12圖至第18圖為示意性剖面圖,說明根據本發明另一實施例,製作包含不同大小的封裝穿孔(TAVs)的封裝上封裝構件的方法。1 is a schematic cross-sectional view illustrating a package-on-package member according to an embodiment of the present invention. Fig. 2 is a schematic view showing the arrangement and layout of package vias (TAVs) in the package-on-package member of the embodiment shown in Fig. 1. Fig. 3 is a schematic view showing the arrangement and layout of package vias (TAVs) in a package-on-package member of another embodiment. 4 through 11 are schematic cross-sectional views illustrating a method of fabricating package-on-package members including package vias (TAVs) of different sizes as shown in FIG. 1 in accordance with an embodiment of the present invention. 12 through 18 are schematic cross-sectional views illustrating a method of fabricating package-on-package members comprising package vias (TAVs) of different sizes in accordance with another embodiment of the present invention.

1‧‧‧封裝上封裝構件 1‧‧‧Package components

10‧‧‧底部封裝 10‧‧‧ bottom package

20‧‧‧頂部封裝 20‧‧‧Top package

100‧‧‧封裝穿孔 100‧‧‧Packing perforations

104‧‧‧凸塊 104‧‧‧Bumps

110‧‧‧穿矽通孔 110‧‧‧through through hole

201‧‧‧晶片安裝區 201‧‧‧ wafer mounting area

202‧‧‧週邊區域 202‧‧‧ surrounding area

210‧‧‧穿模通孔 210‧‧‧through hole

220‧‧‧半導體晶粒 220‧‧‧Semiconductor grain

250a、250b‧‧‧焊錫凸塊 250a, 250b‧‧‧ solder bumps

400‧‧‧重佈線層結構 400‧‧‧Rewiring layer structure

400a‧‧‧第一面 400a‧‧‧ first side

400b‧‧‧第二面 400b‧‧‧ second side

412‧‧‧介電層 412‧‧‧ dielectric layer

414‧‧‧金屬層 414‧‧‧metal layer

413、415‧‧‧鈍化層 413, 415‧‧‧ Passivation layer

419‧‧‧防焊層 419‧‧‧ solder mask

500‧‧‧成型模料 500‧‧‧ molding materials

520‧‧‧錫球 520‧‧‧ solder balls

420‧‧‧晶粒 420‧‧‧ grain

420a‧‧‧主動面 420a‧‧‧ active surface

420c‧‧‧下表面 420c‧‧‧ lower surface

Claims (5)

一種製作半導體元件的方法，包含：提供一第一載板；於該第一載板上設置一晶粒，其中該晶矽包含複數個穿矽通孔；以一成型模料模封該晶粒；於該晶粒的一主動面上及該成型模料表面上形成一重佈線層結構；於該重佈線層結構上形成一防銲層；於該重佈線層結構上形成複數個焊錫凸塊或錫球；使該複數個焊錫凸塊或錫球貼合置一第二載板；研磨該成型模料與該晶粒，以顯露出各該穿矽通孔的一端面；及在該晶粒周圍的該成型模料中形成複數個穿模通孔。 A method for fabricating a semiconductor device, comprising: providing a first carrier; disposing a die on the first carrier, wherein the wafer comprises a plurality of through vias; and molding the die with a molding compound Forming a redistribution layer structure on an active surface of the die and the surface of the molding die; forming a solder resist layer on the redistribution layer structure; forming a plurality of solder bumps on the redistribution layer structure or a solder ball; the plurality of solder bumps or solder balls are attached to a second carrier; the molding material and the crystal grains are ground to expose an end surface of each of the through holes; and A plurality of through-holes are formed in the surrounding molding compound. 如申請專利範圍第1項所述的製作半導體元件的方法，其中各該穿模通孔的孔徑係大於各該穿矽通孔的孔徑。 The method of fabricating a semiconductor device according to claim 1, wherein each of the through-holes has a larger aperture than the aperture of each of the through-holes. 如申請專利範圍第1項所述的製作半導體元件的方法，其中該複數個穿矽通孔係沿著該晶粒的邊緣設置。 The method of fabricating a semiconductor device according to claim 1, wherein the plurality of through vias are disposed along an edge of the die. 如申請專利範圍第1項所述的製作半導體元件的方法，其中在以該成型模料模封該晶粒之後，另包含：移除該第一載板。 The method of fabricating a semiconductor device according to claim 1, wherein after molding the die with the molding die, the method further comprises: removing the first carrier. 如申請專利範圍第1項所述的製作半導體元件的方法，其中在該晶粒 周圍的該成型模料中形成複數個穿模通孔係包含：於該成型模料中形成開孔，連通該重佈線層結構的一金屬層；及將金屬填入該開孔。 A method of fabricating a semiconductor device according to claim 1, wherein the crystal grain Forming a plurality of through-holes in the surrounding molding material includes: forming an opening in the molding die, connecting a metal layer of the redistribution layer structure; and filling a metal into the opening.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI722411B (en) * 2019-02-01 2021-03-21 南亞科技股份有限公司 Semiconductor package, semiconductor package stack and manufacturing method thereof

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10103038B1 (en) 2017-08-24 2018-10-16 Micron Technology, Inc. Thrumold post package with reverse build up hybrid additive structure
US20190067248A1 (en) * 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
KR101933425B1 (en) * 2017-11-30 2018-12-28 삼성전기 주식회사 Semiconductor package
US10651126B2 (en) * 2017-12-08 2020-05-12 Applied Materials, Inc. Methods and apparatus for wafer-level die bridge
US10867879B2 (en) * 2018-09-28 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
DE102018130035B4 (en) 2018-09-28 2020-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. PACKAGE AND PROCEDURE
CN110071084A (en) * 2019-04-11 2019-07-30 广东气派科技有限公司 A kind of two-sided welding encapsulating products and its assemble method
TWI697080B (en) * 2019-04-17 2020-06-21 力成科技股份有限公司 Chip package structure and manufacturing method thereof
CN110957291A (en) * 2019-12-18 2020-04-03 江苏中科智芯集成科技有限公司 Wafer-level double-sided fan-out structure and packaging method thereof
US11830851B2 (en) 2020-04-07 2023-11-28 Mediatek Inc. Semiconductor package structure
DE102021107982B4 (en) 2020-04-07 2024-02-22 Mediatek Inc. SEMICONDUCTOR PACKAGE STRUCTURE

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201349402A (en) * 2012-05-18 2013-12-01 Taiwan Semiconductor Mfg Semiconductor package and method for fabricating the same
US20140225246A1 (en) * 2013-02-13 2014-08-14 Qualcomm Incorporated Dual substrate, power distribution and thermal solution for direct stacked integrated devices
TW201545286A (en) * 2014-05-30 2015-12-01 Taiwan Semiconductor Mfg Ring structures in device die
US20150348940A1 (en) * 2014-05-28 2015-12-03 Invensas Corporation Structure and method for integrated circuits packaging with increased density

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148167B (en) * 2010-02-08 2013-03-27 日月光半导体制造股份有限公司 Method for manufacturing stackable packaging structure
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US9165887B2 (en) * 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9818734B2 (en) * 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201349402A (en) * 2012-05-18 2013-12-01 Taiwan Semiconductor Mfg Semiconductor package and method for fabricating the same
US20140225246A1 (en) * 2013-02-13 2014-08-14 Qualcomm Incorporated Dual substrate, power distribution and thermal solution for direct stacked integrated devices
US20150348940A1 (en) * 2014-05-28 2015-12-03 Invensas Corporation Structure and method for integrated circuits packaging with increased density
TW201545286A (en) * 2014-05-30 2015-12-01 Taiwan Semiconductor Mfg Ring structures in device die

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI722411B (en) * 2019-02-01 2021-03-21 南亞科技股份有限公司 Semiconductor package, semiconductor package stack and manufacturing method thereof
US11195823B2 (en) 2019-02-01 2021-12-07 Nanya Technology Corporation Semiconductor package and manufacturing method thereof

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