JP6122290B2 - 再配線層を有する半導体パッケージ - Google Patents
再配線層を有する半導体パッケージ Download PDFInfo
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- JP6122290B2 JP6122290B2 JP2012274772A JP2012274772A JP6122290B2 JP 6122290 B2 JP6122290 B2 JP 6122290B2 JP 2012274772 A JP2012274772 A JP 2012274772A JP 2012274772 A JP2012274772 A JP 2012274772A JP 6122290 B2 JP6122290 B2 JP 6122290B2
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
また、本発明の目的は、信号伝達経路を短縮し、大きさを縮小しながら複数の半導体チップ及び受動素子を搭載することができる半導体パッケージを提供することにある。
前記第2半導体チップは、前記データパッドに相対的に近く、前記電源パッドに相対的に遠く離隔され得る。
前記第1半導体チップと前記第2半導体チップとの間の第1電気的接続経路は、前記第2半導体チップと前記基板との間の第2電気的接続経路よりも短くあり得る。
前記上部配線層は、前記第1半導体チップの前記データパッドと前記第2半導体チップとの間に形成された第1再配線パターンと、前記第2半導体チップと前記基板との間に形成された第2再配線パターンと、を含み、前記第1再配線パターンは、前記第2再配線パターンよりも短く、前記第1半導体チップの前記データパッドは、前記第1導電性接続、前記第1再配線パターン、前記第2半導体チップ、前記第2再配線パターン、及び前記第2導電性接続を順に経由して前記基板に接続され得る。
前記上部配線層は、前記第1半導体チップの前記データパッドと前記第2半導体チップとの間に形成された第1再配線パッドと、前記第2半導体チップと前記基板との間に形成された再配線パターンと、前記再配線パターンの両端に形成された第2及び第3再配線パッドと、を含み、前記第2半導体チップは、前記第1再配線パッドに近く、前記第2導電性接続は、前記第3再配線パッドに接続され、前記第1半導体チップの前記データパッドは、前記第1再配線パッド、前記第2半導体チップ、前記第2再配線パッド、前記再配線パターン、前記第3再配線パッド、及び前記第2導電性接続を順に経由して前記基板に接続され得る。
前記半導体パッケージは、前記再配線パッド間に形成された第3導電性接続を更に含むことができ、前記第3導電性接続は、前記再配線パターンのうちの少なくとも1つの上部を横切り、前記第3導電性接続は、前記再配線パターンと離隔され、前記第3導電性接続は、ボンディングワイヤ(bonding wire)、ビームリード(beam lead)、又は導電性テープ(conductive tape)であり得る。
前記上部配線層は、前記最上層第1半導体チップ上を部分的に覆い、前記最上層第1半導体チップと前記第2半導体チップとの間には、前記上部配線層がないものとし得る。
前記第1半導体チップの前記データパッドは、全てが前記第2半導体チップ、前記再配線パッド、前記再配線パターン、及び前記第2導電性接続を順に経由して前記基板に電気的に接続され得る。
前記基板は、基板内部配線を含み、前記基板内部配線のそれぞれは、前記第1半導体チップの前記電源パッド又は前記第2半導体チップに接続され得る。
前記基板内には、前記第1半導体チップの前記データパッドと前記第2半導体チップとの間を連結する配線がないものとし得る。
前記第2半導体チップは、長軸と短軸の長さ比率が1.2以下であり得る。
前記第1半導体チップの前記電源パッドは、前記第2半導体チップを経由せずに前記基板に直接的に接続され得る。
前記半導体パッケージは、前記第2半導体チップに接続されたバッファチップを更に含むことができる。
前記バッファチップは、前記上部配線層上に形成され得る。
前記上部配線層は、前記第1半導体チップの前記データパッドと前記第2半導体チップとの間に形成された第1再配線パターンと、前記第2半導体チップと前記基板との間に形成された第2再配線パターンと、前記第2半導体チップと前記バッファチップとの間に形成された第3再配線パターンと、を含み、前記バッファチップは、前記第3再配線パターンを経由して前記第2半導体チップに接続され得る。
前記半導体パッケージは、中間配線層を更に含むことができ、前記第1半導体チップのうちの一部は、第1方向に順にオフセット整列されて第1チップスタック(chip stack)を構成し、前記第1半導体チップのうちの他の一部は、前記第1チップスタック上に前記第1方向と異なる第2方向に順にオフセット整列されて第2チップスタックを構成し、前記中間配線層は、前記第1チップスタックと前記第2チップスタックとの間に形成され、前記第1チップスタックに含まれる前記第1半導体チップは、前記中間配線層を経由して前記上部配線層に電気的に接続され得る。
前記上部配線層は、第1再配線パターン、前記第1再配線パターンの両端に接続された第1及び第2再配線パッド、前記第1再配線パターンと離隔された第2再配線パターン、及び前記第2再配線パターンの両端に接続された第3及び第4再配線パッドを含み、前記第2導電性接続の一端は、前記第1再配線パッドに接触し、前記第2再配線パッドは、前記第3半導体チップに電気的に接続され、前記第3導電性接続の一端は、前記第4再配線パッドに接触し、前記第3再配線パッドは、前記第3半導体チップに電気的に接続され、前記第2再配線パッドと前記第3半導体チップとの間に第4導電性接続が形成され、前記第3再配線パッドと前記第3半導体チップとの間に第5導電性接続が形成され得る。
前記上部配線層は、第1再配線パッド、前記第1再配線パッドと離隔された第2再配線パターン、及び前記第2再配線パターンの両端に接続された第3及び第4再配線パッドを含み、前記第2導電性接続の一端は、前記第1再配線パッドに接触し、前記第1再配線パッドは、前記第3半導体チップに電気的に接続され、前記第3導電性接続の一端は、前記第4再配線パッドに接触し、前記第3再配線パッドは、前記第3半導体チップに電気的に接続され得る。
前記上部配線層は、第1再配線パターン、及び前記第1再配線パターンの両端に接続された第1及び第2再配線パッドを含み、前記第2導電性接続の一端は、前記第1再配線パッドに接触し、前記第2再配線パッドは、前記第3半導体チップに電気的に接続され、前記第3導電性接続の一端は、前記第3半導体チップに接触し得る。
前記第2半導体チップの前記電源パッドは、前記第3半導体チップを経由せずに前記基板に直接的に接続され得る。
前記複数の第2半導体チップのうちの一部は、第1方向に順にオフセット整列されて第1チップスタック(chip stack)を構成し、前記複数の第2半導体チップのうちの他の一部は、前記第1チップスタック上に前記第1方向と異なる第2方向に順にオフセット整列されて第2チップスタックを構成し、前記第1チップスタック上に中間配線層が形成され、前記第1チップスタックに含まれる前記第2半導体チップは、前記中間配線層を経由して前記上部配線層に電気的に接続され得る。
前記第2チップスタックの底表面に付着して前記中間配線層上に接触する中間接着膜が提供され、前記第2導電性接続の一部は、前記中間接着膜を通過して前記中間配線層に接続され得る。
前記第1半導体チップは、バッファチップを含み、前記第2半導体チップのそれぞれは、前記第1半導体チップよりも大きい幅を有する不揮発性メモリチップを含み、前記第3半導体チップは、前記第2半導体チップよりも狭い幅を有するロジックチップを含み得る。
前記第1受動素子は、MLCC(Multi−Layer Ceramic Capacitor)、IPD(Integrated Passive Device)、又はそれらの組み合わせであり得る。
前記第1受動素子は、前記再配線パターンを経由して前記第2半導体チップに電気的に接続され得る。
前記上部配線層は、前記最上層第1半導体チップのパッシベーション絶縁膜上に直接的に接触し得る。
前記半導体パッケージは、前記第1受動素子と前記再配線パッドとの間に形成された第2導電性接続を更に含むことができ、前記第1受動素子は、前記第2導電性接続、前記再配線パッド、及び前記再配線パターンを経由して前記第2半導体チップに電気的に接続され、前記第2導電性接続は、導電性ペースト(conductive paste)、ソルダボール(solder ball)、又はソルダバンプ(solder bump)であり得る。
前記半導体パッケージは、前記第1受動素子と前記第2半導体チップとの間に形成されたボンディングワイヤ(bonding wire)を更に含むことができ、前記第1受動素子は、前記ボンディングワイヤを経由して前記第2半導体チップに電気的に接続され得る。
前記半導体パッケージは、前記基板上に第2受動素子を更に含むことができ、前記第2受動素子は、前記基板に形成された電極フィンガーを経由して前記第2半導体チップに電気的に接続され得る。
前記半導体パッケージは、前記最上層第1半導体チップ上に形成されて前記第2半導体チップに電気的に接続されたバッファチップを更に含むことができ、前記バッファチップは、DRAM又はSRAMを含み得る。
前記第1キャパシタ電極及び前記第2キャパシタ電極は、同一の水平レベルに形成され得る。
前記キャパシタ誘電膜は、前記第1キャパシタ電極の上部表面を覆い、前記第2キャパシタ電極は、前記キャパシタ誘電膜上に形成され得る。
前記第1キャパシタ電極及び前記第2キャパシタ電極は、前記第2半導体チップに電気的に接続され得る。
前記最上層第1半導体チップ上に、前記第2半導体チップに電気的に接続されたIPD(Integrated Passive Device)が搭載され得る。
その他の実施形態の具体的な事項は詳細な説明及び図面に含まれる。
また、半導体パッケージは、基板上にバッファチップ、支持台、接着膜、複数のメモリチップ、及びロジックチップが搭載され、メモリチップのうちの最上層メモリチップ上に再配線層が形成される。これにより、信号伝達経路が短縮され、構造的に安定し、複数の半導体チップを搭載しながらも軽薄短小化に有利な半導体パッケージを具現することができる。
3 基板
5 外部端子
7 ロジックチップ
9 チップスタック(chip stack)
10、20 第1及び第2チップスタック
11、12、13、14、21、22、23、24 メモリチップ
14P パッシベーション絶縁膜
50 支持台
59 封止材
91、93、94、95、96、97 データパッド
92 電源パッド
231、232、233、331、431 電極フィンガー
241、242、243、244、245、246、247、248、249、312、341、347、348、449、450、451、452、453、541 導電性接続
253、254、255、256、257 接着膜
261、262 バッファチップ
274、274P、284 再配線層
274A 第1絶縁膜
274B 第2絶縁膜
275、276、277、285、313、376、377、475、476 再配線パターン
291、292、293、294、295、296、297、298、311、314、393、394、395、396、491、492、493、494 再配線パッド
321、322、323 基板内部配線
405、406、511 デカップリングキャパシタ(decoupling capacitor)
407 IPD(Integrated Passive Device)
501、501A、505、505A キャパシタ電極
503、503A キャパシタ誘電膜
521、521A、525、525A キャパシタパッド
1002 ホスト(Host)
1100 ソリッドステートドライブ(SSD)
1113 インターフェース
1115 制御器(controller)
1118 不揮発性メモリ(non−volatile memory)
1119 バッファメモリ(buffer memory)
1200 eMMC(embedded multi−media chip)
1300 microSD
1900 携帯電話
2100 電子システム
2110 ボディ
2120 マイクロプロセッサユニット
2130 パワーユニット
2140 機能ユニット
2150 ディスプレイコントローラユニット
2160 ディスプレイユニット
2170 外部装置
2180 通信ユニット
Claims (30)
- 基板上に搭載されてデータパッド及び電源パッドを含む複数の第1半導体チップと、
前記第1半導体チップのうちの最上層第1半導体チップ上に形成されて複数の再配線パターン及び複数の再配線パッドを含む上部配線層と、
前記最上層第1半導体チップ上に形成されて前記データパッドに近い第2半導体チップと、
前記データパッドと前記第2半導体チップとの間に形成された第1導電性接続と、
前記第2半導体チップと前記基板との間に形成された第2導電性接続と、を有し、
前記再配線パターンは、同一レベルに配置されて互いに重畳せず、
前記第1半導体チップの前記データパッドは、前記第1導電性接続、前記第2半導体チップ、前記再配線パターン、前記再配線パッド、及び前記第2導電性接続を経由して前記基板に電気的に接続され、
前記第2半導体チップと前記複数の第1半導体チップとの間においてデータ信号を伝達する役割を担う配線は、前記複数の第1半導体チップの内の最下層の第1半導体チップよりも上部レベルに形成されることを特徴とする半導体パッケージ。
- 前記再配線パッドのうちの少なくとも1つは、前記最上層第1半導体チップの前記データパッドのうちの1つに直接的に接触することを特徴とする請求項1に記載の半導体パッケージ。
- 前記第2半導体チップは、前記データパッドに相対的に近く、前記電源パッドに相対的に遠く離隔されることを特徴とする請求項1に記載の半導体パッケージ。
- 前記第1半導体チップと前記第2半導体チップとの間の第1電気的接続経路は、前記第2半導体チップと前記基板との間の第2電気的接続経路よりも短いことを特徴とする請求項1に記載の半導体パッケージ。
- 前記上部配線層は、
前記第1半導体チップの前記データパッドと前記第2半導体チップとの間に形成された第1再配線パターンと、
前記第2半導体チップと前記基板との間に形成された第2再配線パターンと、を含み、
前記第1再配線パターンは、前記第2再配線パターンよりも短く、
前記第1半導体チップの前記データパッドは、前記第1導電性接続、前記第1再配線パターン、前記第2半導体チップ、前記第2再配線パターン、及び前記第2導電性接続を順に経由して前記基板に接続されることを特徴とする請求項4に記載の半導体パッケージ。 - 前記上部配線層は、
前記第1半導体チップの前記データパッドと前記第2半導体チップとの間に形成された第1再配線パッドと、
前記第2半導体チップと前記基板との間に形成された再配線パターンと、
前記再配線パターンの両端に形成された第2及び第3再配線パッドと、を含み、
前記第2半導体チップは、前記第1再配線パッドに近く、
前記第2導電性接続は、前記第3再配線パッドに接続され、
前記第1半導体チップの前記データパッドは、前記第1再配線パッド、前記第2半導体チップ、前記第2再配線パッド、前記再配線パターン、前記第3再配線パッド、及び前記第2導電性接続を順に経由して前記基板に接続されることを特徴とする請求項4に記載の半導体パッケージ。 - 前記再配線パッド間に形成された第3導電性接続を更に含み、
前記第3導電性接続は、前記再配線パターンのうちの少なくとも1つの上部を横切り、
前記第3導電性接続は、前記再配線パターンと離隔され、
前記第3導電性接続は、ボンディングワイヤ、ビームリード、又は導電性テープであることを特徴とする請求項1に記載の半導体パッケージ。 - 前記上部配線層は、前記最上層第1半導体チップ上を部分的に覆い、
前記最上層第1半導体チップと前記第2半導体チップとの間には、前記上部配線層がないことを特徴とする請求項1に記載の半導体パッケージ。 - 前記第1半導体チップの前記データパッドは、全てが前記第2半導体チップ、前記再配線パッド、前記再配線パターン、及び前記第2導電性接続を順に経由して前記基板に電気的に接続されることを特徴とする請求項1に記載の半導体パッケージ。
- 前記基板は、基板内部配線を含み、
前記基板内部配線のそれぞれは、前記第1半導体チップの前記電源パッド又は前記第2半導体チップに接続されることを特徴とする請求項9に記載の半導体パッケージ。 - 前記基板内には、前記第1半導体チップの前記データパッドと前記第2半導体チップとの間を連結する配線がないことを特徴とする請求項9に記載の半導体パッケージ。
- 前記第2半導体チップは、長軸と短軸との長さ比率が1.2以下であることを特徴とする請求項1に記載の半導体パッケージ。
- 前記第1半導体チップの前記電源パッドは、前記第2半導体チップを経由せずに前記基板に直接的に接続されることを特徴とする請求項1に記載の半導体パッケージ。
- 前記第2半導体チップに接続されたバッファチップを更に含むことを特徴とする請求項1に記載の半導体パッケージ。
- 前記バッファチップは、前記上部配線層上に形成されることを特徴とする請求項14に記載の半導体パッケージ。
- 前記上部配線層は、
前記第1半導体チップの前記データパッドと前記第2半導体チップとの間に形成された第1再配線パターンと、
前記第2半導体チップと前記基板との間に形成された第2再配線パターンと、
前記第2半導体チップと前記バッファチップとの間に形成された第3再配線パターンと、を含み、
前記バッファチップは、前記第3再配線パターンを経由して前記第2半導体チップに接続されることを特徴とする請求項15に記載の半導体パッケージ。 - 中間配線層を更に含み、
前記第1半導体チップのうちの一部は、第1方向に順にオフセット整列されて第1チップスタックを構成し、
前記第1半導体チップのうちの他の一部は、前記第1チップスタック上に前記第1方向と異なる第2方向に順にオフセット整列されて第2チップスタックを構成し、
前記中間配線層は、前記第1チップスタックと前記第2チップスタックとの間に形成され、
前記第1チップスタックに含まれる前記第1半導体チップは、前記中間配線層を経由して前記上部配線層に電気的に接続されることを特徴とする請求項1に記載の半導体パッケージ。 - 基板上に搭載されてデータパッド及び電源パッドを含む複数の第1半導体チップと、
前記第1半導体チップのうちの最上層第1半導体チップ上に形成され、複数の第1及び第2再配線パッド、前記第1再配線パッドと前記第2再配線パッドとの間の第1再配線パターン、複数の第3及び第4再配線パッド、前記第3再配線パッドと前記第4再配線パッドとの間の第2再配線パターン、複数の第5及び第6再配線パッド、前記第5再配線パッドと前記第6再配線パッドとの間の第3再配線パターン、複数の第7及び第8再配線パッド、及び前記第7再配線パッドと前記第8再配線パッドとの間の第4再配線パターンを含み、前記第1再配線パッドが前記最上層第1半導体チップの前記データパッドに接触する上部配線層と、
前記上部配線層上の第2半導体チップと、
前記第1再配線パッドと前記データパッドとの間の第1導電性接続と、
前記第2再配線パッドと前記第2半導体チップとの間の第2導電性接続と、
前記第2半導体チップと前記第3再配線パッドとの間の第3導電性接続と、
前記第4再配線パッドと前記基板との間の第4導電性接続と、
前記第2半導体チップと前記第5再配線パッドとの間の第5導電性接続と、
前記第6再配線パッドと前記第7再配線パッドとの間の第6導電性接続と、
前記第8再配線パッドと前記基板との間の第7導電性接続と、を有し、
前記第6導電性接続は、ボンディングワイヤ、ビームリード、又は導電性テープであり、
前記第1再配線パターン及び前記第2再配線パターンのうちの少なくとも1つは、前記第6再配線パッドと前記第7再配線パッドとの間に配置され、
前記第6導電性接続は、前記第1再配線パターン及び前記第2再配線パターンと離隔され、
前記第2半導体チップと前記複数の第1半導体チップとの間においてデータ信号を伝達する役割を担う配線は、前記複数の第1半導体チップの内の最下層の第1半導体チップよりも上部レベルに形成されることを特徴とする半導体パッケージ。
- 基板上に搭載されてデータパッド及び電源パッドを含む複数の第1半導体チップと、
前記第1半導体チップのうちの最上層第1半導体チップ上を部分的に覆い、複数の第1再配線パッド、複数の第2再配線パッド、及び前記第1再配線パッドと前記第2再配線パッドとの間に形成された複数の再配線パターンを含む上部配線層と、
前記最上層第1半導体チップ上の第2半導体チップと、
前記第1半導体チップ間に形成されて前記データパッドに接触する第1導電性接続と、
前記第2半導体チップと前記最上層第1半導体チップの前記データパッドとの間に形成された第2導電性接続と、
前記第2半導体チップと前記第1再配線パッドとの間の第3導電性接続と、
前記第2再配線パッドと前記基板との間に形成された第4導電性接続と、を有し、
前記最上層第1半導体チップと前記第2半導体チップとの間には、前記上部配線層がなく、
前記第1半導体チップの前記データパッドは、前記第1導電性接続、前記第2導電性接続、前記第2半導体チップ、前記第3導電性接続、前記第1再配線パッド、前記再配線パターン、前記第2再配線パッド、及び前記第4導電性接続を順に経由して前記基板に電気的に接続され、
前記第2半導体チップと前記複数の第1半導体チップとの間においてデータ信号を伝達する役割を担う配線は、前記複数の第1半導体チップの内の最下層の第1半導体チップよりも上部レベルに形成されることを特徴とする半導体パッケージ。
- 基板上に搭載された第1半導体チップと、
前記第1半導体チップと前記基板とを連結する第1導電性接続と、
前記基板上に搭載されて前記第1半導体チップと同一レベルに位置する支持台と、
前記支持台及び前記第1半導体チップ上に搭載されてデータパッド及び電源パッドを含む複数の第2半導体チップと、
前記第2半導体チップのうちの最下層第2半導体チップの底表面に形成されて前記支持台及び前記第1半導体チップ上に付着された接着膜と、
前記第2半導体チップのうちの最上層第2半導体チップ上に形成されて前記データパッドに電気的に接続された上部配線層と、
前記データパッドと前記上部配線層との間に形成された第2導電性接続と、 前記上部配線層上に搭載され、前記データパッドに近く形成されて前記上部配線層に電気的に接続された第3半導体チップと、
前記第3半導体チップと前記基板との間に形成された第3導電性接続と、を有し、
前記第1導電性接続は、前記接着膜の内部を通過し、
前記複数の第2半導体チップは、前記データパッド、前記第2導電性接続、前記上部配線層、前記第3半導体チップ、及び前記第3導電性接続を順に経由して前記基板に電気的に接続され、
前記第3半導体チップと前記第1半導体チップ、前記複数の第2半導体チップとの間においてデータ信号を伝達する役割を担う配線は、前記第1半導体チップよりも上部レベルに形成されることを特徴とする半導体パッケージ。
- 基板上に搭載されてデータパッド及び電源パッドを含む複数の第1半導体チップと、
前記第1半導体チップのうちの最上層第1半導体チップ上に形成されて複数の再配線パターン及び複数の再配線パッドを含む上部配線層と、
前記最上層第1半導体チップ上に形成されて前記データパッドに近い第2半導体チップと、
前記最上層第1半導体チップ上に形成されて前記第2半導体チップに電気的に接続された第1受動素子と、
前記データパッドと前記第2半導体チップとの間に形成された第1導電性接続と、
前記第2半導体チップと前記基板との間に形成された第2導電性接続と、を有し、
前記第1半導体チップの前記データパッドは、前記第1導電性接続、前記第2半導体チップ、前記再配線パターン、前記再配線パッド、及び前記第2導電性接続を経由して前記基板に電気的に接続され、
前記第2半導体チップと前記複数の第1半導体チップとの間においてデータ信号を伝達する役割を担う配線は、前記複数の第1半導体チップの内の最下層の第1半導体チップよりも上部レベルに形成されることを特徴とする半導体パッケージ。
- 前記第1受動素子は、前記第2半導体チップに近く搭載されることを特徴とする請求項21に記載の半導体パッケージ。
- 前記第1受動素子は、MLCC(Multi−Layer Ceramic Capacitor)、IPD(Integrated Passive Device)、又はそれらの組み合わせであることを特徴とする請求項21に記載の半導体パッケージ。
- 前記第1受動素子は、前記再配線パターンを経由して前記第2半導体チップに電気的に接続されることを特徴とする請求項21に記載の半導体パッケージ。
- 前記上部配線層は、前記最上層第1半導体チップのパッシベーション絶縁膜上に直接的に接触することを特徴とする請求項21に記載の半導体パッケージ。
- 前記第1受動素子と前記再配線パッドとの間に形成された第2導電性接続を更に含み、
前記第1受動素子は、前記第2導電性接続、前記再配線パッド、及び前記再配線パターンを経由して前記第2半導体チップに電気的に接続され、
前記第2導電性接続は、導電性ペースト、ソルダボール、又はソルダバンプであることを特徴とする請求項21に記載の半導体パッケージ。 - 前記第1受動素子と前記第2半導体チップとの間に形成されたボンディングワイヤを更に含み、
前記第1受動素子は、前記ボンディングワイヤを経由して前記第2半導体チップに電気的に接続されることを特徴とする請求項21に記載の半導体パッケージ。 - 前記基板上に搭載された第2受動素子を更に含み、
前記第2受動素子は、前記基板に形成された電極フィンガーを経由して前記第2半導体チップに電気的に接続されることを特徴とする請求項21に記載の半導体パッケージ。 - 前記最上層第1半導体チップ上に形成されて前記第2半導体チップに電気的に接続されたバッファチップを更に含み、
前記バッファチップは、DRAM又はSRAMを含むことを特徴とする請求項21に記載の半導体パッケージ。 - 基板上に搭載されてデータパッド及び電源パッドを含む複数の第1半導体チップと、
前記第1半導体チップのうちの最上層第1半導体チップ上に形成されてデカップリングキャパシタ、複数の再配線パターン、及び複数の再配線パッドを含む上部配線層と、
前記最上層第1半導体チップ上に形成されて前記データパッドに近い第2半導体チップと、
前記データパッドと前記第2半導体チップとの間に形成された第1導電性接続と、
前記第2半導体チップと前記基板との間に形成された第2導電性接続と、を有し、
前記第1半導体チップの前記データパッドは、前記第1導電性接続、前記第2半導体チップ、前記再配線パターン、前記再配線パッド、及び前記第2導電性接続を経由して前記基板に電気的に接続され、
前記第2半導体チップと前記複数の第1半導体チップとの間においてデータ信号を伝達する役割を担う配線は、前記複数の第1半導体チップの内の最下層の第1半導体チップよりも上部レベルに形成されることを特徴とする半導体パッケージ。
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2012
- 2012-12-17 JP JP2012274772A patent/JP6122290B2/ja active Active
- 2012-12-21 CN CN2012105607986A patent/CN103178054A/zh active Pending
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US9496216B2 (en) | 2016-11-15 |
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