US20180114781A1

US20180114781A1 - Package structure and manufacturing method thereof

Info

Publication number: US20180114781A1
Application number: US15/717,944
Authority: US
Inventors: Chi-An Wang; Hung-Hsin Hsu
Original assignee: Powertech Technology Inc
Current assignee: Powertech Technology Inc
Priority date: 2016-10-21
Filing date: 2017-09-28
Publication date: 2018-04-26
Also published as: TWI643268B; TW201828370A; TW201828371A; US20180114782A1; US20180114704A1; US10170458B2; US10276553B2; TW201830527A; CN107978583A; US20180114783A1; TW201828372A; CN107978571A; CN107978583B; TWI644369B; TWI665740B; CN107978532A; TWI651828B; CN107978566A; TW201824500A; US20180114786A1

Abstract

A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S. provisional application Ser. No. 62/410,851, filed on Oct. 21, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of the specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a package structure and a manufacturing method thereof and more particularly relates to a semiconductor package structure.

2. Description of Related Art

In order for electronic product design to achieve being light, slim, short, and small, semiconductor packaging technology has kept progressing, in attempt to develop products that are smaller in volume, lighter in weight, higher in integration, and more competitive in the market. For example, 3D stacking technologies such as package have been developed to meet the requirements of higher packaging densities. As such, how to increase the number of I/O connections with lower manufacturing cost has become a challenge to researchers in the field.

SUMMARY OF THE INVENTION

The disclosure provides a package structure and manufacturing method thereof, which reduces manufacturing cost and increases the number of I/O connections.
The disclosure provides a manufacturing method of a package structure. The method includes at least the following steps. A die is disposed on a circuit carrier. A substrate is disposed on the die. The substrate includes a plurality of openings. A plurality of conductive wires going through the openings of the substrate are formed to form electrical connection between the substrate and the circuit carrier. An encapsulant is formed on the circuit carrier to encapsulate the die, the substrate and the conductive wires.
The disclosure provides a package structure including a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.
Based on the above, the substrate disposed on the die is conducive to form the conductive wires. In addition, the substrate may serve as the conductive interface for further electrical connection. Moreover, since the vias are formed on the encapsulant to expose at least a portion of the substrate, it makes the package structure more flexible for compatibility with different device applications.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1A to FIG. 1D are schematic cross-sectional views illustrating manufacturing method of a package structure according to an embodiment of the disclosure.

FIG. 2 is a schematic top view illustrating a substrate of a package structure according to an embodiment of the disclosure.

FIG. 3 is a schematic cross-sectional view illustrating a package structure according to an embodiment of the disclosure.

FIG. 4 is a schematic cross-sectional view illustrating a package structure according to an embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 1A to FIG. 1D are schematic cross-sectional views illustrating manufacturing method of a package structure according to an embodiment of the disclosure. FIG. 2 is a schematic top view illustrating a substrate of a package structure according to an embodiment of the disclosure. Referring to FIG. 1A, a circuit carrier 110 is provided. The circuit carrier 110 may have a top surface S1 and a bottom surface S2 opposite to the top surface S1. For example, the circuit carrier 110 may include a core layer 112, a top circuit layer 114 disposed on the top surface S1 and the bottom circuit layer 116 disposed on the bottom surface S2 of the circuit carrier 110. In other word, the core layer 112 is disposed between and electrically connects the top circuit layer 114 and the bottom circuit layer 116. In some embodiments, the top circuit layer 114 may include a plurality of conductive pads 114 a and the bottom circuit layer 116 may include a plurality of conductive pads 116 a used for electrical connection. Moreover, the conductive pads 114 a of the top circuit layer 114 and the conductive pads 116 a of the bottom circuit layer 116 may be formed by the same material copper, solder, gold, nickel, or the like and the same process such as photolithography and etching processes. In other embodiments, the conductive pads 114 a of the top circuit layer 114 and the conductive pads 116 a of the bottom circuit layer 116 may be formed by different materials and/or different processes according to the design requirement.
The core layer 112 may include embedded circuit layers serving as an intermediate circuit layer to electrically connect the top circuit layer 114 and the bottom circuit layer 116. For example, the core layer 112 may include a base layer and a plurality of conductive vias penetrating through the base layer. In addition, the two opposite ends of the conductive vias of the core layer 112 may electrically connect to the conductive pads 114 a of the top circuit layer 114 and the conductive pads 116 a of the bottom circuit layer 116. In some embodiments, the circuit carrier 110 may include a plurality of conductive structures 118 formed on the bottom surface S2. For example, a material of the conductive structures 118 may include copper, tin, gold, nickel or other suitable conductive material, which is not limited thereto. Moreover, the conductive structures 118 may, for example, be conductive bumps, conductive pillars or solder balls formed by a ball placement process and a reflow process. It should be noted that other possible forms and shapes of the conductive structures 118 may be utilized for further electrical connection. In some embodiments, the conductive structures 118 may form a fine pitched array arranged on the bottom surface S2 of the circuit carrier 110 as required in the subsequent processes.
In addition, a die 120 is bonded on the top surface S1 of the circuit carrier 110. The die 120 may be electrically connected to the circuit carrier 110 through flip-chip bonding. In some embodiment, an active surface (not illustrated) of the die 120 may be coupled to the conductive pads 114 a of the top circuit layer 114 of the circuit carrier 110 through a plurality of conductive bumps 122 facing toward the circuit carrier 110. The conductive bumps 122 may be copper bumps. In some embodiments, solders (not illustrated) may be applied onto surfaces of the conductive bumps 122 to couple with the conductive pads 114 a of the top circuit layer 114 of the circuit carrier 110. Furthermore, the die 120 may be, for example, an ASIC (Application-Specific Integrated Circuit). In some embodiments, the die 120 may be used to perform logic applications. However, it construes no limitation in the disclosure. Other suitable active devices may also be utilized as the die 120. Furthermore, an underfill (not illustrated) may be formed on the top surface S1 of the circuit carrier 110 and also in the gap between the active surface of the die 120 and the top surface S1 of the circuit carrier 110 to enhance the reliability of the die bonding process.
Referring to FIG. 1B and FIG. 2, a substrate 130 is disposed on the die 120. The substrate 130 may include a plurality of openings 130 a. A material of the substrate 130 may include conductive materials (e.g., aluminium, copper, nickel, gold or alloys thereof, etc.), non-conductive materials (e.g., glass, rigid plastic or the like, etc.) or combination thereof. It should be noted that other suitable material may be adapted as the substrate 130 as long as the material is able to withstand the processes performed thereon. In addition, the size, the shape and the thickness of the substrate 130 construe no limitation in the disclosure. In addition, the openings 130 a of the substrate 130 may be formed through mechanical drilling, photolithography and etching or other suitable methods, which is not limited thereto. Moreover, referring to FIG. 2, the openings 130 a of the substrate 130 may be formed on the substrate 130 surrounding the periphery of the die 120. Moreover, the openings 130 a may be staggered from the die 120. It should be noted that the number of the openings 130 a construes no limitation in the disclosure.
In some embodiments, a conductive layer 130 b may be formed on a surface 130 c opposite to the die 120 of the substrate 130 by means of physical vapor deposition (PVD), chemical vapor deposition (CVD), electro-plating or other suitable metal deposition process, which is not limited thereto. A material of the conductive layer 130 b may include aluminum, copper, gold, silver or other suitable electrically conductive material. However, it construes no limitation in the disclosure. In other embodiments, the conductive layer 130 b may be patterned to form as a plurality of conductive connectors such as contact pads (e.g., aluminium pads, copper pads or the like). In other word, the substrate 130 not only serves as the conductive connectors for performing subsequent electrical bonding process but also provides a spacer function to prevent damage to the die 120.
The substrate 130 may be bonded to the die 120 through an adhesive layer 140. In some embodiments, the adhesive layer 140 may be a die attach film or formed from the adhesive material including an epoxy resin. The adhesive layer 140 may be formed by methods such as spin coating, inject printing or other suitable methods for providing a structural support to eliminate the need for mechanical clamping between the die 120 and the substrate 130.
Referring to FIG. 1C, the substrate 130 and the circuit carrier 110 are electrically connected by a plurality of conductive wires 150 that go through the openings 130 a of the substrate 130. For example, the conductive wires 150 may be formed through a wire bonder (not illustrated). The types of the wire bonder may include wedge bond, ball bond, or other suitable wire bonder according to the design requirement. Moreover, the conductive wires 150 are connected between the conductive layer 130 b of the substrate 130 and the circuit carrier 110. A material of the conductive wires 150 may be gold, copper, or other suitable material. However, it construes no limitation in the disclosure. In some embodiments, the conductive wires 150 may be formed from the substrate 130 to the circuit carrier 110. In other embodiments, the conductive wires 150 may be formed from the circuit carrier 110 to the substrate 130. The forming sequence of the conductive wires 150 may depend on the design requirement. In some embodiments, since the conductive wires 150 are formed between the conductive layer 130 b of the substrate 130 and the circuit carrier 110 and through the openings 130 a of the substrate 130, the size of the openings 130 a of the substrate 130 may be large enough for the wire bonder to pass through.
Moreover, a peak (not illustrated) of each of the conductive wires 150 is defined as the highest point relative to the two ends of each of the conductive wires 150 after connecting the substrate 130 and the circuit carrier 110. In addition, a loop height H of each of the conductive wires 150 is defined as a distance between the peak of each of the conductive wires 150 and the circuit carrier 110. It should be noted that the value of the loop height H of each of the conductive wires 150 depends on the types of the wire bonder and/or the design requirement.
In addition, each of the conductive wires 150 may include a first segment 150 a, a central segment 150 b and a second segment 150 c. The first segment 150 a may be coupled to the circuit carrier 110, the second segment 150 c may be coupled to the substrate 130, and the central segment 150 b may be the segment between the first segment 150 a and the second segment 150 c. In some embodiments, the first segment 150 a may be formed below the substrate 130 and the second segment 150 c may be formed above the substrate 130. The second segment 150 c of each of the conductive wires 150 may be formed with an arc shape. In addition, the peak of each of the conductive wires 150 may be the highest point of the second segment 150 c. Furthermore, the central segment 150 b may pass through a corresponding opening 130 a of the substrate 130. In some embodiments, the loop height H of each of the conductive wires 150 may be greater than a distance D1 between the surface 130 c of the substrate 130 and the top surface S1 of the circuit carrier 110.
Referring to FIG. 1D, an encapsulant 160 is formed on the circuit carrier 110 to encapsulate the die 120, the substrate 130, the adhesive layer 140 and the conductive wires 150. In some embodiments, a thickness of the encapsulant 160 is greater than the loop height H of the conductive wires 150. In addition, the encapsulant 160 may include a molding compound formed by a molding process. In some embodiments, the encapsulant 160 may be formed by an insulating material such as epoxy, resins, moldable polymer, or other suitable resins. However, it construes no limitation in the disclosure.
Thus, the package structure 10 have the substrate 130 stacked on the die 120 to serve as the conductive interface for performing the wire bonding process and form an additional interposer within the package structure 10 unnecessary for further electrical connection. In this way, a simplified manufacturing method with lower manufacturing cost may be achieved.
FIG. 3 is a schematic cross-sectional view illustrating a package structure according to an embodiment of the disclosure. Referring to FIG. 3, the manufacturing methods of a package structure 20 is similar to the manufacturing methods of the embodiment illustrated in FIG. 1A to FIG. 1D. The detailed descriptions are omitted herein. The difference between the present embodiment and the embodiment illustrated in FIG. 1A to FIG. 1D lies in that a plurality of vias 160 a may be formed on the encapsulant 160 extending from a surface 160 b of the encapsulant 160 to the surface 130 c of the substrate 130 to expose at least a portion of the substrate 130 so as to form the package structure 20 after forming the encapsulant 160 on the circuit carrier 110 as illustrated in FIG. 1D.
For example, the encapsulant 160 may be removed by laser ablation, laser drilling, mechanical drilling, or other suitable methods to form the vias 160 a. It should be noted that the number of the vias construes no limitation in the disclosure. Moreover, for example, a depth D2 of each of the vias 160 a may be controlled by the power of the laser, the speed at which the laser is moved, and/or other processing factors. In some embodiments, the depth D2 of each of the vias 160 a may be equal to a distance D3 between the surface 130 c of the substrate 130 and the surface 160 b of the encapsulant 160 farthest from the circuit carrier 110. In some embodiments, a portion of the vias 160 a may be formed within the area of the die 120. Since the substrate 130 provides a spacer function, the reliability of the die 120 may not be affected when forming the portion of the vias 160 a formed within the area of the die 120.
In some embodiments, the vias 160 a may be staggered from the openings 130 a of the substrate 130. As such, when forming the vias 160 on the encapsulant 160, the conductive wires 150 may not be affected, thereby ensuring the electrical connection between the substrate 130 and the circuit carrier 110. In some embodiments, the vias 160 a may be formed corresponding to the conductive layer 130 b to form conductive vias. As such, the vias 160 a may serve as the conductive path between the package structure 20 and the external connectors. Furthermore, the package structure 20 may achieve the fine pitch requirement and increase the number of I/O connections. Therefore, the package structures 20 may be compatible with high-end device applications and advanced front-end technology node, of which a number of I/O connections is higher, and a pad pitch of each die is narrower.
FIG. 4 is a schematic cross-sectional view illustrating a package structure according to an embodiment of the disclosure. Referring to FIG. 4, the manufacturing methods of a package structure 30 is similar to the manufacturing methods of the embodiment illustrated in FIG. 3. The detailed descriptions are omitted herein. As shown in FIG. 4, the vias 160 a may be filled with a conductive element 170 and a semiconductor element 200 may be stacked on the encapsulant 160 and also electrically connected to the substrate 130 to form the package structure 30.
For example, the conductive element 170 filled in the vias 160 a may be formed as conductive bumps, conductive pillars, conductive pads, or other conductive connectors. In some embodiments, the conductive element 170 may be formed by having a conductive material (e.g., aluminum, copper, nickel, gold, silver, solder, or alloy, etc.) deposited on the surface 160 b of the encapsulant 160 and fill the vias 160 a through evaporation, electro-plating, ball drop, screen printing, or other suitable methods. In addition, the conductive material may be patterned through a photolithography and an etching process to form the conductive element 170. However, the material and the forming process of the conductive element 170 construe no limitation in the disclosure. As such, after the vias 160 a are filled with the conductive element 170, the package structure may have the conductive elements 170 and the conductive structures 118 of the circuit carrier 110 on the two opposite sides of the semiconductor package 30, thereby increasing the number of I/O connections.
In some embodiments, the vias 160 a may be filled with solder materials by paste print process to enable the ball grid array (BGA) interconnections. In other embodiments, the vias 160 a may be used to build up the interconnect structure (e.g. the conductive element 170) for further electrically connection to the semiconductor element 200. In other embodiments, the semiconductor element 200 may include DRAM, NAND flash memory or other suitable active devices, which is not limited thereto. Moreover, the semiconductor element 200 may further include a plurality of conductive structure 202 correspondingly coupled to the conductive elements 170, for example. In addition, the conductive structures 202 may be conductive bumps, conductive pillars or solder balls formed by a ball placement process and a reflow process. In other word, the semiconductor element 200 may be stacked on the encapsulant 160 and electrically connected to the circuit carrier 110 through the conductive elements 170, the substrate 130, and the conductive wires 150 to form the package structure 30.
In some embodiments, the package structure 30 may sometimes be referred to as a package-on-package (POP) structure. Therefore, the package structure may be conducive for further electrical connection, since the substrate 130 may serve as the conductive interface and the vias 160 a are formed on the encapsulant 160 to expose at least a portion of the substrate 130. As such, it makes the package structure more flexible for compatibility with different device applications.
Based on the above, the substrate disposed on the die is not only conducive to form the conductive wires but also provides a spacer function to prevent the damage of the die in the subsequent processes. In addition, when the vias are formed on the encapsulant to expose at least a portion of the substrate, the conductive wires may serve as the conductive interface for further electrical connection. Therefore, the package structure may achieve the fine pitch requirement and also increase the number of I/O connections. As such, it makes the package structure more flexible for compatibility with different device applications. As a result, it may open the possibility to various package designs with lower manufacturing cost.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.

Claims

What is claimed is:

1. A manufacturing method of a package structure, comprising:

disposing a die on a circuit carrier;

disposing a substrate on the die, wherein the substrate comprises a plurality of openings;

forming a plurality of conductive wires going through the openings of the substrate to form electrical connection between the substrate and the circuit carrier; and

forming an encapsulant on the circuit carrier to encapsulate the die, the substrate and the conductive wires.

2. The manufacturing method of a package structure according to claim 1, wherein the die is disposed on the circuit carrier through flip-chip bonding.

3. The manufacturing method of a package structure according to claim 1, wherein disposing the substrate on the die is adhering disposing the substrate and the die to each other using an adhesive layer.

4. The manufacturing method of a package structure according to claim 1, wherein forming a plurality of conductive wires is forming a plurality of conductive wires through a wire bonder.

5. The manufacturing method of a package structure according to claim 1, wherein each of the conductive wires comprises a first segment connected to the circuit carrier, a second segment connected to the substrate and a central segment connected between the first segment and the second segment, the first segment is formed below the substrate, the second segment is formed above the substrate and the central segment is formed in one of the corresponding openings of the substrate.

6. The manufacturing method of a package structure according to claim 1, further comprising:

forming the openings on the substrate, wherein the openings surround the periphery of the die.

7. The manufacturing method of a package structure according to claim 1 further comprising:

forming a plurality of vias on the encapsulant to expose at least a portion of the substrate.

8. The manufacturing method of a package structure according to claim 7, wherein a depth of the vias is a distance between a surface of the substrate farthest from the circuit carrier and a surface of encapsulant farthest from the circuit carrier.

9. The manufacturing method of a package structure according to claim 7, further comprising:

filling the vias with a conductive element.

10. The manufacturing method of a package structure according to claim 9, further comprising:

disposing a semiconductor element on the encapsulant and electrically connecting the semiconductor element to the substrate through the vias.

11. A package structure, comprising:

a circuit carrier;

a substrate, disposed on the circuit carrier, wherein the substrate comprises a plurality of openings;

a die, disposed between the circuit carrier and the substrate;

a plurality of conductive wires, going through the openings of the substrate to electrically connect between the substrate and the circuit carrier; and

an encapsulant, disposed on the circuit carrier, wherein the encapsulant encapsulates the die, the substrate and the conductive wires.

12. The package structure according to claim 11, further comprising:

an adhesive layer, disposed between the circuit carrier and the substrate.

13. The package structure according to claim 11, wherein the die comprises a plurality of conductive bumps facing toward the circuit carrier, and the die is electrically connected to the circuit carrier through the conductive bumps.

14. The package structure according to claim 11, wherein a loop height of each of the conductive wires is greater than a distance between a surface of the substrate opposite to the circuit carrier and a surface of the circuit carrier facing toward the substrate.

15. The package structure according to claim 11, wherein each of the conductive wires comprises a first segment connected to the circuit carrier, a second segment connected to the substrate and a central segment connected between the first segment and the second segment, the first segment is disposed below the substrate, the second segment is disposed above the substrate and the central segment is disposed in one of the corresponding openings of the substrate.

16. The package structure according to claim 11, wherein the openings are arranged on the substrate surrounding the periphery of the die.

17. The package structure according to claim 11, wherein the encapsulant comprises a plurality of vias exposing at least a portion of the substrate.

18. The package structure according to claim 17, wherein a depth of the vias is a distance between a surface of the substrate farthest from the circuit carrier and a surface of the encapsulant farthest from the circuit carrier.

19. The package structure according to claim 17, wherein the encapsulant comprises a conductive element disposed in the vias.

20. The package structure according to claim 19, further comprising:

a semiconductor element, disposed on the encapsulant, wherein the semiconductor element is electrically connected to the substrate through the vias.