TW202218069A - 半導體封裝及製造半導體封裝的方法 - Google Patents

半導體封裝及製造半導體封裝的方法 Download PDF

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TW202218069A
TW202218069A TW109143341A TW109143341A TW202218069A TW 202218069 A TW202218069 A TW 202218069A TW 109143341 A TW109143341 A TW 109143341A TW 109143341 A TW109143341 A TW 109143341A TW 202218069 A TW202218069 A TW 202218069A
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die
interposer
molding material
protective layer
semiconductor package
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TW109143341A
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TWI765455B (zh
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曾淑容
李福仁
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台灣積體電路製造股份有限公司
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Abstract

在本發明實施例中，一種半導體封裝包括中介件、晶粒、保護層、多個第一電連接件及第一模制材料。晶粒包括第一表面及與第一表面相對的第二表面，且晶粒通過第一表面結合到中介件。保護層設置在晶粒的第二表面上。第一電連接件設置在晶粒旁邊。第一模制材料設置在晶粒、保護層及第一電連接件旁邊。

Description

半導體封裝及製造半導體封裝的方法
近年來，由於各種電子裝置（例如，電晶體、二極體、電阻器、電容器等）的集成密度不斷提高，半導體行業已經歷快速增長。在很大程度上，集成密度的此種提高來自於最小特徵尺寸（minimum feature size）的連續減小，此使得更多的裝置能夠整合到給定的區域中。
這些更小的電子裝置還需要比先前的封裝佔據更少面積的更小的封裝。有前景的半導體封裝之一是用於面向雲端運算、資料中心及超級電腦應用的先進產品的“基底上晶圓上晶片（chip on wafer on substrate，CoWoS）”結構。儘管現有的半導體封裝對於其預期目的來說一般是足夠的，然而其尚未在所有方面都完全令人滿意。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。為簡化本公開，下文闡述元件及佈置的具體實例。當然，這些僅為實例而非旨在進行限制。例如，以下說明中將第二特徵形成在第一特徵“之上”或第一特徵“上”可包括其中第二特徵與第一特徵被形成為直接接觸的實施例，且也可包括其中第二特徵與第一特徵之間可形成有附加特徵、進而使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參考編號和/或字母。此種重複使用是出於簡明及清晰的目的，且自身並不表示所論述的各種實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“頂部（top）”、“下面（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”及類似用語等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。除圖中所繪示的取向以外，所述空間相對性用語旨在還囊括裝置在使用或操作中的不同取向。裝置可被另外取向（旋轉90度或處於其他取向），且本文所使用的空間相對性描述語可同樣相應地作出解釋。
也可包括其他特徵及製程。例如，可包括測試結構，以説明對三維（three-dimensional，3D）封裝或三維積體電路（3D integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試墊，以使得能夠對3D封裝或3DIC進行測試、對探針和/或探針卡（probe card）進行使用以及進行類似操作。可對中間結構以及最終結構實行驗證測試。另外，本文所公開的結構及方法可結合包括對已知良好晶粒（known good die）進行中間驗證的測試方法來使用，以提高良率（yield）並降低成本。
圖1A到圖1D是根據一些實施例的形成晶粒的方法中的各種階段的示意性剖視圖。
參照圖1A，提供半導體晶圓20。在一些實施例中，半導體晶圓20包括任意數目的晶粒22。半導體晶圓20可包括塊狀半導體基底（bulk semiconductor substrate）、絕緣體上半導體（semiconductor-on-insulator，SOI）基底或類似物。半導體晶圓20的半導體材料可為：矽、鍺；化合物半導體，包括矽鍺、碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦和/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或者其組合。也可使用例如多層式基底或梯度基底等其他基底。半導體晶圓20可為經摻雜的或未經摻雜的。半導體晶圓20可包括可用於產生晶粒22的設計的所期望結構及功能要求的各種各樣的主動裝置及被動裝置（例如電容器、電阻器、電感器及類似物）。可使用任何合適的方法將主動裝置及被動裝置形成在半導體晶圓20內或者形成在半導體晶圓20的主動表面20a上。
在主動表面20a上形成包括一個或多個介電層及相應金屬化圖案的內連線結構24。介電層中的金屬化圖案可例如通過使用通孔和/或跡線在裝置之間路由電訊號，且還可包含各種電裝置（例如電容器、電阻器、電感器或類似物）。所述各種裝置及金屬化圖案可進行內連以實行一個或多個功能。所述功能可包括記憶體結構、處理結構、感測器、放大器、功率分配、輸入/輸出電路系統或類似物。
在一些實施例中，將結合墊26電連接到內連線結構24，且形成電連接件28且將電連接件28電連接到結合墊26，以提供到電路系統及裝置的外部電連接。在一些實施例中，利用電連接件28將晶粒22結合到其他結構。電連接件28可為受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、例如球格陣列（ball grid array，BGA）等焊球、金屬柱、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊或類似物。電連接件28包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合等導電材料。在電連接件28是焊料凸塊的實施例中，通過例如蒸發、電鍍、印刷、焊料轉移、植球或類似方法等各種方法最初在結合墊26上形成焊料層來形成電連接件28。在此實施例中，一旦已在結合墊26上形成焊料層，就實行回流（reflow）以將所述材料造型成所期望的凸塊形狀。在另一實施例中，電連接件28是通過濺鍍、印刷、電鍍、化學鍍覆、化學氣相沉積（chemical vapor deposition，CVD）或類似方法形成的金屬柱（例如銅柱）。在實施例中，金屬柱是無焊料的，且具有實質上垂直的側壁。在一些實施例中，在金屬柱電連接件28的頂部上形成金屬頂蓋層（metal cap layer）（未示出）。在一些實施例中，金屬頂蓋層包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物或其組合，且通過鍍覆製程形成所述金屬頂蓋層。所屬領域中的普通技術人員將理解，以上實例是出於例示目的而提供。對於給定的應用，可適當地使用其他電路系統。
參照圖1B，對半導體晶圓20的表面20b實行薄化製程（thinning process）以將半導體晶圓20薄化。表面20b與主動表面20a相對設置。主動表面20a可為前側表面，且表面20b可為背側表面。薄化製程可包括蝕刻製程、研磨製程、類似製程或其組合。在一些實施例中，在薄化製程之後，半導體晶圓20、內連線結構24及電連接件28具有介於約100 μm到約300 μm範圍內的組合厚度。
參照圖1C，在半導體晶圓20的表面20b上形成保護材料30。在一些實施例中，保護材料30完全覆蓋半導體晶圓20的表面20b。保護材料30可為例如膠水、黏合劑、類似物或其組合等電絕緣材料。保護材料30的材料可包括環氧樹脂、酚醛樹脂、丙烯酸橡膠、二氧化矽填料、類似物或其組合。保護材料30可與晶圓的表面20b直接接觸（例如，與晶圓的半導體材料直接接觸）。可通過塗布製程（coating process）、疊層製程（lamination process）、類似製程或其組合來形成保護材料30。
參照圖1D，將其上具有保護材料30的半導體晶圓20單體化成各別的晶粒22及各別的保護層32。單體化可包括鋸切（sawing）、切割（dicing）或類似製程。通常，儘管晶粒22可具有不同的電路系統，然而晶粒22包含例如裝置及金屬化圖案等相同的電路系統。晶粒22中的每一者可包括一個或多個邏輯晶粒（例如，中央處理器（central processing unit）、圖形處理單元（graphics processing unit）、系統晶片（system-on-a-chip）、現場可程式設計閘陣列（field-programmable gate array，FPGA）、微控制器或類似物）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒或類似物）、電源管理晶粒（例如，電源管理積體電路（power management integrated circuit，PMIC）晶粒、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，模擬前端（analog front-end，AFE）晶粒）、類似物或其組合。此外，在一些實施例中，晶粒22為不同的尺寸（例如，不同的高度和/或表面積），且在其他實施例中，晶粒22為相同的尺寸（例如，相同的高度和/或表面積）。
晶粒22具有主動表面22a及與主動表面22a相對的表面22b。主動表面22a可為前側表面，且表面22b可為背側表面。每一晶粒22在表面22b上具有保護層32。保護層32的尺寸對晶粒22的尺寸的比率可介於約1.1到約0.95範圍內。在實施例中，保護層32的尺寸是在中介件102（interposer，如圖2C中所示）上的投影面積，且晶粒22的尺寸是在中介件102（如圖2C中所示）上的投影面積。在實施例中，在晶粒22的整個表面22b上形成保護層32。在此種實施例中，保護層32的側壁與晶粒22的側壁實質上齊平。在一些實施例中，晶粒22在其表面22b上具有保護層32，且因此防止晶粒22的表面22b被損壞。
圖2A到圖2H是根據一些實施例的製造半導體封裝的方法中的各種階段的示意性剖視圖。圖3是根據一些實施例的半導體封裝的示意性俯視圖。為例示簡明及清晰起見，在圖3所示俯視圖中僅示出幾個元件。在一些實施例中。圖2G是沿著圖3所示的線I-I截取的半導體封裝的剖視圖。
參照圖2A，提供中介件102。中介件102可包括基底104、多個穿孔106及重佈線結構108、110。在一些實施例中，基底104由例如矽、鍺、金剛石或類似物等元素半導體製成。在其他實施例中，基底104由例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、類似物或其組合等化合物半導體製成。在實施例中，基底104是絕緣體上矽（silicon-on-insulator，SOI）基底。一般來說，SOI基底包括由例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料形成的層。在替代實施例中，基底104由預浸料（其包含環氧樹脂、樹脂、二氧化矽填料和/或玻璃纖維）、味之素增層膜（Ajinomoto Buildup Film，ABF）、樹脂塗布式銅箔（resin coated copper foil，RCC）、聚醯亞胺、感光成像介電質（photo image dielectric，PID）、陶瓷芯、玻璃芯、模制化合物、類似物或其組合製成。
穿孔106穿透基底104。在一些實施例中，穿孔106是由例如鋁、鈦、銅、鎳、鎢、其合金、類似物或其組合等導電材料製成。在基底104的兩側上設置重佈線結構108、110，且將重佈線結構108、110電連接到穿孔106。將重佈線結構108、110形成為連接各種裝置以形成功能電路系統。重佈線結構108、110包括交替堆疊的多個介電層與多個導電圖案化層。介電層可包含氮化矽、碳化矽、氧化矽、低介電常數介電質（low-k dielectric）（例如碳摻雜氧化物）、極低介電常數介電質（extremely low-k dielectric）（例如多孔碳摻雜二氧化矽）、聚合物（例如環氧樹脂、聚醯亞胺、苯併環丁烯（benzocyclobutene，BCB）、聚苯併噁唑（polybenzoxazole，PBO））、類似物或其組合。在一些實施例中，通過化學氣相沉積（CVD）、物理氣相沉積（physical vapor deposition，PVD）、原子層沉積（atomic layer deposition，ALD）、旋塗介電質製程（spin-on-dielectric process）、類似製程或其組合來沉積介電層。導電圖案化層可包含金屬或金屬合金（包括銅、鋁、鎢、類似物或其組合）。在一些實施例中，通過沉積、鑲嵌、雙鑲嵌（dual damascene）或類似製程來形成導電圖案化層。
在一些實施例中，中介件102是包含至少一個功能裝置或積體電路裝置的主動中介件。在一些實例中，此種主動中介件被稱為“含裝置中介件（device-containing interposer）”。在一些實施例中，功能裝置包括主動裝置、被動裝置或其組合。功能裝置可包括電晶體、電容器、電阻器、二極體、光電二極體、熔絲裝置、類似物或其組合。在一些實施例中，功能裝置包括閘極介電層、閘電極、源極/汲極區、間隙壁及類似物。在替代性實施例中，中介件102是被動中介件，其缺少功能裝置或積體電路裝置。在一些實例中，此種被動中介件被稱為“無裝置中介件（device-free interposer）”。
在一些實施例中，在中介件102上形成一個或多個表面裝置120。可通過電連接件122及結合墊112將表面裝置120安裝到重佈線結構108上。結合墊112將隨後結合的表面裝置120電耦合到重佈線結構108。在一些實施例中，結合墊112包括例如通過PVD、CVD、ALD、類似製程或其組合沉積在中介件102之上的薄晶種層（seed layer）（未示出）。晶種層是由銅、鈦、鎳、金、類似物或其組合製成。在一些實施例中，在薄晶種層之上沉積結合墊112的導電材料。在一些實施例中，通過電化學鍍覆製程、CVD、ALD、PVD、類似製程或其組合來形成導電材料。在實施例中，結合墊112的導電材料是銅、鎢、鋁、銀、金、類似物或其組合。
在實施例中，結合墊112是凸塊下金屬（under bump metallurgy，UBM），且包括三個導電材料層（例如鈦層、銅層及鎳層）。然而，用於形成UBM的材料及層的許多合適的佈置方式在本公開的設想範圍內。例如，此種佈置包括合適的鉻/鉻-銅合金/銅/金佈置方式、鈦/鈦鎢/銅佈置方式、銅/鎳/金佈置方式或類似佈置方式。此外，可用於UBM的任何合適的材料或材料層也在本申請的設想範圍內。
在形成結合墊112之後，通過電連接件122及結合墊112將具有電連接件122的表面裝置120結合到中介件102的表面102a。表面裝置120可用於向要形成的封裝結構提供附加的功能性（functionality）或程式設計（programming）。在實施例中，表面裝置120包括表面安裝裝置（surface mount device，SMD）或積體被動裝置（integrated passive device，IPD），且IPD包括例如期望連接到封裝結構且與封裝結構結合使用的電阻器、電感器、電容器、跨接線（jumper）、類似物或其組合等被動裝置。表面裝置120可具有不同的尺寸（例如高度、寬度或其組合）。在實施例中，如圖2A中所示，具有較大尺寸的表面裝置120設置在中介件102的中心區上，且由具有較小尺寸的表面裝置120環繞。然而，本公開不限於此。
將電連接件122結合到表面裝置120上的接觸件或電極。電連接件122可為受控塌陷晶片連接（C4）凸塊、例如球格陣列（BGA）等焊球、金屬柱、無電鍍鎳鈀浸金技術（ENEPIG）形成的凸塊或類似物。電連接件122包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合等導電材料。在電連接件122是焊料凸塊的實施例中，通過例如蒸發、電鍍、印刷、焊料轉移、植球或類似方法等各種方法最初在結合墊112上形成焊料層來形成電連接件122。在此實施例中，一旦已在結合墊112上形成焊料層，就實行回流以將所述材料造型成所期望的凸塊形狀。在一些實施例中，表面裝置120與中介件102之間的結合是焊料結合。在實施例中，通過回流製程將表面裝置120結合到中介件102。在此回流製程期間，電連接件122與結合墊112及表面裝置120接觸，以將表面裝置120物理耦合到及電耦合到中介件102。
在放置表面裝置120之後，在表面裝置120上及表面裝置120周圍模制模制材料130。模制材料130填充表面裝置120之間的間隙。在實施例中，形成模制材料130，且模制材料130填充表面裝置120與重佈線結構108之間的間隙。在一些實施例中，模制材料130是由模制化合物、模制底部填充膠、環氧樹脂、樹脂、類似物或其組合製成。在一些實施例中，提供模具槽（mold chase）（未示出），且模具槽在施加及固化模制材料130的期間對模制材料130進行保持及造型。例如，模具槽具有用於在施加模制材料130時保持模制材料130的邊界或其他特徵。模具槽可包括釋放膜（release film），以幫助將模具槽與模制材料130分開。例如，在模制材料130是環氧樹脂或樹脂的實施例中使用釋放膜，以防止模制化合物材料黏合到模具槽表面。可基於模具槽以及表面裝置120的高度來調整模制材料130的厚度。在實施例中，模制材料130具有在約700 μm到約800 μm之間的厚度。在一些實施例中，模制材料130的表面130a高於表面裝置120的表面120a。即，模制材料130可覆蓋表面裝置120的表面120a。
參照圖2B，將模制材料130部分移除到所需厚度。在實施例中，實行例如研磨製程等薄化製程以將模制材料130薄化，直到獲得所需厚度為止而不暴露出表面裝置120的表面120a。模制材料130可覆蓋表面裝置120的表面120a。在一些實施例中，模制材料130通過壓力板（pressure plate）或模具（未示出）經歷壓力模制製程（pressure molding process），以對模制材料130進行造型。在一些實施例中，在薄化製程之後，模制材料130所具有的厚度介於400 μm到500 μm範圍內。
參照圖2C，將其之上具有表面裝置120及模制材料130的中介件102上下翻轉。然後，將其之上具有保護層32的晶粒22結合到中介件102。在一些實施例中，將圖1D所示晶粒22拾取且放置到中介件102的表面102b上。通過電連接件28及結合墊114將晶粒22結合到中介件102。結合墊114將隨後結合的晶粒22電耦合到重佈線結構110。在一些實施例中，將結合墊116形成為將隨後結合的電連接件146（如圖2G中所示）電耦合到重佈線結構110。在實施例中，同時形成結合墊116與結合墊114。儘管結合墊112、114及116未必相同，然而結合墊114、116可相似於上述結合墊112，且本文中不再予以贅述。
在一些實施例中，晶粒22與中介件102之間的結合是焊料結合或直接金屬對金屬結合（例如銅對銅結合或錫對錫結合）。在實施例中，通過回流製程將晶粒22結合到中介件102。在此回流製程期間，電連接件28與結合墊114及晶粒22接觸，以將晶粒22物理耦合到及電耦合到中介件102。
在一些實施例中，保護層32的尺寸（例如，在中介件102上的投影面積）對中介件102的尺寸（例如，中介件102的表面102b的面積）的比率介於約0.5到約0.9範圍內。在此種實施例中，如圖3中所示，保護層32的面積等於保護層32的寬度W1與長度L1的乘積，且中介件102的表面102b的面積等於中介件102的寬度W2與長度L2的乘積。在一些實施例中，在中介件102的表面102b的中心區上設置晶粒22。即，晶粒22的第一側壁S1及中介件102的第一側壁S1’之間的水平距離d1與晶粒22的和第一側壁S1相對的第二側壁S2及中介件102的和第一側壁S1’相對的第二側壁S2’之間的水平距離d1’實質上相同。相似地，晶粒22的第三側壁S3及中介件102的第三側壁S3’之間的水平距離d2與晶粒22的和第三側壁S3相對的第四側壁S4及中介件102的和第三側壁S3’相對的第四側壁S4’之間的水平距離d2’實質上相同。然而，本公開不限於此。
晶粒22具有厚度t1，且保護層32具有厚度t2。厚度t1可為晶粒22的厚度（如圖2C中所示）或者晶粒22與其上的電連接件28的總厚度。在一些實施例中，保護層32的厚度t2對晶粒22的厚度t1的比率介於約5%到約50%範圍內。在實施例中，厚度t1不大於80 μm，厚度t2不大於30 μm。在實施例中，晶粒22的厚度t1介於約100 μm到約300 μm範圍內，且厚度t2介於約5 μm到約50 μm範圍內。
參照圖2D，在結合晶粒22之後，在晶粒22上及晶粒22周圍模制模制材料140。模制材料140包封晶粒22且填充電連接件28之間的間隙。在實施例中，形成模制材料140，且模制材料140填充晶粒22與重佈線結構110之間的間隙。在一些實施例中，模制材料140是由模制化合物、模制底部填充膠、環氧樹脂、樹脂、類似物或其組合製成。儘管模制材料130與140未必相同，然而模制材料140可相似於上述模制材料130，且本文中不再予以贅述。可基於模具槽以及晶粒22的高度來調整模制材料140的厚度。在實施例中，模制材料140具有在約400 μm到約500 μm之間的厚度。在一些實施例中，模制材料140的表面140a高於保護層32的表面32a。換句話說，模制材料140覆蓋保護層32的表面32a。
參照圖2E，將模制材料140部分移除以暴露出保護層32。在實施例中，實行例如研磨製程等薄化製程以將模制材料140薄化，直到模制材料140的表面140a與保護層32的表面32a實質上共面為止。在實施例中，保護層32實質上沒有通過薄化製程移除，在薄化製程之後模制材料140所具有的厚度實質上等於晶粒22的厚度t1與保護層32的厚度t2的總和。在替代性實施例中，保護層32通過薄化製程被部分移除，而晶粒22保持完整而沒有被移除。在薄化製程期間，晶粒22由保護層32保護而免受損壞。因此，防止由薄化製程導致在晶粒22的表面22b上形成研磨痕跡（grinding mark），且增強了晶粒強度。
參照圖2F，在模制材料140中形成多個開口142以暴露出結合墊116。在一些實施例中，通過雷射燒蝕或鑽孔製程（laser ablation or drilling process）、蝕刻製程、類似製程或其組合來形成開口142。開口142可具有不垂直及不平行於中介件102的表面102b的側壁144，且側壁144可彼此不同。
參照圖2G，在開口142中形成多個電連接件146，以電連接到結合墊116。在實施例中，儘管可替代地使用任何合適的材料，然而電連接件146是包含例如焊料等共晶材料（eutectic material）的球格陣列（BGA）。在電連接件146是焊料凸塊的實施例中，使用例如直接落球製程（direct ball drop process）等落球方法來形成電連接件146。在另一實施例中，通過例如蒸發、電鍍、印刷、焊料轉移等任何合適的方法最初形成錫層、且然後實行回流以便將所述材料造型成所期望的凸塊形狀來形成焊料凸塊。在一些實施例中，電連接件146從模制材料140突出。例如，電連接件146的表面146a高於保護層32的表面32a。在替代性實施例中，通過多個步驟來形成電連接件146。詳細來說，在結合墊116上形成第一電連接件（未示出），且形成模制材料140並將模制材料140圖案化以暴露出第一電連接件。然後，在第一電連接件上形成第二電連接件，且通過回流製程將第二電連接件與第一電連接件接合以形成電連接件146。
參照圖2H，進一步將圖2G所示結構貼合到具有電路結構的基底200，以形成半導體封裝10。在一些實施例中，通過電連接件146將圖2G所示結構結合到具有電路結構的基底200。具有電路結構的基底200可為封裝基底、另一晶粒/晶圓、印刷電路板、高密度內連線或類似物。具有電路結構的基底200可包括基底202、穿孔204、重佈線結構206、208及電連接件210。穿孔204穿透基底202。重佈線結構206、208設置在基底202的相對兩側上，且重佈線結構206、208通過穿孔204彼此電連接。電連接件210相對於基底202與中介件102相對設置，且可轉而連接到另一基底（未示出）。
在一些實施例中，具有電路結構的基底200包括空腔212，進而使得晶粒22延伸到形成在下伏的具有電路結構的基底200中的空腔212中。在一些實施例中，在保護層32與具有電路結構的基底200之間形成間隙214。由於具有空腔212，防止保護層32與具有電路結構的基底200接觸。在此種實施例中，由於電連接件146的尺寸不再需要大於晶粒22與保護層32的總厚度，因此電連接件146的尺寸可能小於使用不具有空腔的基底時的電連接件146的尺寸。因此，更薄的總體封裝是可能的。然而，本公開不限於此。在替代性實施例中，由於保護層32是不導電的，因此保護層32與具有電路結構的基底200接觸，即不在晶粒22與具有電路結構的基底200之間形成間隙。在省略空腔的替代性實施例中，電連接件146具有更大的高度，以維持具有電路結構的基底200與晶粒22之間的間隙。
在一些實施例中，在薄化製程期間，晶粒22的表面22b由保護層32保護以免被暴露出和/或損壞。因此，防止由薄化製程導致在晶粒22上形成研磨痕跡，且增強了晶粒強度。因此，當實行例如回流製程等熱製程和/或施加外力時，晶粒22免於開裂。
圖4示出根據一些實施例的製造半導體封裝的方法。儘管所述方法被示出和/或闡述為一系列動作或事件，然而應理解，所述方法不限於所示出的次序或動作。因此，在一些實施例中，所述動作以與所示出的次序不同的次序來施行和/或同時施行。此外，在一些實施例中，所示出的動作或事件被細分成多個動作或事件，這些動作或事件可在分開的時間施行或者與其他動作或子動作同時施行。在一些實施例中，省略一些所示出的動作或事件，且包括其他未示出的動作或事件。
在動作302處，將晶粒結合到中介件上以電連接到中介件，其中晶粒上具有保護層，且晶粒設置在保護層與中介件之間。圖2A示出對應於動作302的一些實施例的剖視圖。
在動作304處，在中介件之上形成模制材料以包封晶粒，其中第一模制材料覆蓋保護層。圖2D示出對應於動作304的一些實施例的剖視圖。
在動作306處，在晶粒由保護層保護的同時，對模制材料進行薄化。圖2E示出對應於動作306的一些實施例的剖視圖。
在一些實施例中，還包括將中介件結合到具有電路結構的基底上，其中晶粒設置在中介件與具有電路結構的基底之間。圖2H示出對應於此動作的一些實施例的剖視圖。
圖5所示半導體封裝10可相似於圖2H所示半導體封裝10，且其之間的不同之處在於，圖2C中的保護層32是在對模制材料140實行薄化製程之前形成，而圖5中的保護層32是在對模制材料140實行薄化製程之後形成。在此種實施例中，對模制材料140進行薄化，直到模制材料140的表面140a與晶粒22的表面22b實質上共面為止。在薄化製程之後，在晶粒22的表面22b上形成保護層32。因此，保護層32的表面32a從模制材料140的表面140a突出。在此種實施例中，通過塗布製程、疊層製程、類似製程或其組合來形成保護層32。在一些實施例中，當實行例如回流製程等熱製程和/或施加外力時，保護層32保護晶粒22免於開裂。
在一些實施例中，晶粒的背側表面由保護層保護以免被暴露出和/或損壞。因此，防止由薄化製程導致在晶粒上形成研磨痕跡，且增強了晶粒強度。因此，當實行例如回流製程等熱製程和/或施加外力時，晶粒免於開裂。因此，包括晶粒的半導體封裝可具有良好的性能。
根據本公開的一些實施例，一種半導體封裝包括中介件、晶粒、保護層、多個第一電連接件及第一模制材料。晶粒包括第一表面及與第一表面相對的第二表面，且晶粒通過第一表面結合到中介件。保護層設置在晶粒的第二表面上。第一電連接件位於晶粒旁邊。第一模制材料設置在晶粒、保護層及第一電連接件旁邊。
根據本公開的一些實施例，一種半導體封裝包括中介件、晶粒及具有電路結構的基底。晶粒結合到且電連接到中介件，且晶粒上具有保護層。中介件結合到且電連接到具有電路結構的基底，且晶粒設置在中介件與具有電路結構的基底之間且通過中介件電連接到具有電路結構的基底。
根據本公開的一些實施例，一種製造半導體封裝的方法包括以下步驟。將晶粒結合到中介件上以電連接到中介件，其中晶粒上具有保護層，且晶粒設置在保護層與中介件之間。在中介件之上形成第一模制材料以包封晶粒，其中第一模制材料覆蓋保護層。在晶粒由保護層保護的同時，對第一模制材料進行薄化。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的方面。所屬領域中的技術人員應理解，其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文所介紹的實施例相同的目的和/或實現與本文所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，此種等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
10:半導體封裝 20:半導體晶圓 20a,22a:主動表面 20b,22b,32a,102a,102b,120a,130a,140a,146a:表面 22:晶粒 24:內連線結構 26:結合墊 28:電連接件 30:保護材料 32:保護層 102:中介件 104,202:基底 106,204:穿孔 108,110,206,208:重佈線結構 112,114,116:結合墊 120:表面裝置 122,146,210:電連接件 130,140:模制材料 142:開口 144:側壁 200:具有電路結構的基底 212:空腔 214:間隙 302,304,306:動作 d1,d1’,d2,d2’:水平距離 S1,S1’:第一側壁 S2,S2’:第二側壁 S3,S3’:第三側壁 S4,S4’:第四側壁 t1,t2:厚度
圖1A到圖1D是根據一些實施例的形成晶粒的方法中的各種階段的示意性剖視圖。 圖2A到圖2H是根據一些實施例的製造半導體封裝的方法中的各種階段的示意性剖視圖。 圖3是根據一些實施例的半導體封裝的示意性俯視圖。 圖4示出根據一些實施例的製造半導體封裝的方法。 圖5是根據一些實施例的半導體封裝的示意性剖視圖。
10:半導體封裝
22:晶粒
24:內連線結構
26:結合墊
28:電連接件
32:保護層
102:中介件
104,202:基底
106,204:穿孔
108,110,206,208:重佈線結構
112,114,116:結合墊
120:表面裝置
122,146,210:電連接件
130,140:模制材料
140a:表面
200:具有電路結構的基底
212:空腔
214:間隙

Claims (20)

  1. 一種半導體封裝，包括： 中介件； 晶粒，包括第一表面及與所述第一表面相對的第二表面，所述晶粒通過所述第一表面結合到所述中介件； 保護層，設置在所述晶粒的所述第二表面上； 多個第一電連接件，位於所述晶粒旁邊；以及 第一模制材料，設置在所述晶粒、所述保護層及所述第一電連接件旁邊。
  2. 如請求項1所述的半導體封裝，其中所述第一模制材料的表面與所述保護層的表面實質上共面。
  3. 如請求項1所述的半導體封裝，其中所述保護層從所述第一模制材料突出。
  4. 如請求項1所述的半導體封裝，其中所述第一電連接件從所述第一模制材料突出。
  5. 如請求項1所述的半導體封裝，其中所述保護層的材料不同於所述第一模制材料的材料。
  6. 如請求項1所述的半導體封裝，進一步包括至少一個表面安裝裝置，其中所述至少一個表面安裝裝置相對於所述中介件與所述晶粒相對設置。
  7. 如請求項5所述的半導體封裝，進一步包括包封及覆蓋所述至少一個表面安裝裝置的第二模制材料。
  8. 如請求項1所述的半導體封裝，其中所述晶粒包括位於所述第一表面上的多個第二電連接件，且所述晶粒通過所述第二電連接件結合到且電連接到所述中介件。
  9. 一種半導體封裝，包括： 中介件； 晶粒，結合到且電連接到所述中介件，所述晶粒上具有保護層；以及 具有電路結構的基底，其中所述中介件結合到且電連接到所述具有電路結構的基底，且所述晶粒設置在所述中介件與所述具有電路結構的基底之間且通過所述中介件電連接到所述具有電路結構的基底。
  10. 如請求項9所述的半導體封裝，其中所述保護層設置在所述晶粒與所述具有電路結構的基底之間，且所述保護層通過間隙與所述具有電路結構的基底分離。
  11. 如請求項9所述的半導體封裝，進一步包括至少一個表面安裝裝置，其中所述至少一個表面安裝裝置相對於所述中介件與所述晶粒相對設置。
  12. 如請求項9所述的半導體封裝，進一步包括包封所述晶粒的第一模制材料及相對於所述中介件與所述第一模制材料相對設置的第二模制材料，其中所述第一模制材料的側壁與所述第二模制材料的側壁實質上齊平。
  13. 如請求項9所述的半導體封裝，其中所述晶粒設置在所述具有電路結構的基底的空腔中，而不與所述具有電路結構的基底直接接觸。
  14. 如請求項9所述的半導體封裝，其中所述保護層的側壁與所述晶粒的側壁實質上齊平。
  15. 如請求項9所述的半導體封裝，其中所述晶粒通過多個第一電連接件結合到所述中介件，所述中介件通過多個第二電連接件結合到所述具有電路結構的基底，且所述第二電連接件環繞所述第一電連接件。
  16. 一種製造半導體封裝的方法，包括： 將晶粒結合到中介件上以電連接到所述中介件，其中所述晶粒上具有保護層，且所述晶粒設置在所述保護層與所述中介件之間； 在所述中介件之上形成第一模制材料以包封所述晶粒，其中所述第一模制材料覆蓋所述保護層；以及 在所述晶粒由所述保護層保護的同時，對所述第一模制材料進行薄化。
  17. 如請求項16所述的方法，其中所述第一模制材料的表面與所述保護層的表面實質上共面。
  18. 如請求項16所述的方法，進一步包括在所述第一模制材料中形成多個電連接件以環繞所述晶粒。
  19. 如請求項16所述的方法，進一步包括將所述中介件結合到具有電路結構的基底上，其中所述晶粒設置在所述中介件與所述具有電路結構的基底之間。
  20. 如請求項16所述的方法，進一步包括： 將至少一個表面安裝裝置結合到所述中介件上，其中所述至少一個表面安裝裝置相對於所述中介件與所述晶粒相對設置；以及 在所述中介件之上形成第二模制材料以包封所述至少一個表面安裝裝置。
TW109143341A 2020-10-21 2020-12-09 半導體封裝及製造半導體封裝的方法 TWI765455B (zh)

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