TWI778691B - 積體電路封裝及其製造方法 - Google Patents

積體電路封裝及其製造方法 Download PDF

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TWI778691B
TWI778691B TW110124352A TW110124352A TWI778691B TW I778691 B TWI778691 B TW I778691B TW 110124352 A TW110124352 A TW 110124352A TW 110124352 A TW110124352 A TW 110124352A TW I778691 B TWI778691 B TW I778691B
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Taiwan
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die
integrated circuit
top surface
circuit element
heat dissipation
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TW110124352A
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TW202238864A (zh
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陳憲偉
陳明發
葉松峯
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台灣積體電路製造股份有限公司
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Abstract

一種元件包含：中介層；第一積體電路元件，附接至中介 層；第二積體電路元件，附接至中介層，第二積體電路元件鄰近第一積體電路元件；散熱晶粒，位於第二積體電路元件上；以及密封體，圍繞散熱晶粒、第二積體電路元件以及第一積體電路元件，密封體的頂表面與散熱晶粒的頂表面及第一積體電路元件的頂表面共面。

Description

積體電路封裝及其製造方法
本發明實施例是有關於一種積體電路封裝及其製造方法。
半導體行業歸因於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)的整合密度的持續改良而經歷快速增長。主要地，整合密度的改良由最小特徵大小的迭代減小引起，此允許將更多組件整合至給定區域中。隨著對於縮小電子元件的需求增長，已出現對於更小且更具創造性的半導體晶粒的封裝技術的需求。
本發明實施例的一種積體電路封裝包含：中介層；第一積體電路元件，附接至中介層；第二積體電路元件，附接至中介層，第二積體電路元件鄰近第一積體電路元件；散熱晶粒，位於第二積體電路元件上；以及密封體，圍繞散熱晶粒、第二積體電路元件以及第一積體電路元件，密封體的頂表面與散熱晶粒的頂表面及第一積體電路元件的頂表面共面。
本發明實施例的一種元件包含：中介層；第一晶粒堆疊， 接合至中介層的前側；第二晶粒堆疊，接合至中介層的前側，第二晶粒堆疊的頂表面安置成比第一晶粒堆疊的頂表面更接近於中介層；散熱晶粒，位於第二晶粒堆疊上，散熱晶粒的頂表面安置成與第一晶粒堆疊的頂表面距中介層相同距離；以及散熱片，位於散熱晶粒的頂表面及第二晶粒堆疊的頂表面上。
本發明實施例的一種方法包含：將第一積體電路元件及第二積體電路元件接合至中介層的前側；將散熱晶粒附著於第一積體電路元件上；用密封體密封散熱晶粒、第一積體電路元件以及第二積體電路元件；薄化密封體及散熱晶粒以及第二積體電路元件直至密封體的頂表面與散熱晶粒的頂表面及第一積體電路元件的頂表面共面為止；以及將散熱片附著至密封體的頂表面、散熱晶粒的頂表面以及第二積體電路元件的頂表面。
50:積體電路晶粒
50A:第一積體電路晶粒
50B:第二積體電路晶粒
50F、70F:前側
52:半導體基底
54、74:內連線結構
56:晶粒連接件
58、312:介電層
60A、60B:晶粒堆疊
62、76、302:導通孔
64:對準標記
70、300、400:晶圓
70A:封裝區
70B、400B:背側
72:基底
80:積體電路元件
80A:第一積體電路元件
80B:第二積體電路元件
82、106:導電連接件
84、206:底部填充劑
92、210:黏著層
92A:第一黏著層
92B:第二黏著層
92C:第三黏著層
94:散熱晶粒
94A:下部散熱晶粒
94B:中間散熱晶粒
94C:上部散熱晶粒
96、304、404:密封體
98、406:載體基底
102、408:絕緣層
104:凸塊下冶金
110:中介層
150:積體電路封裝
200:封裝基底
202:基底芯
204:接合墊
208:散熱片
300A、400A:晶粒區
306:障壁層
310、410:重佈線結構
314:金屬化層
316:凸塊下金屬化物
D1、D2、D3、D4:差
G1:間隙
T1、T2、T3、T4:厚度
TC:組合厚度
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本揭露內容的態樣。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。實際上，為了論述的清楚起見，可任意增大或減小各種特徵的尺寸。
圖1為積體電路晶粒的橫截面圖。
圖2A至圖2B為根據一些實施例的晶粒堆疊的橫截面圖。
圖3至圖11為根據一些實施例的積體電路封裝的製造中的中間階段的橫截面圖。
圖12至圖15為根據一些實施例的積體電路封裝的橫截面圖。
圖16至圖19為根據一些實施例的晶粒堆疊的製造中的中間階段的橫截面圖。
圖20及圖23為根據一些實施例的積體電路封裝的橫截面圖。
圖24至圖29為根據一些實施例的晶粒堆疊的製造中的中間階段的橫截面圖。
圖30至圖33為根據一些實施例的積體電路封裝的橫截面圖。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或在第二特徵上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清晰的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，為易於描述，本文中可使用諸如「在...下方」、「在...之下」、「下部」、「在...之上」、「上部」以及類似者的空間相對術語來描述如諸圖中所示出的一個部件或特徵與另一部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。元件可以其他方式定向(旋轉90度或 處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
根據各種實施例，形成積體電路封裝，所述積體電路封裝包含各種厚度的積體電路元件及積體電路元件上方的具有較小厚度的散熱晶粒。散熱晶粒經由形成在積體電路元件周圍的密封體而暴露。散熱晶粒的設置減少了具有較小厚度的積體電路元件上方的密封體的量，其可有助於避免積體電路封裝中的應力集中及晶粒破裂。此外，散熱片可附接至散熱晶粒的頂表面，其可有助於改良積體電路封裝中的熱耗散效率。
圖1為積體電路晶粒50的橫截面圖。多個積體電路晶粒50將在後續處理中封裝以形成積體電路封裝。每一積體電路晶粒50可為邏輯晶粒(例如，中央處理單元(central processing unit；CPU)、圖形處理單元(graphics processing unit；GPU)、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取記憶體(static random access memory；SRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit；PMIC)晶粒)、射頻(radio frequency；RF)晶粒、介面晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、信號處理晶粒(例如，數位信號處理(digital signal processing；DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end；AFE)晶粒)類似者或其組合(例如，系統單晶片(system-on-a-chip；SoC)晶粒)。積體電路晶粒50可形成於晶圓中，所述晶圓可包含在後續步驟中單體化以形成多個積體電路晶粒50的不同晶粒區。積體電 路晶粒50包含半導體基底52、內連線結構54、晶粒連接件56以及介電層58。
半導體基底52可為經摻雜的或未經摻雜的矽基底，或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底52可包含其他半導體材料，諸如：鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦以及/或銻化銦；合金半導體，包含矽-鍺、砷化鎵磷化物、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵以及/或砷化銦鎵磷化物；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。半導體基底52具有主動表面(例如，圖1中的朝上的表面)及非主動表面(例如，圖1中的朝下的表面)。元件位於半導體基底52的主動表面處。元件可為主動元件(例如，電晶體、二極體等)、電容器、電阻器等。非主動表面可不含元件。
內連線結構54位於半導體基底52的主動表面上方，且用以電性連接半導體基底52的元件以形成積體電路。內連線結構54可包含一或多個介電層及介電層中的各別金屬化層。用於介電層的可接受的介電材料包含：氧化物(諸如，氧化矽或氧化鋁)；氮化物(諸如，氮化矽)；碳化物(諸如，碳化矽)；類似者；或其組合(諸如，氮氧化矽、碳氧化矽、碳氮化矽、氧碳氮化矽或類似者)。亦可使用其他介電材料，諸如聚合物(諸如，聚苯并噁唑(polybenzoxazole；PBO))、聚醯亞胺、苯環丁烷(benzocyclobuten；BCB)類聚合物或類似者。金屬化層可包含導通孔及/或導電線以使半導體基底52的元件互連。金屬化層可由諸如金屬(諸如，銅、鈷、鋁、金、其組合或類似者)的導電材料形成。內連線結構54 可藉由鑲嵌(damascene)製程(諸如，單鑲嵌製程、雙鑲嵌製程或類似者)形成。
晶粒連接件56位於積體電路晶粒50的前側50F處。晶粒連接件56可為進行外部連接的導電柱、接墊或類似者。晶粒連接件56位於內連線結構54中及/或內連線結構54上。舉例而言，晶粒連接件56可為內連線結構54的上部金屬化層的部分。晶粒連接件56可由諸如銅、鋁或類似者的金屬形成，且可藉由例如鍍覆或類似者來形成。
視情況，在積體電路晶粒50的形成期間，焊料區(未單獨示出)可安置於晶粒連接件56上。焊料區可用以對積體電路晶粒50執行晶片探針(chip probe；CP)測試。舉例而言，焊料區可為焊料球、焊料凸塊或類似者，其用以將晶片探針附接至晶粒連接件56。可對積體電路晶粒50執行晶片探針測試以確定積體電路晶粒50是否為良裸晶粒(known good die；KGD)。因此，僅封裝經歷後續處理的積體電路晶粒50(其為KGD)，且並不封裝晶片探針測試失敗的晶粒。在測試之後，可在後續處理步驟中移除焊料區。
介電層58位於積體電路晶粒50的前側50F處。介電層58位於內連線結構54中及/或內連線結構54上。舉例而言，介電層58可為內連線結構54的上部介電層。介電層58橫向地密封晶粒連接件56。介電層58可為氧化物、氮化物、碳化物、聚合物、類似者或其組合。介電層58可例如藉由旋塗、層壓、化學氣相沈積(chemical vapor deposition；CVD)或類似者形成。初始地，介電層58可內埋晶粒連接件56，使得介電層58的頂表面位於晶粒 連接件56的頂表面之上。在積體電路晶粒50的形成期間，經由介電層58暴露晶粒連接件56。暴露晶粒連接件56可移除可能存在於晶粒連接件56上的任何焊料區。移除製程可應用於各種層以移除晶粒連接件56上方的多餘材料。移除製程可為平坦化製程，諸如化學機械拋光(chemical mechanical polish；CMP)、回蝕、其組合或類似者。在平坦化製程之後，晶粒連接件56及介電層58的頂表面為共面的(在製程變化內)且在積體電路晶粒50的前側50F處暴露。
圖2A至圖2B為根據一些實施例的晶粒堆疊(die stack)60A、晶粒堆疊60B的橫截面圖。晶粒堆疊60A、晶粒堆疊60B可各自具有單個功能(例如，邏輯元件、記憶體晶粒等)或可具有多個功能。在一些實施例中，晶粒堆疊60A為諸如系統上積體晶片(system-on-integrated-chip；SoIC)元件等邏輯元件，且晶粒堆疊60B為諸如高頻寬記憶體(high bandwidth memory；HBM)元件等記憶體元件。
如圖2A中所繪示，晶粒堆疊60A包含兩個接合的積體電路晶粒50(例如，第一積體電路晶粒50A及第二積體電路晶粒50B)。在一些實施例中，第一積體電路晶粒50A為邏輯晶粒，且第二積體電路晶粒50B為介面晶粒。介面晶粒將邏輯晶粒橋接至記憶體晶粒，且在邏輯晶粒與記憶體晶粒之間轉譯命令。在一些實施例中，接合第一積體電路晶粒50A與第二積體電路晶粒50B，使得主動表面面向彼此(例如，「面對面」接合)。導通孔62可形成以穿過積體電路晶粒50中的一者，使得可對晶粒堆疊60A進行外部連接。導通孔62可為基底穿孔(through-substrate via；TSV)， 諸如矽穿孔或類似者。在所繪示的實施例中，導通孔62形成於第二積體電路晶粒50B(例如，介面晶粒)中。導通孔62延伸穿過對應的積體電路晶粒50的半導體基底52，以實體地及電性連接至內連線結構54的金屬化層。將隨後描述形成晶粒堆疊60A的方法。
如圖2B中所繪示，晶粒堆疊60B為包含多個半導體基底52的堆疊元件。舉例而言，晶粒堆疊60B可為包含多個記憶體晶粒的記憶體元件，諸如混合記憶體立方體(hybrid memory cube；HMC)元件、高頻寬記憶體(HBM)元件或類似者。半導體基底52中的每一者可(或可不)具有單獨的內連線結構54。半導體基底52由導通孔62連接。
圖3至圖11為根據一些實施例的積體電路封裝的製造中的中間階段的橫截面圖。具體而言，積體電路封裝150藉由將積體電路元件80接合至晶圓70而形成。在實施例中，積體電路封裝150為晶圓上晶片(chip-on-wafer；CoW)封裝，但應瞭解，實施例可應用於其他三維積體電路(three-dimensional integrated circuit；3DIC)封裝。晶圓70具有封裝區70A，所述封裝區70A包含形成於其中的元件，諸如中介層110。封裝區70A將在後續處理中單體化以形成積體電路封裝150，所述積體電路封裝150包含晶圓70的單體化部分(例如，中介層110)及接合至晶圓70的單體化部分的積體電路元件80。接著將積體電路封裝150安裝至封裝基底200。在實施例中，所得封裝為基底上晶圓上晶片(chip-on-wafer-on-substrate；CoWoS)封裝，但應瞭解，實施例可應用於其他3DIC封裝。
示出晶圓70的一個封裝區70A的處理。應瞭解，晶圓70的任何數目個封裝區70A可同時經處理及單體化以自晶圓70的單體化部分形成多個積體電路封裝150。
在圖3中，獲得或形成晶圓70。晶圓70包括封裝區70A中的元件，所述元件將在後續處理中單體化以包含於積體電路封裝150中。晶圓70中的元件可為中介層、積體電路晶粒，或類似者。在一些實施例中，中介層110形成於晶圓70中，所述晶圓70包含基底72、內連線結構74以及導通孔76。
基底72可為塊狀半導體基底、絕緣層上半導體(SOI)基底、多層半導體基底或類似者。基底72可包含半導體材料，諸如：矽；鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦以及/或銻化銦；合金半導體，包含矽-鍺、砷化鎵磷化物、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵以及/或砷化銦鎵磷化物；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。基底72可經摻雜或未經摻雜。在中介層形成於晶圓70中的實施例中，基底72通常在其中不包含主動元件，但中介層可包含形成於基底72的前表面(例如，圖3中的朝上的表面)中及/或基底72的前表面上的被動元件。在積體電路元件形成於晶圓70中的實施例中，主動元件(諸如，電晶體、電容器、電阻器、二極體以及類似者)可形成於基底72的前表面中及/或基底72的前表面上。
內連線結構74位於基底72的前表面上方，且用以電性連接基底72的元件(若存在)。內連線結構74可包含一或多個介電層及介電層中的各別金屬化層。用於介電層的可接受的介電材 料包含：氧化物(諸如，氧化矽或氧化鋁)；氮化物(諸如，氮化矽)；碳化物(諸如，碳化矽)；類似者；或其組合(諸如，氮氧化矽、碳氧化矽、碳氮化矽、氧碳氮化矽或類似者)。亦可使用其他介電材料，諸如聚合物(諸如，聚苯并噁唑(PBO))、聚醯亞胺、苯環丁烷(BCB)類聚合物或類似者。金屬化層可包含導通孔及/或導電線以將任何元件互連在一起及/或互連至外部元件。金屬化層可由諸如金屬(諸如，銅、鈷、鋁、金、其組合或類似者)的導電材料形成。內連線結構74可藉由鑲嵌製程(諸如，單鑲嵌製程、雙鑲嵌製程或類似者)形成。
在一些實施例中，晶粒連接件及介電層(未單獨示出)位於晶圓70的前側70F處。具體而言，晶圓70可包含晶粒連接件及介電層，其類似於針對圖1所描述的積體電路晶粒50的彼等。舉例而言，晶粒連接件及介電層可為內連線結構74的上部金屬化層的部分。
導通孔76延伸至內連線結構74及/或基底72中。導通孔76電性連接至內連線結構74的金屬化層。導通孔76有時亦稱為TSV。作為形成導通孔76的實例，凹部可藉由例如蝕刻、研磨、雷射技術、其組合及/或類似者形成於內連線結構74及/或基底72中。薄介電材料可諸如藉由使用氧化技術而形成於凹部中。薄障壁層可諸如藉由CVD、原子層沈積(atomic layer deposition；ALD)、物理氣相沈積(physical vapor deposition；PVD)、熱氧化、其組合及/或類似者而保形地(conformally)沈積於開口中。障壁層可由氧化物、氮化物、碳化物、其組合或類似者形成。導電材料可沈積於障壁層上方及開口中。導電材料可藉由電化學鍍覆製程、CVD、 ALD、PVD、其組合以及/或類似者形成。導電材料的實例為銅、鎢、鋁、銀、金、其組合以及/或類似者。多餘導電材料及障壁層藉由例如CMP自內連線結構74或基底72的表面移除。障壁層及導電材料的剩餘部分形成導通孔76。
在圖4中，積體電路元件80(例如，第一積體電路元件80A及多個第二積體電路元件80B)附接至晶圓70。所需類型及數量的積體電路元件80附接於封裝區70A中。在所繪示的實施例中，包含第一積體電路元件80A及第二積體電路元件80B的多個積體電路元件80鄰近彼此置放，其中第一積體電路元件80A在第二積體電路元件80B之間。第一積體電路元件80A可具有與第二積體電路元件80B不同的功能。第一積體電路元件80A可為邏輯元件，諸如中央處理單元(CPU)、圖形處理單元(GPU)、系統單晶片(SoC)、微控制器或類似者。第二積體電路元件80B可為記憶體元件，諸如動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒、混合記憶體立方體(HMC)模組、高頻寬記憶體(HBM)模組，或類似者。第一積體電路元件80A及第二積體電路元件80B可形成於相同技術節點的製程中，或可形成於不同技術節點的製程中。舉例而言，第一積體電路元件80A可屬於比第二積體電路元件80B更高級的製程節點。
在所示出的實施例中，積體電路元件80使用焊料接合(諸如，用導電連接件82)附接至晶圓70。積體電路元件80可使用例如取放工具置放於內連線結構74上。導電連接件82可由可回焊的導電材料形成，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件82藉由經由諸如蒸 發、電鍍、印刷、焊料轉移、植球或類似者的方法初始地形成焊料層來形成。一旦焊料層已形成於結構上，便可執行回焊以便將導電連接件82塑形成所需凸塊形狀。將積體電路元件80附接至晶圓70可包含將積體電路元件80置放於晶圓70上及回焊導電連接件82。導電連接件82在晶圓70的對應晶粒連接件與積體電路元件80之間形成接合點，從而將中介層110電性連接至積體電路元件80。
底部填充劑84可形成在導電連接件82周圍，及晶圓70與積體電路元件80之間。底部填充劑84可減小應力且保護由導電連接件82的回焊產生的接合點。底部填充劑84可由底部填充劑材料形成，諸如模製化合物、環氧樹脂或類似者。底部填充劑84可在積體電路元件80附接至晶圓70之後藉由毛細流動製程而形成，或可在積體電路元件80附接至晶圓70之前藉由適合的沈積方法而形成。底部填充劑84可以液體或半液體形式施加且接著隨後固化。
在其他實施例(針對圖15所描述)中，積體電路元件80使用直接接合附接至晶圓70。舉例而言，混合接合、熔融接合、介電接合、金屬接合或類似者可在不使用黏著劑或焊料的情況下用以直接接合晶圓70及積體電路元件80的對應介電層及/或晶粒連接件。當使用直接接合時，可省略底部填充劑84。此外，可使用混合接合技術，例如，一些積體電路元件80可藉由焊料接合附接至晶圓70，且其他積體電路元件80可藉由直接接合附接至晶圓70。
積體電路元件80A可為積體電路晶粒(類似於針對圖1 所描述的積體電路晶粒50)，或可為晶粒堆疊(類似於針對圖2A所描述的晶粒堆疊60A)。在此實施例中，第一積體電路元件80A為積體電路晶粒。在其他實施例(隨後更詳細地描述)中，第一積體電路元件80A為晶粒堆疊。
積體電路元件80B可為積體電路晶粒(類似於針對圖1所描述的積體電路晶粒50)，或可為晶粒堆疊(類似於針對圖2B所描述的晶粒堆疊60B)。在此實施例中，第一積體電路元件80B為晶粒堆疊。晶粒堆疊，且尤其諸如高頻寬記憶體(HBM)元件的記憶體晶粒堆疊由於具有多個半導體基底而具有較大厚度。舉例而言，高容量HBM元件可具有十二個或大於十二個半導體基底。當第二積體電路元件80B為記憶體晶粒堆疊時，其可具有比第一積體電路元件80A更大的厚度。舉例而言，第一積體電路元件80A可具有在200微米至775微米的範圍內的厚度T1，且第二積體電路元件80B可各自具有在300微米至1000微米的範圍內的厚度T2，其中厚度T1與厚度T2之間的差D1在50微米至800微米的範圍內。因此，第二積體電路元件80B的頂表面安置成比第一積體電路元件80A的頂表面距晶圓70更遠。因此，間隙G1存在於第一積體電路元件80A上方，其中間隙G1由第一積體電路元件80A的頂表面與第二積體電路元件80B的頂表面之間的區域界定。
在圖5中，散熱晶粒94附接至第一積體電路元件80A。散熱晶粒94包含塊狀基底，且可不包含元件、金屬化層或類似者。散熱晶粒94由具有高導熱性的材料形成，諸如矽、陶瓷、導熱玻璃，諸如銅或鐵的金屬或類似者。在一些實施例中，散熱晶粒94 由在CMP期間產生少量殘餘物的材料(諸如，矽)形成。散熱晶粒94亦可稱為虛擬(dummy)晶粒或熱增強(thermal enhancement)晶粒。
在一些實施例中，黏著層92用以將散熱晶粒94黏著至第一積體電路元件80A。黏著層92可為熱介面材料(thermal interface material；TIM)、晶粒附接膜(die attach film；DAF)或類似者。舉例而言，黏著層92可由諸如聚合材料、焊錫、銦焊錫或類似者的TIM形成，所述TIM可施配於第一積體電路元件80A及/或散熱晶粒94上。散熱晶粒94亦可藉由其他技術附接至第一積體電路元件80A。
黏著層92(若存在)及散熱晶粒94可具有若干寬度。在此實施例中，黏著層92及散熱晶粒94具有與第一積體電路元件80A相同的寬度，使得第一積體電路元件80A、黏著層92以及散熱晶粒94的外側壁橫向地相連。在其他實施例(隨後更詳細地描述)中，黏著層92及散熱晶粒94具有比第一積體電路元件80A更大或更小的寬度。
如隨後將更詳細地描述，將密封積體電路元件80。當厚度T2大於厚度T1時，存在密封體保留於在第一積體電路元件80A上方的間隙G1(參見圖4)中的風險，此可在積體電路封裝150中引起應力集中、晶粒破裂以及不良熱耗散效率。黏著層92(若存在)及散熱晶粒94填充第一積體電路元件80A上方的間隙G1，使得在隨後薄化製程之後，密封體不保留於第一積體電路元件80A上方。具體而言，第二積體電路元件80B具有比第一積體電路元件80A、黏著層92(若存在)以及散熱晶粒94的組合厚度更小的 厚度。舉例而言，黏著層92(若存在)可具有在5微米至50微米的範圍內的厚度T3，且散熱晶粒94可具有在100微米至800微米的範圍內的厚度T4，使得第一積體電路元件80A、黏著層92(若存在)以及散熱晶粒94具有在105微米至850微米的範圍內的組合厚度，其中組合厚度TC與厚度T2之間的差D2在50微米至500微米的範圍內。因此，第二積體電路元件80B的頂表面安置成比散熱晶粒94的頂表面更接近於晶圓70。
在圖6中，密封體96形成於各種組件上及周圍。在形成之後，密封體96密封積體電路元件80、底部填充劑84(若存在)、黏著層92(若存在)以及散熱晶粒94。密封體96可為模製化合物、環氧樹脂或類似者。密封體96可藉由壓縮模製、轉移模製或類似者來施加，且形成於晶圓70上方，使得內埋或覆蓋散熱晶粒94及積體電路元件80。密封體96進一步形成於積體電路元件80與散熱晶粒94之間的間隙區中。由於黏著層92(若存在)及散熱晶粒94填充第一積體電路元件80A上方的間隙G1(參見圖4)，故無密封體96形成於間隙G1中。密封體96可以液體或半液體形式施加且接著隨後固化。
在圖7中，薄化密封體96以暴露第二積體電路元件80B及散熱晶粒94。薄化製程可為研磨製程、化學機械拋光(CMP)、回蝕、其組合或類似者。在薄化製程之後，第二積體電路元件80B、散熱晶粒94以及密封體96的頂表面為共面的(在製程變化內)。執行薄化直至已移除所需量的第二積體電路元件80B、散熱晶粒94以及密封體96為止。具體而言，薄化移除密封體96的覆蓋散熱晶粒94的頂表面的部分，直至無密封體96保留於散熱晶粒94 上方為止。此外，薄化減小散熱晶粒94的厚度，直至第二積體電路元件80B具有與第一積體電路元件80A、黏著層92(若存在)以及散熱晶粒94的組合厚度相等的厚度為止。舉例而言，在薄化之後，散熱晶粒94可具有在100微米至800微米的範圍內的厚度T4，使得第一積體電路元件80A、黏著層92(若存在)以及散熱晶粒94具有在300微米至1000微米的範圍內的組合厚度TC。厚度TC等於厚度T2。因此，第二積體電路元件80B的頂表面及散熱晶粒94的頂表面安置成距晶圓70相同距離。
在圖8中，翻轉中間結構(未單獨示出)以準備處理晶圓70的背側70B。中間結構可置放於載體基底98上或其他適合的支撐結構上以用於後續處理。舉例而言，載體基底98可附接至密封體96、散熱晶粒94以及第二積體電路元件80B。載體基底98可由釋放層附接至密封體96、散熱晶粒94以及第二積體電路元件80B。釋放層可由聚合物類材料形成，所述釋放層可在處理之後與載體基底98一起自結構移除。在一些實施例中，載體基底98為諸如塊狀半導體或玻璃基底的基底。在一些實施例中，釋放層為在加熱時損失其黏著特性的環氧基熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)釋放塗層。
在圖9中，薄化基底72以暴露導通孔76。導通孔76的暴露可藉由薄化製程(諸如，研磨製程、化學機械拋光(CMP)、回蝕、其組合或類似者)來完成。在所示出的實施例中，執行凹入製程以使基底72的背表面凹入，使得導通孔76在晶圓70的背側70B處突出。凹入製程可為例如適合的回蝕製程、化學機械拋光(CMP)或類似者。在一些實施例中，用於暴露導通孔76的薄化 製程包含CMP，且導通孔76由於在CMP期間發生的凹陷而在晶圓70的背側70B處突出。絕緣層102視情況形成於基底72的背表面上，從而包圍導通孔76的突出部分。在一些實施例中，絕緣層102由含矽絕緣體(諸如，氮化矽、氧化矽、氮氧化矽或類似者)形成，且可藉由適合的沈積方法(諸如，旋塗、CVD、電漿增強CVD(plasma-enhanced CVD；PECVD)、高密度電漿CVD(high density plasma CVD；HDP-CVD)或類似者)形成。初始地，絕緣層102可掩埋導通孔76。移除製程可應用於各種層以移除導通孔76上方的多餘材料。移除製程可為平坦化製程，諸如化學機械拋光(CMP)、回蝕、其組合或類似者。在平坦化之後，導通孔76及絕緣層102的經暴露表面為共面的(在製程變化內)且在晶圓70的背側70B處暴露。在另一實施例中，省略絕緣層102，且基底72及導通孔76的經暴露表面為共面的(在製程變化內)。
在圖10中，凸塊下冶金(under bump metallurgy；UBM)104形成於導通孔76及絕緣層102(或基底72，當省略絕緣層102時)的經暴露表面上。作為形成UBM 104的實例，晶種層(未單獨示出)形成於導通孔76及絕緣層102(若存在)或基底72的經暴露表面上方。在一些實施例中，晶種層為金屬層，所述金屬層可為包含由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包含鈦層及鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。接著在晶種層上形成光阻且圖案化光阻。光阻可藉由旋塗或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於UBM 104。圖案化形成穿過光阻的開口以暴露晶種層。導電材料接著形成於光阻的開口中及晶種層的經暴露部分上。導 電材料可藉由諸如電鍍或無電極鍍覆的鍍覆或類似者形成。導電材料可包含金屬，諸如銅、鈦、鎢、鋁或類似者。接著，移除光阻及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程來移除晶種層的經暴露部分。晶種層及導電材料的剩餘部分形成UBM 104。
此外，導電連接件106形成於UBM 104上。導電連接件106可為球柵陣列(ball grid array；BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微凸塊、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成的凸塊或類似者。導電連接件106可由可回焊的導電材料形成，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件106藉由經由蒸發、電鍍、印刷、焊料轉移、植球或類似者初始地形成焊料層來形成。一旦焊料層已形成於結構上，則可執行回焊以便將材料塑形成所需凸塊形狀。在另一實施例中，導電連接件106包括藉由濺鍍、印刷、電鍍、無電極鍍覆、CVD或類似者形成的金屬柱(諸如，銅柱)。金屬柱可不含焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層形成於金屬柱的頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可由鍍覆製程形成。
在圖11中，執行載體剝離以將載體基底98自密封體96、散熱晶粒94以及第二積體電路元件80B分離(剝離)。在載體基底98由釋放層附接至密封體96、散熱晶粒94以及第二積體電路 元件80B的實施例中，剝離包含將諸如雷射光或紫外(ultraviolet；UV)光的光投影於釋放層上，使得釋放層在光的熱量下分解且可移除載體基底98。接著翻轉結構且置放於載帶(未單獨示出)上。
此外，單體化製程藉由沿著例如在封裝區70A周圍的切割道區切削來執行。單體化製程可包含鋸切、切割或類似者舉例而言，單體化製程可包含鋸切絕緣層102、密封體96、內連線結構74以及基底72。單體化製程使封裝區70A自鄰近封裝區單體化。所得單體化積體電路封裝150來自封裝區70A。單體化製程自晶圓70的單體化部分形成中介層110。由於單體化製程，故中介層110及密封體96的外側壁橫向地相連(在製程變化內)。
接著翻轉積體電路封裝150且使用導電連接件106附接至封裝基底200。封裝基底200包含基底芯(substrate core)202，所述基底芯202可由諸如矽、鍺、金剛石或類似者的半導體材料製成。替代地，亦可使用化合物材料，諸如，矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、砷化鎵磷化物、磷化鎵銦、其組合或類似者。另外，基底芯202可為SOI基底。一般而言，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代實施例中，基底芯202為諸如玻璃纖維強化樹脂芯的絕緣芯。一種實例芯材料為諸如FR4的玻璃纖維樹脂。芯材料的替代物包含雙馬來亞醯胺三嗪(bismaleimide-triazine；BT)樹脂，或替代地，其他印刷電路板(printed circuit board；PCB)材料或膜。諸如味之素累積膜(Ajinomoto build-up film；ABF)的累積膜或其他層壓物可用於基底芯202。
基底芯202可包含主動元件及被動元件(未單獨示出)。 諸如電晶體、電容器、電阻器、其組合以及類似者的元件可用以產生用於系統的設計的結構及功能需求。可使用任何適合的方法來形成元件。
基底芯202亦可包含金屬化層及通孔(未單獨示出)，以及金屬化層及通孔上方的接合墊204。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電材料(例如，低k介電材料)及導電材料(例如，銅)的交替層形成，其中通孔使導電材料層互連且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或類似者)來形成。在一些實施例中，基底芯202實質上不含主動元件及被動元件。
導電連接件106經回焊以將UBM 104附接至接合墊204。導電連接件106將包含內連線結構74的金屬化層的積體電路封裝150連接至包含基底芯202中的金屬化層的封裝基底200。因此，封裝基底200電性連接至積體電路元件80。在一些實施例中，被動元件(例如，表面安裝元件(surface mount device；SMD)，未單獨示出)可在安裝於封裝基底200上之前附接至積體電路封裝150(例如，接合至UBM 104)。在此類實施例中，被動元件可接合至積體電路封裝150的與導電連接件106相同的表面。在一些實施例中，被動元件(例如，SMD，未單獨示出)可附接至封裝基底200，例如附接至接合墊204。
在一些實施例中，底部填充劑206形成於積體電路封裝150與封裝基底200之間，從而包圍導電連接件106及UBM 104。底部填充劑206可在附接積體電路封裝150之後藉由毛細流動製程形成，或可在附接積體電路封裝150之前藉由適合的沈積方法 形成。底部填充劑206可為自封裝基底200延伸至中介層110(例如，絕緣層102)的連續材料。
散熱片208附接至積體電路封裝150。散熱片208可由具有高導熱性的材料形成，諸如矽、陶瓷、導熱玻璃、諸如銅或鐵的金屬或類似者。散熱片208保護積體電路封裝150且形成熱路徑以傳導來自積體電路封裝150的各種組件(例如，積體電路元件80)的熱量。散熱片208熱耦接至第二積體電路元件80B、散熱晶粒94以及密封體96的頂表面。散熱片208可由與散熱晶粒94相同的材料形成，或可包含不同材料。舉例而言，散熱晶粒94可由矽形成，且散熱片208可由銅形成。
如上文所提及，薄化密封體96使得暴露散熱晶粒94的頂表面。藉由暴露散熱晶粒94的頂表面，散熱片208可附接至散熱晶粒94的頂表面。散熱晶粒94由具有高導熱性的材料形成。具體而言，散熱晶粒94的材料具有比密封體96的材料更高的導熱性。因此，相比於使用密封體96將熱量自第一積體電路元件80A傳導至散熱片208，散熱晶粒94增加自第一積體電路元件80A至散熱片208的導熱性。
在一些實施例中，黏著層210用以將散熱片208黏著至積體電路封裝150。黏著層210可為熱介面材料(TIM)、晶粒附接膜(DAF)或類似者。舉例而言，黏著層210可由諸如聚合材料、焊錫、銦焊錫或類似者的TIM形成，所述TIM可施配於積體電路封裝150(例如，第二積體電路元件80B、散熱晶粒94以及密封體96的頂表面上)及/或散熱片208上。散熱片208亦可藉由其他技術附接至積體電路封裝150。在所示出的實施例中，散熱片 208包含向上延伸且遠離積體電路封裝150的鰭片。在一些實施例中，散熱片208可具有其他形狀，諸如平蓋或盒蓋底部具有凹部的盒蓋，使得盒蓋可覆蓋積體電路封裝150。
圖12為根據一些實施例的積體電路封裝的橫截面圖。除散熱晶粒94具有比第一積體電路元件80A更小的寬度外，此實施例類似於針對圖11所描述的實施例。舉例而言，第一積體電路元件80A的寬度與散熱晶粒94的寬度之間的差D3可在1微米至5微米的範圍內。因此，一些密封體96保留於間隙G1(參見圖4)中，但間隙G1中的密封體96的量小於不存在散熱晶粒94的間隙G1中的密封體96的量。形成寬度小於第一積體電路元件80A的散熱晶粒94可有助於避免在用於形成密封體96的模製製程期間可能發生的在壓合時的晶粒破裂。在所示出的實施例中，黏著層92具有比第一積體電路元件80A更小的寬度，但應瞭解黏著層92亦可具有與第一積體電路元件80A相同的寬度，諸如在黏著層92施配於第一積體電路元件80A上的實施例中。
圖13為根據一些實施例的積體電路封裝的橫截面圖。除散熱晶粒94具有比第一積體電路元件80A更大的寬度外，此實施例類似於針對圖11所描述的實施例。舉例而言，第一積體電路元件80A的寬度與散熱晶粒94的寬度之間的差D4可在1微米至5微米的範圍內。形成寬度大於第一積體電路元件80A的散熱晶粒94可有助於進一步減小積體電路封裝150的頂表面處的密封體96的量，從而改良熱耗散。在所示出的實施例中，黏著層92具有與第一積體電路元件80A相同的寬度，但應瞭解黏著層92亦可具有比第一積體電路元件80A更大的寬度，諸如在黏著層92施配於散 熱晶粒94上的實施例中。
圖14為根據一些實施例的積體電路封裝的橫截面圖。除散熱晶粒94的堆疊附接至第一積體電路元件80A外，此實施例類似於針對圖11至圖13所描述的實施例。具體而言，多個散熱晶粒94(例如，下部散熱晶粒94A、中間散熱晶粒94B以及上部散熱晶粒94C)堆疊於第一積體電路元件80A上。在一些實施例中，黏著層92(例如，第一黏著層92A、第二黏著層92B以及第三黏著層92C)用以將每一散熱晶粒94黏著至各別下伏散熱晶粒94或第一積體電路元件80A。可基於第一積體電路元件80A上方的間隙G1(參見圖4)的大小而選擇散熱晶粒94的數量，其中更多散熱晶粒94正用以填充更大間隙G1。在所示出的實施例中，堆疊中的散熱晶粒94各自具有比第一積體電路元件80A更小的寬度(以與針對圖12所描述的類似的方式)，但應瞭解堆疊中的散熱晶粒94可各自具有比第一積體電路元件80A更大的寬度(以與針對圖13所描述的類似的方式)，或與第一積體電路元件80A相同的寬度(以與針對圖11所描述的類似的方式)。
當散熱晶粒94的堆疊附接至第一積體電路元件80A時，用於薄化密封體96的製程(先前針對圖7所描述)暴露堆疊的上部散熱晶粒94C的頂表面。具體而言，薄化移除密封體96，直至無密封體96保留於上部散熱晶粒94C上方為止，且可移除上部散熱晶粒94C中的一些。在一些實施例中，散熱晶粒94中的每一者初始地具有相同厚度，但在薄化之後，上部散熱晶粒94C具有比下部散熱晶粒94A及中間散熱晶粒94B(其保留其初始厚度)更小的厚度。在薄化製程之後，第二積體電路元件80B、上部散熱晶 粒94C以及密封體96的頂表面為共面的(在製程變化內)。因此，第二積體電路元件80B的頂表面及上部散熱晶粒94C的頂表面安置成距晶圓70相同距離。散熱片208可附接至上部散熱晶粒94C的頂表面。
圖15為根據一些實施例的積體電路封裝的橫截面圖。除積體電路元件80使用直接接合附接至晶圓70外，此實施例類似於針對圖11所描述的實施例。舉例而言，混合接合、熔融接合、介電接合、金屬接合或類似者可在不使用黏著劑或焊料的情況下用以直接接合晶圓70及積體電路元件80的對應介電層及/或晶粒連接件。儘管針對圖11所描述的實施例繪示直接接合，但應瞭解直接接合亦可用於先前針對圖12至圖14所描述的實施例，或隨後將針對圖20至圖23以及圖30至圖33所描述的實施例中的任一者中。
圖16至圖19為根據一些實施例的晶粒堆疊60A的製造中的中間階段的橫截面圖。藉由將積體電路晶粒50B(具有導通孔62)接合至晶圓300形成晶粒堆疊60A。在實施例中，晶粒堆疊60A為系統積體晶片(SoIC)元件，但應瞭解實施例可應用於其他三維積體電路(3DIC)封裝。晶圓300具有晶粒區300A，所述晶粒區300A包含形成於其中的晶粒，諸如積體電路晶粒50A(其可不具有導通孔62)。晶粒區300A將在後續處理中單體化以形成晶粒堆疊60A，所述晶粒堆疊60A包含晶圓300的單體化部分(例如，積體電路晶粒50A)及接合至晶圓300的單體化部分的積體電路晶粒50B，如隨後將更詳細地描述，晶粒堆疊60A可用作積體電路封裝150中的第一積體電路元件80A。
示出晶圓300的一個晶粒區300A的處理。應瞭解，晶圓300的任何數目個晶粒區300A可同時經處理及單體化以自晶圓300的單體化部分形成多個晶粒堆疊60A。
在圖16中，獲得或形成晶圓300。晶圓300包括晶粒區300A中的元件，所述元件將在後續處理中單體化以包含於晶粒堆疊60A中。在一些實施例中，積體電路晶粒50A形成於晶圓300中，所述晶圓300包含基底52、內連線結構54、晶粒連接件56以及介電層58，其類似於針對圖1所描述的彼等。
積體電路晶粒50B使用直接接合附接至晶圓300。舉例而言，混合接合、熔融接合、介電接合、金屬接合或類似者可在不使用黏著劑或焊料的情況下用以直接接合積體電路晶粒50A、積體電路晶粒50B的對應介電層58及/或晶粒連接件56。任何所需數量的積體電路晶粒50B可附接至晶圓300。在一些實施例中，積體電路晶粒50A、積體電路晶粒50B更包含在其對應的內連線結構54中的對準標記64，所述對準標記64可用以在接合期間對準積體電路晶粒50A、積體電路晶粒50B。積體電路晶粒50B包含延伸至內連線結構54及/或半導體基底52中的導通孔62。導通孔62電性連接至內連線結構54的金屬化層。
在圖17中，導通孔302視情況形成於晶圓300上，例如晶粒連接件56上。導通孔302電性連接至積體電路晶粒50A。作為形成導通孔302的實例，晶種層形成於晶圓300上方。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包含鈦層及鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。在晶 種層上形成光阻且圖案化光阻。光阻可藉由旋塗或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於導通孔302。圖案化形成穿過光阻的開口以暴露晶種層。導電層接著形成於第一光阻的開口中及晶種層的經暴露部分上。導電層可藉由諸如自晶種層無電極鍍覆或電鍍的鍍覆或類似者形成。導電層可由銅、鈦、鎢、鋁或類似者形成。移除光阻及晶種層上未形成金屬層的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程(諸如，藉由濕式蝕刻或乾式蝕刻)來移除晶種層的經暴露部分。晶種層及金屬層的剩餘部分形成導通孔302。
密封體304形成於各種組件上及周圍。在形成之後，密封體304密封導通孔302(若存在)及積體電路晶粒50B。密封體304可為模製化合物、環氧樹脂或類似者。密封體304可藉由壓縮模製、轉移模製或類似者施加，且可形成於晶圓300上方，使得內埋或覆蓋導通孔302(若存在)及積體電路晶粒50B。密封體304進一步形成於導通孔302(若存在)與積體電路晶粒50B之間的間隙區中。密封體304可以液體或半液體形式施加且接著隨後固化。視情況薄化密封體304以暴露導通孔302(若存在)及積體電路晶粒50B。薄化製程可為研磨製程、化學機械拋光(CMP)、回蝕、其組合或類似者。在薄化製程之後，密封體304、導通孔302(若存在)以及積體電路晶粒50B的頂表面為共面的(在製程變化內)。執行薄化直至已移除所需量的密封體304、導通孔302(若存在)以及積體電路晶粒50B為止。舉例而言，若已暴露導通孔302(若存在)及積體電路晶粒50B，則可省略密封體304的薄化。
在圖18中，密封體304及積體電路晶粒50B的半導體基底52接地以暴露導通孔62。可執行一或多個移除製程，若導通孔302尚未暴露，則所述移除製程亦暴露導通孔302。移除製程可為平坦化製程，諸如化學機械拋光(CMP)、研磨製程、回蝕、其組合或類似者。在一些實施例中，執行移除製程以薄化積體電路晶粒50B的半導體基底52且暴露導通孔62。障壁層306可視情況形成在導通孔62周圍。障壁層306可有助於使導通孔62彼此電隔離，因此避免短路。作為形成障壁層306的實例，積體電路晶粒50B的半導體基底52可凹入以暴露導通孔62的側壁部分。凹入可藉由蝕刻製程(諸如乾式蝕刻)進行。障壁材料接著可形成於凹部中。障壁材料可為諸如低溫聚醯亞胺材料的介電材料，但亦可使用任何其他適合的介電材料，諸如PBO、密封體、其組合或類似者。可執行諸如CMP、研磨或回蝕的平坦化製程以移除積體電路晶粒50B的半導體基底52上方的障壁材料的多餘部分。凹部中的障壁材料的剩餘部分形成障壁層306。在形成障壁層306之後，其由密封體304橫向地包圍。導通孔302(若存在)、密封體304、障壁層306(若存在)以及導通孔62的頂表面為共面的(在製程變化內)。
在圖19中，重佈線結構310形成於導通孔302(若存在)、密封體304、障壁層306(若存在)以及導通孔62的頂表面上。重佈線結構310包含介電層312及介電層312中的金屬化層314(有時稱為重佈線層或重佈線)。舉例而言，重佈線結構310可包含由各別介電層312彼此分開的多個金屬化層314。重佈線結構310的金屬化層314連接至導通孔302(若存在)及導通孔62。具 體而言，金屬化層314由導通孔302(若存在)及導通孔62連接至積體電路晶粒50A、積體電路晶粒50B。
在一些實施例中，介電層312由聚合物形成，所述聚合物可為諸如PBO、聚醯亞胺、BCB類聚合物或類似者的感光材料，且可使用微影罩幕圖案化。在其他實施例中，介電層312由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。介電層312可藉由旋塗、層壓、CVD、類似者或其組合形成。在形成每一介電層312之後，接著經圖案化以暴露下伏導電特徵，諸如下伏導通孔62、導通孔302或金屬化層314的部分。可藉由可接受的製程進行圖案化，諸如藉由在介電層312為感光材料時將介電層暴露於光下，或藉由使用例如非等向性蝕刻來蝕刻。若介電層312為感光材料，則介電層312可在暴露之後顯影。
金屬化層314各自包含導通孔及/或導電線。導通孔延伸穿過介電層312，且導電線沿著介電層312延伸。作為形成金屬化層的實例，晶種層(未單獨示出)形成於各別下伏特征上方。舉例而言，晶種層可形成於各別介電層312上及穿過各別介電層312的開口中，或可形成於下伏導通孔302(若存在)或下伏導通孔62上。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用諸如PVD或類似者的沈積製程形成晶種層。接著在晶種層上形成光阻且圖案化光阻。光阻可藉由旋塗或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化層。圖案化形成穿過光阻的開口以暴露晶種層。導電材 料形成於光阻的開口中及晶種層的經暴露部分上。導電材料可藉由諸如電鍍或無電極鍍覆的鍍覆或類似者形成。導電材料可包括金屬或金屬合金，諸如銅、鈦、鎢、鋁、類似者或其組合。接著，移除光阻及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程(諸如，藉由濕式蝕刻或乾式蝕刻)來移除晶種層的經暴露部分。晶種層及導電材料的剩餘部分形成金屬化層。
重佈線結構310示出為實例。比所示出更多或更少的介電層312及金屬化層314可藉由重複或省略先前所描述的步驟形成於重佈線結構310中。
導電連接件82(先前所描述)形成於重佈線結構310上。導電連接件82可連接至重佈線結構310的金屬化層314。舉例而言，導電連接件82可形成於重佈線結構310的凸塊下金屬化物(under-bump metallization；UBM)316上。
單體化製程藉由沿著例如在晶粒區300A周圍的切割道區切削來執行。單體化製程可包含鋸切、切割或類似者舉例而言，單體化製程可包含鋸切重佈線結構310、密封體304以及晶圓300。單體化製程使晶粒區300A自鄰近晶粒區單體化。所得單體化晶粒堆疊60A來自晶粒區300A。單體化製程自晶圓300的單體化部分形成積體電路晶粒50A。由於單體化製程，故重佈線結構310、密封體304以及積體電路晶粒50A的外側壁橫向地相連(在製程變化內)。積體電路晶粒50B各自具有比積體電路晶粒50A更小的寬度。
圖20、圖21、圖22以及圖23為根據一些實施例的積體電路封裝的橫截面圖。除第一積體電路元件80A為與針對圖16至圖19所描述的晶粒堆疊類似的晶粒堆疊60A外，此等實施例類似於針對圖11、圖12、圖13以及圖14所描述的實施例。為了說明清晰起見，省略晶粒堆疊60A的一些特徵。在此等實施例中，晶粒堆疊60A的重佈線結構310使用焊料接合(例如，導電連接件82)附接至中介層110。因此，重佈線結構310連接至導通孔62(參見圖19)、導通孔302(若存在，參見圖19)以及中介層110。此外，在此等實施例中，晶粒堆疊60A包含一個積體電路晶粒50B而非圖16至圖19中所繪示的三個積體電路晶粒50B，但應瞭解任何所需數量的積體電路晶粒50B可包含於晶粒堆疊60A中。散熱片208可附接至積體電路晶粒50A的頂表面。
圖24至圖29為根據一些實施例的晶粒堆疊60A的製造中的中間階段的橫截面圖。晶粒堆疊60A藉由將積體電路晶粒50A(其可不具有導通孔62)接合至晶圓400形成。在實施例中，晶粒堆疊60A為系統積體晶片(SoIC)元件，但應瞭解實施例可應用於其他三維積體電路(3DIC)封裝。晶圓400具有晶粒區400A，所述晶粒區400A包含形成於其中的晶粒，諸如積體電路晶粒50B(具有導通孔62)。晶粒區400A將在後續處理中單體化以形成晶粒堆疊60A，所述晶粒堆疊60A包含晶圓400的單體化部分(例如，積體電路晶粒50B)及接合至晶圓400的單體化部分的積體電路晶粒50A。如隨後將更詳細地描述，晶粒堆疊60A可用作積體電路封裝150中的第一積體電路元件80A。
示出晶圓400的一個晶粒區400A的處理。應瞭解，晶圓 400的任何數目個晶粒區400A可同時經處理及單體化以自晶圓400的單體化部分形成多個晶粒堆疊60A。
在圖24中，獲得或形成晶圓400。晶圓400可類似於針對圖16所描述的晶圓300，且包含晶粒區400A中的積體電路晶粒50B。積體電路晶粒50B包含延伸至內連線結構54及/或半導體基底52中的導通孔62。積體電路晶粒50A接著以與針對圖16所描述的類似的方式附接至晶圓400。任何所需數量的積體電路晶粒50A可附接至晶圓400。
在圖25中，密封體404形成於各種組件上及周圍。密封體404可類似於針對圖17所描述的密封體96，且可藉由類似製程形成。視情況薄化密封體404以暴露積體電路晶粒50A。可以與針對圖17所描述的類似的方式薄化密封體404。
在圖26中，翻轉中間結構(未單獨示出)以準備處理晶圓400的背側400B。中間結構可置放於載體基底406上或其他適合的支撐結構上以用於後續處理。載體基底406可類似於針對圖8所描述的載體基底98，且可以與針對圖8所描述的類似的方式附接至密封體404。
在圖27中，薄化晶圓400的基底52以暴露導通孔62。可以與針對圖9所描述的類似的方式薄化基底52。絕緣層408可視情況形成於基底52的背表面上，從而包圍導通孔62的突出部分。絕緣層408可類似於針對圖9所描述的絕緣層102，且可藉由類似製程形成。
在圖28中，重佈線結構410形成於基底52、導通孔62以及絕緣層408(若存在)上。重佈線結構410可類似於針對圖19 所描述的重佈線結構310，且可藉由類似製程形成。導電連接件82(先前所描述)形成於重佈線結構410上。導電連接件82可連接至重佈線結構410的金屬化層。舉例而言，導電連接件82可形成於重佈線結構410的凸塊下金屬化物(UBM)上。
在圖29中，執行載體剝離以自密封體404分離(剝離)載體基底406。可以與針對圖11所描述的類似的方式剝離載體基底406。
單體化製程藉由沿著例如在晶粒區400A周圍的切割道區切削來執行。單體化製程可包含鋸切、切割或類似者舉例而言，單體化製程可包含鋸切重佈線結構410、密封體404以及晶圓400。單體化製程使晶粒區400A自鄰近晶粒區單體化。所得單體化晶粒堆疊60A來自晶粒區400A。單體化製程自晶圓400的單體化部分形成積體電路晶粒50B。由於單體化製程，故重佈線結構410、密封體404以及積體電路晶粒50B的外側壁橫向地相連(在製程變化內)。積體電路晶粒50A各自具有比積體電路晶粒50B更小的寬度。
圖30、圖31、圖32以及圖33為根據一些實施例的積體電路封裝的橫截面圖。除第一積體電路元件80A為與針對圖24至圖29所描述的晶粒堆疊類似的晶粒堆疊60A外，此等實施例類似於針對圖11、圖12、圖13以及圖14所描述的實施例，。為了說明清晰起見，省略晶粒堆疊60A的一些特徵。在此等實施例中，晶粒堆疊60A的重佈線結構410使用焊料接合(例如，導電連接件82)附接至中介層110。因此，重佈線結構410連接至導通孔62及中介層110。此外，在此等實施例中，晶粒堆疊60A包含一 個積體電路晶粒50A而非圖24至圖29中所繪示的三個積體電路晶粒50A，但應瞭解任何所需數量的積體電路晶粒50A可包含於晶粒堆疊60A中。散熱片208可附接至積體電路晶粒50A的頂表面。
實施例可實現優勢。用黏著層92(若存在)填充第一積體電路元件80A上方的間隙G1(參見圖4)，且散熱晶粒94有助於減小保留於積體電路封裝150中的第一積體電路元件80A上方的密封體96的量。可因此避免應力集中及晶粒破裂。此外，散熱片208可附接至散熱晶粒94的頂表面，所述散熱晶粒94由具有高導熱性的材料形成。因此，散熱晶粒94增加自第一積體電路元件80A至散熱片208的導熱性。因此可改良積體電路封裝150中的散熱效率。
在實施例中，元件包含：中介層；第一積體電路元件，附接至中介層；第二積體電路元件，附接至中介層，第二積體電路元件鄰近第一積體電路元件；散熱晶粒，位於第二積體電路元件上；以及密封體，圍繞散熱晶粒、第二積體電路元件以及第一積體電路元件，密封體的頂表面與散熱晶粒的頂表面及第一積體電路元件的頂表面共面。在元件的一些實施例中，散熱晶粒的頂表面安置成與第一積體電路元件的頂表面距中介層相同距離。在元件的一些實施例中，散熱晶粒的寬度等於第二積體電路元件的寬度。在元件的一些實施例中，散熱晶粒的寬度大於第二積體電路元件的寬度。在元件的一些實施例中，散熱晶粒的寬度小於第二積體電路元件的寬度。在元件的一些實施例中，散熱晶粒為安置於第二積體電路元件上的多個散熱晶粒中的一者。在元件的一些實施例中，第一積 體電路元件為第一晶粒堆疊且第二積體電路元件為第二晶粒堆疊。在元件的一些實施例中，第一積體電路元件為晶粒堆疊且第二積體電路元件為積體電路晶粒。在一些實施例中，元件更包含：散熱片，位於密封體的頂表面、散熱晶粒的頂表面以及第一積體電路元件的頂表面上。
在實施例中，元件包含：中介層；第一晶粒堆疊，接合至中介層的前側；第二晶粒堆疊，接合至中介層的前側，第二晶粒堆疊的頂表面安置成比第一晶粒堆疊的頂表面更接近於中介層；散熱晶粒，位於第二晶粒堆疊上，散熱晶粒的頂表面安置成與第一晶粒堆疊的頂表面距中介層相同距離；以及散熱片，位於散熱晶粒的頂表面及第二晶粒堆疊的頂表面上。在元件的一些實施例中，第二晶粒堆疊包含：第一積體電路晶粒；第二積體電路晶粒，接合至第一積體電路晶粒，第二積體電路晶粒包含第一導通孔；密封體，在第二積體電路晶粒周圍；以及重佈線結構，位於密封體及第二積體電路晶粒上，重佈線結構連接至第一導通孔及中介層。在元件的一些實施例中，第二晶粒堆疊更包含：第二導通孔，延伸穿過密封體，第二導通孔連接至第一積體電路晶粒及重佈線結構。在元件的一些實施例中，第二晶粒堆疊包含：密封體；第一積體電路晶粒，位於密封體中；第二積體電路晶粒，接合至第一積體電路晶粒，第二積體電路晶粒包含導通孔；以及重佈線結構，位於第二積體電路晶粒上，重佈線結構連接至導通孔及中介層。在一些實施例中，元件更包含：密封體，在第一晶粒堆疊、第二晶粒堆疊以及散熱晶粒周圍，密封體的頂表面安置成與第一晶粒堆疊的頂表面及散熱晶粒的頂表面距中介層相同距離。
在實施例中，方法包含：將第一積體電路元件及第二積體電路元件接合至中介層的前側；將散熱晶粒附著於第一積體電路元件上；用密封體密封散熱晶粒、第一積體電路元件以及第二積體電路元件；薄化密封體及散熱晶粒以及第二積體電路元件直至密封體的頂表面與散熱晶粒的頂表面及第一積體電路元件的頂表面共面為止；以及將散熱片附著至密封體的頂表面、散熱晶粒的頂表面以及第二積體電路元件的頂表面。在方法的一些實施例中，密封體的第一部分覆蓋散熱晶粒的頂表面，且薄化密封體移除密封體的第一部分。在方法的一些實施例中，第二積體電路元件的頂表面安置成比第一積體電路元件的頂表面距中介層更遠，在薄化散熱晶粒之前，散熱晶粒的頂表面安置成比第二積體電路元件的頂表面距中介層更遠，且在薄化散熱晶粒之後，散熱晶粒的頂表面安置成與第二積體電路元件的頂表面距中介層相同距離。在方法的一些實施例中，第二積體電路元件為高頻寬記憶體(HBM)元件。在方法的一些實施例中，第一積體電路元件為系統積體晶片(SoIC)元件。在方法的一些實施例中，第一積體電路元件為積體電路晶粒。
前文概述若干實施例的特徵，使得所屬技術領域中具有通常知識者可更佳地理解本揭露的態樣。所屬技術領域中具有通常知識者應瞭解，其可易於使用本揭露作為用於設計或修改用於實施本文中所引入的實施例的相同目的及/或達成相同優勢的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具有通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作 出各種改變、替代以及更改。
72:基底
74:內連線結構
80:積體電路元件
80A:第一積體電路元件
80B:第二積體電路元件
82、106:導電連接件
84、206:底部填充劑
92、210:黏著層
94:散熱晶粒
96:密封體
102:絕緣層
104:凸塊下冶金
150:積體電路封裝
200:封裝基底
204:接合墊
208:散熱片
110:中介層
D3:差

Claims (10)

  1. 一種積體電路封裝，包括：中介層；第一積體電路元件，附接至所述中介層；第二積體電路元件，附接至所述中介層，第二積體電路元件鄰近所述第一積體電路元件；散熱晶粒，位於所述第二積體電路元件上，其中所述散熱晶粒為安置於所述第二積體電路元件上的多個散熱晶粒中的一者；以及密封體，圍繞所述散熱晶粒、所述第二積體電路元件以及所述第一積體電路元件，所述密封體的頂表面與所述散熱晶粒的頂表面及所述第一積體電路元件的頂表面共面。
  2. 如請求項1所述的積體電路封裝，其中所述散熱晶粒的所述頂表面安置成與所述第一積體電路元件的所述頂表面距所述中介層相同距離。
  3. 如請求項1所述的積體電路封裝，其中所述第一積體電路元件為第一晶粒堆疊且所述第二積體電路元件為第二晶粒堆疊或積體電路晶粒。
  4. 如請求項1所述的積體電路封裝，更包括：散熱片，位於所述密封體的所述頂表面、所述散熱晶粒的所述頂表面以及所述第一積體電路元件的所述頂表面上。
  5. 一種積體電路封裝，包括：中介層；第一晶粒堆疊，接合至所述中介層的前側； 第二晶粒堆疊，接合至所述中介層的所述前側，所述第二晶粒堆疊的頂表面安置成比所述第一晶粒堆疊的頂表面更接近於所述中介層；散熱晶粒，位於所述第二晶粒堆疊上，所述散熱晶粒的頂表面安置成與所述第一晶粒堆疊的所述頂表面距所述中介層相同距離，以及散熱片，位於所述散熱晶粒的所述頂表面及所述第二晶粒堆疊的所述頂表面上。
  6. 如請求項5所述的積體電路封裝，其中所述第二晶粒堆疊包括：第一積體電路晶粒；第二積體電路晶粒，接合至所述第一積體電路晶粒，所述第二積體電路晶粒包括第一導通孔；密封體，圍繞所述第二積體電路晶粒；以及重佈線結構，位於所述密封體及所述第二積體電路晶粒上，所述重佈線結構連接至所述第一導通孔及所述中介層。
  7. 如請求項5所述的積體電路封裝，其中所述第二晶粒堆疊包括：密封體；第一積體電路晶粒，位於所述密封體中；第二積體電路晶粒，接合至所述第一積體電路晶粒，所述第二積體電路晶粒包括導通孔；以及重佈線結構，位於所述第二積體電路晶粒上，所述重佈線結構連接至所述導通孔及所述中介層。
  8. 如請求項5所述的積體電路封裝，更包括：密封體，圍繞所述第一晶粒堆疊、所述第二晶粒堆疊以及所述散熱晶粒，所述密封體的頂表面安置成與所述第一晶粒堆疊的所述頂表面及所述散熱晶粒的所述頂表面距所述中介層相同距離。
  9. 如請求項5所述的積體電路封裝，其中所述散熱晶粒為安置於所述第二積體電路元件上的多個散熱晶粒中的一者。
  10. 一種積體電路封裝的製造方法，包括：將第一積體電路元件及第二積體電路元件接合至中介層的前側，其中所述第一積體電路元件，其中所述第一積體電路元件包括多個晶粒彼此堆疊，且所述第一積體電路元件的頂表面安置成比所述第二積體電路元件的頂表面更接近於所述中介層；將散熱晶粒黏著於所述第一積體電路元件上；用密封體密封所述散熱晶粒、所述第一積體電路元件以及所述第二積體電路元件；薄化所述密封體、所述散熱晶粒以及所述第二積體電路元件，直至所述密封體的頂表面與所述散熱晶粒的頂表面及所述第二積體電路元件的頂表面共面為止；以及將散熱片黏著至所述密封體的所述頂表面、所述散熱晶粒的所述頂表面以及所述第二積體電路元件的所述頂表面。
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