CN115132675A - 集成电路封装件和方法 - Google Patents

集成电路封装件和方法 Download PDF

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Publication number
CN115132675A
CN115132675A CN202210114069.1A CN202210114069A CN115132675A CN 115132675 A CN115132675 A CN 115132675A CN 202210114069 A CN202210114069 A CN 202210114069A CN 115132675 A CN115132675 A CN 115132675A
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Prior art keywords
integrated circuit
die
heat spreader
circuit device
top surface
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CN202210114069.1A
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陈宪伟
陈明发
叶松峯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN115132675A publication Critical patent/CN115132675A/zh
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Abstract

在一个实施例中，一种器件包括：插件；第一集成电路器件，连接至插件；第二集成电路器件，连接至邻接第一集成电路器件的插件；散热管芯，位于第二集成电路器件上；以及密封剂，位于散热管芯、第二集成电路器件、和第一集成电路器件周围，密封剂的顶面与散热管芯的顶面和第一集成电路器件的顶面共面。本申请的实施例提供了集成电路封装件和方法。

Description

集成电路封装件和方法
技术领域
本申请的实施例涉及集成电路封装件和方法。
背景技术
由于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度方面的持续改进，半导体工业已经经历了快速增长。在大多数情况下，集成密度方面的改进源于最小特征尺寸的迭代减小，这允许将更多组件集成至给定区域中。随着对缩小电子器件的需求的增长，对更小、更具创造性的半导体管芯封装技术的需求应运而生。
发明内容
在一个实施例中，一种器件包括：插件；第一集成电路器件，连接至插件；第二集成电路器件，连接至邻接第一集成电路器件的插件；散热管芯，位于第二集成电路器件上；以及密封剂，位于散热管芯、第二集成电路器件、和第一集成电路器件周围，密封剂的顶面与散热管芯的顶面和第一集成电路器件的顶面共面。
在一个实施例中，一种器件包括：插件；第一管芯堆叠件，接合至插件的正面；第二管芯堆叠件，接合至插件的正面，第二管芯堆叠件的顶面设置成比第一管芯堆叠件的顶面更靠近插件；散热管芯，位于第二管芯堆叠件上，散热管芯的顶面设置成与第一管芯堆叠件的顶面距插件相同的距离；以及散热器，位于散热管芯的顶面和第二管芯堆叠件的顶面上。
在一个实施例中，一种方法包括：将第一集成电路器件和第二集成电路器件接合至插件的正面；将散热管芯粘附至第一集成电路器件上；通过密封剂密封散热管芯、第一集成电路器件、和第二集成电路器件；薄化密封剂、散热管芯、和第二集成电路器件，直至密封剂的顶面与散热管芯的顶面和第一集成电路器件的顶面共面；以及将散热器粘附至密封剂的顶面、散热管芯的顶面、和第二集成电路器件的顶面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是集成电路管芯的截面图；
图2A-图2B是根据一些实施例的管芯堆叠件的截面图；
图3-图11是根据一些实施例的集成电路封装件的制造中的中间阶段的截面图；
图12-图15是根据一些实施例的集成电路封装件的截面图；
图16-图19是根据一些实施例的管芯堆叠件的制造中的中间阶段的截面图；
图20-图23是根据一些实施例的集成电路封装件的截面图；
图24-图29是根据一些实施例的管芯堆叠件的制造中的中间阶段的截面图；
图30-图33是根据一些实施例的集成电路封装件的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复参考数字和/或字母。该重复是出于简化和清楚的目的，其本身并不指示所讨论的各种实施例和/或结构之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以容易地描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各种实施例，形成集成电路封装件，其包括各种厚度的集成电路器件，以及位于具有较小厚度的(一些)集成电路器件上方的散热管芯。散热管芯穿过形成在集成电路器件周围的密封剂暴露。散热管芯的包括可以减少位于具有较小厚度的(一些)集成电路器件上方的密封剂的量，这有助于避免集成电路封装件中的应力集中和管芯开裂。另外，散热器可以连接至散热管芯的顶面，这有助于提高集成电路封装件中的散热效率。
图1是集成电路管芯50的截面图。多个集成电路管芯50将在后续处理中进行封装，以形成集成电路封装件。每个集成电路管芯50可以是逻辑管芯(例如中央处理单元(CPU)、图形处理单元(GPU)、微控制器等)、存储器管芯(例如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如电源管理集成电路(PMIC)管芯)、射频(RF)管芯、接口管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如数字信号处理(DSP)管芯)、前端管芯(例如模拟前端(AFE)管芯)等、或其组合(例如片上系统(SoC)管芯)。集成电路管芯50可以形成在晶圆中，其可以包括在后续步骤中进行单个化以形成多个集成电路管芯50的不同管芯区。集成电路管芯50包括半导体衬底52、互连结构54、管芯连接器56、和介电层58。
半导体衬底52可以是掺杂的或者未掺杂的硅衬底，或者是绝缘体上半导体(SOI)衬底的有源层。半导体衬底52可以包括其他半导体材料，例如：锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；合金半导体，包括硅锗、磷化砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、和/或磷化砷化镓铟；或其组合。也可以使用其他衬底，例如多层衬底或者梯度衬底。半导体衬底52具有有源表面(例如图1中朝上的表面)和非有源表面(例如图1中朝下的表面)。器件处于半导体衬底52的有源表面。器件可以是有源器件(例如晶体管、二极管等)、电容器、电阻器等。无源表面可以没有器件。
互连结构54位于半导体衬底52的有源表面上方，并且用于电连接半导体衬底52的器件，以形成集成电路。互连结构54可以包括一个或者多个介电层和(一些)介电层中的相应的(一些)金属化层。用于介电层的可接受的介电材料包括：氧化物，例如氧化硅或者氧化铝；氮化物，例如氮化硅；碳化物，例如碳化硅；等等；或其组合，例如氧氮化硅、氧碳化硅、氮碳化硅、氧碳氮化硅等。也可以使用其他介电材料，例如聚合物，例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)基聚合物等。(一些)金属化层可以包括导电通孔和/或导线，以互连半导体衬底52的器件。(一些)金属化层可以由导电材料形成，例如由诸如铜、钴、铝、金、其组合等的金属形成。互连结构54可以通过诸如单镶嵌工艺、双镶嵌工艺等的镶嵌工艺形成。
管芯连接器56处于集成电路管芯50的正面50F。管芯连接器56可以是外部连接实施于此的导电柱、焊盘等。管芯连接器56位于互连结构54之中和/或之上。例如，管芯连接器56可以是互连结构54的上部金属化层的一部分。管芯连接器56可以由诸如铜铝、铝等的金属形成，并且可以通过例如镀敷等形成。
可选地，在集成电路管芯50的形成期间，焊料区(未单独示出)可以设置在管芯连接器56上。焊料区可以用于在集成电路管芯50上实施芯片探针(CP)测试。例如，焊料区可以是用于将芯片探针连接至管芯连接器56的焊球、焊料凸块等。芯片探针测试可以实施在集成电路管芯50上，以确定集成电路管芯50是否是已知良好的管芯(KGD)。因此，只有作为KGD的集成电路管芯50经过后续处理而进行封装，而芯片探针测试失败的管芯不会进行封装。在测试之后，焊料区可以在后续处理步骤中去除。
介电层58位于集成电路管芯50的正面50F。介电层58位于互连结构54之中和/或之上。例如，介电层58可以是互连结构54的上部介电层。介电层58横向地密封管芯连接器56。介电层58可以是氧化物、氮化物、碳化物、聚合物等、或其组合。介电层58可以例如通过旋涂、层压、化学气相沉积(CVD)等形成。最初，介电层58可以掩埋管芯连接器56，使得介电层58的顶面位于管芯连接器56的顶面之上。在集成电路管芯50的形成期间，管芯连接器56通过介电层58暴露。使管芯连接器56暴露可以去除管芯连接器56上可能存在的任何焊料区。去除工艺可以实施至各个层，以去除管芯连接器56上方的多余材料。去除工艺可以是平坦化工艺，例如化学机械抛光(CMP)、回蚀、其组合等。在平坦化工艺之后，管芯连接器56和介电层58的顶面共面(在工艺变化范围内)，并且暴露在集成电路管芯50的正面50F处。
图2A-图2B是根据一些实施例的管芯堆叠件60A、60B的截面图。管芯堆叠件60A、60B可以各自具有单一功能(例如逻辑器件、存储器管芯等)，或者可以具有多种功能。在一些实施例中，管芯堆叠件60A是诸如集成芯片上系统(SoIC)器件的逻辑器件，而管芯堆叠件60B是诸如高带宽存储器(HBM)器件的存储器器件。
如图2A所示，管芯堆叠件60A包括两个接合的集成电路管芯50(例如第一集成电路管芯50A和第二集成电路管芯50B)。在一些实施例中，第一集成电路管芯50A是逻辑管芯，而第二集成电路管芯50B是接口管芯。接口管芯将逻辑管芯桥接至存储器管芯，并且在逻辑管芯和存储器管芯之间转换命令。在一些实施例中，第一集成电路管芯50A和第二集成电路管芯50B接合成使得有源表面彼此面对(例如为“面对面”接合)。导电通孔62可以形成为穿过集成电路管芯50之一，使得外部连接可以进行至管芯堆叠件60A。导电通孔62可以是贯穿衬底通孔(TSV)，例如贯穿硅通孔等。在所示的实施例中，导电通孔62形成在第二集成电路管芯50B(例如接口管芯)中。导电通孔62延伸穿过相应的集成电路管芯50的半导体衬底52，以物理地和电地连接至互连结构54的(一些)金属化层。形成管芯堆叠件60A的方法将随后进行描述。
如图2B所示，管芯堆叠件60B是包括多个半导体衬底52的堆叠器件。例如，管芯堆叠件60B可以是包括诸如混合存储数据集(HMC)器件、高带宽存储器(HBM)器件等的多个存储器管芯的存储器器件。半导体衬底52中的每一个可以(或者可以不)具有单独的互连结构54。半导体衬底52通过导电通孔62进行连接。
图3-图11是根据一些实施例的集成电路封装件的制造中的中间阶段的截面图。具体地，集成电路封装件150通过将集成电路器件80接合至晶圆70而形成。在一个实施例中，集成电路封装件150是晶圆上芯片(CoW)封装件，但是应当理解的是，实施例可以适用于其他三维集成电路(3DIC)封装件。晶圆70具有封装区70A，其包括形成于其中的器件，例如插件110。封装区70A将在后续处理中进行单个化，以形成集成电路封装件150，其包括晶圆70的单个化部分(例如插件110)，和接合至晶圆70的单个化部分的集成电路器件80。集成电路封装件150然后安装至封装衬底200。在一个实施例中，所得封装件是衬底上晶圆上芯片(CoWoS)封装件，但是应当理解的是，实施例可以适用于其他3DIC封装件。
示出了晶圆70的一个封装区70A的处理。应当理解的是，晶圆70的任何数量的封装区70A可以同时地进行处理和单个化，以从晶圆70的单个化的部分形成多个集成电路封装件150。
在图3中，获得或者形成晶圆70。晶圆70包括封装区70A中的器件，其将会在后续处理中进行单个化，以包括在集成电路封装件150中。晶圆70中的器件可以是插件、集成电路管芯等。在一些实施例中，插件110形成在晶圆70中，其包括衬底72、互连结构74、和导电通孔76。
衬底72可以是体半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底72可以包括半导体材料，例如：硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；合金半导体，包括硅锗、磷化砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、和/或磷化砷化镓铟；或其组合。也可以使用其他衬底，例如多层衬底或者梯度衬底。衬底72可以是掺杂的或者是未掺杂的。在其中插件形成在晶圆70中的实施例中，衬底72中通常不包括有源器件，但是插件可以包括形成在衬底72的正面(例如图3中朝上的表面)之中和/或之上的无源器件。在其中集成电路器件形成在晶圆70中的实施例中，诸如晶体管、电容器、电阻器、二极管等的有源器件可以形成在衬底72的正面之中和/或之上。
互连结构74位于衬底72的正面上方，并且用于电连接衬底72的器件(如果有的话)。互连结构74可以包括一个或者多个介电层，和相应的(一些)介电层中的(一些)金属化层。用于介电层的可接受的介电材料包括：氧化物，例如氧化硅或者氧化铝；氮化物，例如氮化硅；碳化物，例如碳化硅；等等；或其组合，例如氧氮化硅、氧碳化硅、碳氮化硅、氧碳氮化硅等。也可以使用其他介电材料，例如诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)基聚合物等的聚合物。(一些)金属化层可以包括导电通孔和/或导线，以互连任何器件在一起和/或互连至外部器件。(一些)金属化层可以由导电材料形成，例如由诸如铜、钴、铝、金、其组合等的金属形成。互连结构74可以通过诸如单镶嵌工艺、双镶嵌工艺等的镶嵌工艺形成。
在一些实施例中，管芯连接器和介电层(未单独示出)位于晶圆70的正面70F。具体地，晶圆70所包括的管芯连接器和介电层可以类似于针对图1所描述的集成电路管芯50的管芯连接器和介电层。例如，管芯连接器和介电层可以是互连结构74的上部金属化层的一部分。
导电通孔76延伸至互连结构74和/或衬底72中。导电通孔76电连接至互连结构74的(一些)金属化层。导电通孔76有时也称为TSV。作为用以形成导电通孔76的示例，可以通过例如蚀刻、铣削、激光技术、其组合、和/或等等，在互连结构74和/或衬底72中形成凹进。薄介电材料可以形成在凹进中，例如通过使用氧化技术。薄阻挡层可以共形地沉积在开口中，例如通过CVD、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、其组合、和/或等等。阻挡层可以由氧化物、氮化物、碳化物、其组合等形成。导电材料可以沉积在阻挡层上方和开口中。导电材料可以通过电化学镀敷工艺、CVD、ALD、PVD、其组合、和/或等等来形成。导电材料的示例是铜、钨、铝、银、金、其组合、和/或等等。多余的导电材料和阻挡层通过例如CMP从互连结构74或者衬底72的表面去除。阻挡层和导电材料的所剩部分形成导电通孔76。
在图4中，集成电路器件80(例如第一集成电路器件80A和多个第二集成电路器件80B)连接至晶圆70。期望的类型和数量的集成电路器件80连接在封装区70A中。在所示实施例中，多个集成电路器件80，包括第一集成电路器件80A和第二集成电路器件80B，彼此相邻地放置，其中第一集成电路器件80A位于第二集成电路器件80B之间。第一集成电路器件80A可以具有与第二集成电路器件80B不同的功能。第一集成电路器件80A可以是逻辑器件，例如中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等。第二集成电路器件80B可以是存储器器件，例如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储器数据集(HMC)模块、高带宽存储器(HBM)模块、等等。第一集成电路器件80A和第二集成电路器件80B可以在相同技术节点的工艺中形成，或者可以在不同技术节点的工艺中形成。例如，第一集成电路器件80A可以是比第二集成电路器件80B更先进的工艺节点。
在所示的实施例中，集成电路器件80通过焊料接合、例如通过导电连接器82，连接至晶圆70。集成电路器件80可以使用例如拾取和放置工具，放置在互连结构74上。导电连接器82可以通过可回流的导电材料形成，例如通过焊料、铜、铝、金、镍、银、钯、锡等、或其组合形成。在一些实施例中，导电连接器82由通过诸如蒸发、电镀、印刷、焊料转移、球放置等的方法首先形成焊料层来形成。一旦在结构上形成了一层焊料，就可以实施回流，以将导电连接器82成形为期望的凸块形状。将集成电路器件80连接至晶圆70，可以包括将集成电路器件80放置在晶圆70上，并且回流导电连接器82。导电连接器82形成晶圆70的对应管芯连接器和集成电路器件80之间的接头，将插件110电连接至集成电路器件80。
底部填料84可以形成在导电连接器82周围，以及形成在晶圆70和集成电路器件80之间。底部填料84可以减少应力，并且保护由导电连接器82的回流所得的接头。底部填料84可以由诸如模制化合物、环氧树脂等的底部填充材料形成。底部填料84可以在集成电路器件80连接至晶圆70之后、通过毛细管流动工艺形成，或者，可以在集成电路器件80连接至晶圆70之前、通过合适的沉积方法形成。底部填料84可以以流体或者半流体形式施加，然后进行固化。
在其他实施例中(针对图15所描述的)，集成电路器件80通过直接接合连接至晶圆70。例如混合接合、熔融接合、介电接合、金属接合等，可以用于将晶圆70和集成电路器件80的对应介电层和/或管芯连接器直接接合，而无需使用粘附剂或者焊料。当使用直接接合时，底部填料84可以省略。另外，可以使用接合技术的混合，例如，一些集成电路器件80可以通过焊料接合连接至晶圆70，而其他集成电路器件80可以通过直接接合连接至晶圆70。
集成电路器件80A可以是集成电路管芯(类似于针对图1所描述的集成电路管芯50)，或者可以是管芯堆叠件(类似于针对图2A所描述的管芯堆叠件60A)。在本实施例中，第一集成电路器件80A是集成电路管芯。在其他实施例(随后更详细地进行描述)中，第一集成电路器件80A是管芯堆叠件。
集成电路器件80B可以是集成电路管芯(类似于针对图1所描述的集成电路管芯50)，或者可以是管芯堆叠件(类似于针对图2B所描述的管芯堆叠件60B)。在该实施例中，第一集成电路器件80B是管芯堆叠件。由于具有多个半导体衬底，因此管芯堆叠件、特别是诸如高带宽存储器(HBM)器件的存储器管芯堆叠件，具有大的厚度。例如，高容量HBM器件可能具有十二个或者更多个半导体衬底。当第二集成电路器件80B是存储器管芯堆叠件时，其可以具有比第一集成电路器件80A更大的厚度。例如，第一集成电路器件80A可以具有在200μm至775μm范围内的厚度T1，而第二集成电路器件80B可以各自具有在300μm至1000μm范围内的厚度T2，其中厚度T1和厚度T2之间的差值D1在50μm至800μm的范围内。因此，第二集成电路器件80B的顶面设置成比第一集成电路器件80A的顶面更远离晶圆70。因此，间隙G1存在于第一集成电路器件80A上方，其中间隙G1由第一集成电路器件80A的顶面和第二集成电路器件80B的顶面之间的面积来限定。
在图5中，散热管芯94连接至第一集成电路器件80A。散热管芯94包括体衬底，并且可以不包括器件、(一些)金属化层等。散热管芯94由具有高导热性的材料形成，例如由硅、陶瓷、导热玻璃、诸如铜或者铁的金属等形成。在一些实施例中，散热管芯94由在CMP期间产生少量残留物的诸如硅的材料形成。散热管芯94也可以称为伪管芯或者热增强管芯。
在一些实施例中，粘附层92用于将散热管芯94粘附至第一集成电路器件80A。粘附层92可以是热接口材料(TIM)、管芯附着膜(DAF)等。例如，粘附层92可以由诸如聚合材料、焊膏、铟焊膏等的TIM形成，其可以设置在第一集成电路器件80A和/或散热管芯94上。散热管芯94也可以通过其他技术连接至第一集成电路器件80A。
粘附层92(如果存在的话)和散热管芯94可以具有多种宽度。在本实施例中，粘附层92和散热管芯94具有与第一集成电路器件80A相同的宽度，从而第一集成电路器件80A、粘附层92、和散热管芯94的外侧壁横向地毗连。在其他实施例(随后更详细地进行描述)中，粘附层92和散热管芯94具有比第一集成电路器件80A更大或者更小的宽度。
如随后将更详细地进行描述的，集成电路器件80将进行密封。当厚度T2大于厚度T1时，第一集成电路器件80A上方的间隙G1(参见图4)中存在密封剂残留的风险，这可能导致集成电路封装件150中的应力集中、管芯开裂、和散热效率低下。粘附层92(如果存在的话)和散热管芯94填充第一集成电路器件80A上方的间隙G1，使得在随后的薄化工艺之后，密封剂不会残留在第一集成电路器件80A上方。具体地，第二集成电路器件80B具有比第一集成电路器件80A、粘附层92(如果存在的话)、和散热管芯94的组合厚度更小的厚度。例如，粘附层92(如果存在的话)可以具有在5μm至50μm的范围内的厚度T3，而散热管芯94可以具有在100μm至800μm的范围内的厚度T4，从而第一集成电路器件80A、粘附层92(如果存在的话)、和散热管芯94可以具有在105μm至850μm的范围内的组合厚度TC，其中组合厚度TC和厚度T2之间的差值D2在50μm至500μm的范围内。因此，第二集成电路器件80B的顶面设置成比散热管芯94的顶面更靠近晶圆70。
在图6中，密封剂96形成在各种组件之上和周围。在形成之后，密封剂96密封集成电路器件80、底部填料84(如果存在的话)、粘附层92(如果存在的话)、和散热管芯94。密封剂96可以是模制化合物、环氧树脂等。密封剂96可以通过压缩模制、传递模制等施加，并且可以形成在晶圆70上方，从而将散热管芯94和集成电路器件80掩埋或者覆盖。密封剂96进一步形成在集成电路器件80和散热管芯94之间的间隙区域中。由于粘附层92(如果存在的话)和散热管芯94填充第一集成电路器件80A上方的间隙G1(参见图4)，因此密封剂96没有形成在间隙G1中。密封剂96可以以流体或者半流体形式施加，并且随后进行固化。
在图7中，密封剂96进行薄化，以暴露第二集成电路器件80B和散热管芯94。薄化工艺可以是研磨工艺、化学机械抛光(CMP)、回蚀、其组合等。在薄化工艺之后，第二集成电路器件80B、散热管芯94、和密封剂96的顶面共面(在工艺变化范围内)。薄化实施为直至期望量的第二集成电路器件80B、散热管芯94、和密封剂96去除。具体地，薄化去除了覆盖散热管芯94的顶面的密封剂96的部分，直至没有密封剂96保留在散热管芯94上方。另外，薄化减小了散热管芯94的厚度，直至第二集成电路器件80B所具有的厚度等于第一集成电路器件80A、粘附层92(如果存在的话)、和散热管芯94的组合厚度。例如，在薄化之后，散热管芯94可以具有在100μm至800μm的范围内的厚度T4，从而第一集成电路器件80A、粘附层92(如果存在的话)、和散热管芯94具有在300μm至1000μm的范围内的组合厚度TC。厚度TC等于厚度T2。因此，第二集成电路器件80B的顶面和散热管芯94的顶面设置成距晶圆70相同的距离。
在图8中，中间结构进行翻转(未单独示出)，以准备处理晶圆70的背面70B。中间结构可以放置在载体衬底98或者其他合适的支撑结构上，用于后续处理。例如，载体衬底98可以连接至密封剂96、散热管芯94、和第二集成电路器件80B。载体衬底98可以通过剥离层连接至密封剂96、散热管芯94、和第二集成电路器件80B。剥离层可以由聚合物基的材料形成，其可以在处理之后与载体衬底98一起从结构去除。在一些实施例中，载体衬底98是诸如体半导体或者玻璃衬底的衬底。在一些实施例中，剥离层是在受热时失去其粘附特性的环氧基的热剥离材料，例如光热转换(LTHC)剥离涂层。
在图9中，衬底72进行薄化，以暴露导电通孔76。导电通孔76的暴露可以通过薄化工艺完成，例如通过研磨工艺、化学机械抛光(CMP)、回蚀、其组合等完成。在所示的实施例中，实施凹进工艺，以使衬底72的背面凹进，使得导电通孔76在晶圆70的背面70B处凸出。凹进工艺可以是例如合适的回蚀工艺、化学机械抛光(CMP)等。在一些实施例中，用于暴露导电通孔76的薄化工艺包括CMP，并且作为在CMP期间发生的凹陷的结果，导电通孔76在晶圆70的背面70B处凸出。绝缘层102可选地形成在衬底72的背面上，围绕导电通孔76的凸出部分。在一些实施例中，绝缘层102由含硅的绝缘体形成，例如由氮化硅、氧化硅、氧氮化硅等形成，并且可以通过合适的沉积方法形成，例如通过旋涂、CVD、等离子体增强CVD(PECVD)、高密度等离子体CVD(HDP-CVD)等形成。最初，绝缘层102可以掩埋导电通孔76。去除工艺可以施加至各个层，以去除导电通孔76上方的多余材料。去除工艺可以是平坦化工艺，例如化学机械抛光(CMP)、回蚀、其组合等。在平坦化之后，导电通孔76和绝缘层102的暴露表面是共面的(在工艺变化范围内)，并且暴露在晶圆70的背面70B处。在另一个实施例中，绝缘层102省略，并且衬底72和导电通孔76的暴露表面是共面的(在工艺变化范围内)。
在图10中，凸块下金属化件(UBM)104形成在导电通孔76和绝缘层102(或者衬底72，当绝缘层102省略时)的暴露表面上。作为用以形成UBM104的示例，晶种层(未单独示出)形成在导电通孔76和绝缘层102(如果存在的话)或者衬底72的暴露表面上方。在一些实施例中，晶种层是金属层，其可以是单层，或者是包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。晶种层可以使用例如PVD等来形成。光刻胶然后形成并且图案化在晶种层上。光刻胶可以通过旋涂等形成，并且可以暴露至光用于进行图案化。光刻胶的图案对应于UBM104。图案化形成穿过光刻胶以暴露晶种层的开口。然后导电材料形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过镀敷形成，例如通过电镀或者化学镀等形成。导电材料可以包括金属，例如铜、钛、钨、铝等。然后，去除光刻胶和其上未形成导电材料的晶种层的部分。光刻胶可以通过可接受的灰化或者剥离工艺去除，例如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，例如通过使用可接受的蚀刻工艺。晶种层和导电材料的所剩部分形成UBM104。
另外，导电连接器106形成在UBM104上。导电连接器106可以是球栅阵列(BGA)连接器、焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学钯浸金技术(ENEPIG)形成的凸块等。导电连接器106可以通过可回流的导电材料形成，例如通过焊料、铜、铝、金、镍、银、钯、锡等、或其组合形成。在一些实施例中，导电连接器106由通过蒸发、电镀、印刷、焊料转移、球放置等首先形成焊料层来形成。一旦在结构上形成了一层焊料，就可以实施回流，以将材料成形为期望的凸块形状。在另一个实施例中，导电连接器106包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱)。金属柱可以是无焊料的，并且具有基本垂直的侧壁。在一些实施例中，金属覆盖层形成在金属柱的顶部。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等、或其组合，并且可以通过镀敷工艺形成。
在图11中，实施载体剥离，以从密封剂96、散热管芯94、和第二集成电路器件80B分离(剥离)载体衬底98。在其中载体衬底98通过剥离层连接至密封剂96、散热管芯94、和第二集成电路器件80B的实施例中，剥离包括投射诸如激光或者紫外(UV)光的光在剥离层上，使得剥离层在光的加热下分解，并且载体衬底98可以去除。然后结构进行翻转并且放置在胶带(未单独示出)上。
另外，通过沿着划线区(例如在封装区70A周围)进行切割，来实施单个化工艺。单个化工艺可以包括锯切、切割等。例如，单个化工艺可以包括锯切绝缘层102、密封剂96、互连结构74、和衬底72。单个化工艺将封装区70A从相邻的封装区单个化。所得的、单个化的集成电路封装件150来自封装区70A。单个化工艺从晶圆70的单个化的部分形成插件110。作为单个化工艺的结果，插件110和密封剂96的外侧壁横向地毗连(在工艺变化范围内)。
然后使用导电连接器106将集成电路封装件150翻转并且连接至封装衬底200。封装衬底200包括衬底芯202，其可以由诸如硅、锗、金刚石等的半导体材料制成。可替代地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化锗硅、磷化砷镓、磷化镓铟、其组合等的化合物材料。另外，衬底芯202可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI、或其组合的半导体材料的层。在一个可替代的实施例中，衬底芯202是诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是诸如FR4的玻璃纤维树脂。芯材料的替代品包括双马来酰亚胺三嗪(BT)树脂，或者可替代地，包括其他印刷电路板(PCB)材料或者薄膜。诸如味之素堆积膜(ABF)的堆积膜或者其他层压材料可以用于衬底芯202。
衬底芯202可以包括有源器件和无源器件(未单独示出)。诸如晶体管、电容器、电阻器、其组合等的器件可以用于生成用于系统的设计的结构和功能要求。器件可以使用任何合适的方法形成。
衬底芯202还可以包括金属化层和通孔(未单独示出)，以及位于金属化层和通孔上方的接合焊盘204。金属化层可以形成在有源器件和无源器件上方，并且设计成连接各种器件以形成功能电路。金属化层可以由介电材料(例如低k介电材料)和导电材料(例如铜)的交替层形成，具有互连导电材料层的通孔，并且可以通过任何合适的工艺(例如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底芯202基本上没有有源器件和无源器件。
导电连接器106进行回流，以将UBM104连接至接合焊盘204。导电连接器106将集成电路封装件150(包括互连结构74的金属化层)连接至封装衬底200(包括衬底芯202中的金属化层)。因此，封装衬底200电连接至集成电路器件80。在一些实施例中，无源器件(例如表面安装器件(SMD)，未单独示出)可以在安装至封装衬底200上之前，连接至集成电路封装件150(例如接合至UBM104)。在这样的实施例中，无源器件可以与导电连接器106接合至集成电路封装件150的相同表面。在一些实施例中，无源器件(例如SMD，未单独示出)可以连接至封装衬底200，例如连接至接合焊盘204。
在一些实施例中，底部填料206形成在集成电路封装件150和封装衬底200之间，围绕导电连接器106和UBM104。底部填料206可以在集成电路封装件150进行连接之后、通过毛细流动工艺来形成，或者，可以在集成电路封装件150进行连接之前、通过合适的沉积方法来形成。底部填料206可以是从封装衬底200延伸至插件110(例如绝缘层102)的连续材料。
散热器208连接至集成电路封装件150。散热器208可以由具有高导热性的材料形成，例如由硅、陶瓷、导热玻璃、诸如铜或者铁的金属等形成。散热器208保护集成电路封装件150，并且形成热通路，以传导来自集成电路封装件150的各种组件(例如集成电路器件80)的热量。散热器208热连接至第二集成电路器件80B、散热管芯94、和密封剂96的顶面。散热器208可以由与散热管芯94相同的材料形成，或者可以包括不同的材料。例如，散热管芯94可以由硅形成，而散热器208可以由铜形成。
如上所述，密封剂96进行薄化，使得散热管芯94的顶面暴露。通过暴露散热管芯94的顶面，使得散热器208可以连接至散热管芯94的顶面。散热管芯94由具有高导热性的材料形成。具体地，散热管芯94的材料具有比密封剂96的材料更高的导热性。因此，与使用密封剂96将热量从第一集成电路器件80A传导至散热器208相比，散热管芯94增加了从第一集成电路器件80A至散热器208的导热性。
在一些实施例中，粘附层210用于将散热器208粘附至集成电路封装件150。粘附层210可以是热接口材料(TIM)、管芯附着膜(DAF)等。例如，粘附层210可以由诸如聚合材料、焊膏、铟焊膏等的TIM形成，其可以设置在集成电路封装件150上(例如第二集成电路器件80B、散热管芯94、和密封剂96的顶面上)和/或散热器208上。散热器208也可以通过其他技术连接至集成电路封装件150。在所示的实施例中，散热器208包括远离集成电路封装件150向上延伸的翅片。在一些实施例中，散热器208可以具有其他形状，例如平盖或者盒盖，盒盖的底部中具有凹进，使得盒盖可以覆盖集成电路封装件150。
图12是根据一些实施例的集成电路封装件的截面图。该实施例类似于针对图11所描述的实施例，不同之处在于，散热管芯94具有比第一集成电路器件80A更小的宽度。例如，第一集成电路器件80A的宽度和散热管芯94的宽度之间的差值D3可以在1μm至5μm的范围内。因此，一些密封剂96保留在间隙G1中(参见图4)，但是间隙G1中的密封剂96的量小于没有散热管芯94的间隙G1中的密封剂96的量。使散热管芯94形成为比第一集成电路器件80A具有更小的宽度，可以有助于避免可能发生在用于形成密封剂96的模制工艺期间的压制期间的管芯开裂。在所示的实施例中，粘附层92具有比第一集成电路器件80A更小的宽度，但是应当理解的是，粘附层92也可以具有与第一集成电路器件80A相同的宽度，例如在其中粘附层92设置在第一集成电路器件80A上的实施例中。
图13是根据一些实施例的集成电路封装件的截面图。该实施例类似于针对图11所描述的实施例，不同之处在于，散热管芯94具有比第一集成电路器件80A更大的宽度。例如，第一集成电路器件80A的宽度和散热管芯94的宽度之间的差值D4可以在1μm至5μm的范围内。使散热管芯94形成为比第一集成电路器件80A具有更大的宽度，可以有助于进一步减少集成电路封装件150的顶面处的密封剂96的量，从而改善散热。在所示的实施例中，粘附层92具有与第一集成电路器件80A相同的宽度，但是应当理解的是，粘附层92也可以具有比第一集成电路器件80A更大的宽度，例如在其中粘附层92设置在散热管芯94上的实施例中。
图14是根据一些实施例的集成电路封装件的截面图。该实施例类似于针对图11-图13所描述的实施例，不同之处在于，散热管芯94的堆叠件连接至第一集成电路器件80A。具体地，多个散热管芯94(例如下部散热管芯94A、中间散热管芯94B、和上部散热管芯94C)堆叠在第一集成电路器件80A上。在一些实施例中，粘附层92(例如第一粘附层92A、第二粘附层92B、和第三粘附层92C)用于将每个散热管芯94粘附至相应的下面的散热管芯94或者第一集成电路器件80A。散热管芯94的数量可以基于第一集成电路器件80A上方的间隙G1(参见图4)的尺寸来选择，其中更多的散热管芯94用来填充更大的间隙G1。在所示实施例中，散热管芯94在堆叠件中各自具有比第一集成电路器件80A更小的宽度(以与针对图12所描述的类似的方式)，但是应当理解的是，散热管芯94在堆叠件中可以各自具有比第一集成电路器件80A更大的宽度(以与针对图13所描述的类似的方式)，或者具有与第一集成电路器件80A相同的宽度(以与针对图11所描述的类似的方式)。
当散热管芯94的堆叠件连接至第一集成电路器件80A时，用于薄化密封剂96的工艺(先前针对图7所描述的)暴露堆叠件的上部散热管芯94C的顶面。具体地，薄化去除密封剂96，直至没有密封剂96保留在上部散热管芯94C上方，并且可以去除一些上部散热管芯94C。在一些实施例中，散热管芯94中的每一个最初具有相同的厚度，但是在薄化之后，上部散热管芯94C具有比下部散热管芯94A和中间散热管芯94B(其保持其初始厚度)更小的厚度。在薄化工艺之后，第二集成电路器件80B、上部散热管芯94C、和密封剂96的顶面共面(在工艺变化范围内)。因此，第二集成电路器件80B的顶面和上部散热管芯94C的顶面设置成距晶圆70相同的距离。散热器208可以连接至上部散热管芯94C的顶面。
图15是根据一些实施例的集成电路封装件的截面图。该实施例类似于针对图11所描述的实施例，不同之处在于，集成电路器件80通过直接接合连接至晶圆70。例如混合接合、熔融接合、介电接合、金属接合等，可以用于将晶圆70和集成电路器件80的对应介电层和/或管芯连接器直接接合，而无需使用粘附剂或者焊料。虽然针对图11所描述的实施例示出了直接接合，但是应当理解的是，直接接合也可以用于先前针对图12-图14所描述的任何实施例中，或者可以用于随后将针对图20-图23和图30-图33所描述的实施例。
图16-图19是根据一些实施例的管芯堆叠件60A的制造中的中间阶段的截面图。管芯堆叠件60A通过将集成电路管芯50B(具有导电通孔62)接合至晶圆300而形成。在一个实施例中，管芯堆叠件60A是集成芯片上系统(SoIC)器件，但是应当理解的是，实施例可以适用于其他三维集成电路(3DIC)封装件。晶圆300具有管芯区300A，其包括形成在其中的管芯，例如集成电路管芯50A(其可以不具有导电通孔62)。管芯区300A将在后续处理中进行单个化，以形成管芯堆叠件60A，其包括晶圆300的单个化的部分(例如集成电路管芯50A)和接合至晶圆300的单个化的部分的集成电路管芯50B。如随后将更详细地描述的，管芯堆叠件60A可以用作集成电路封装件150中的第一集成电路器件80A。
示出了晶圆300的一个管芯区300A的处理。应当理解的是，晶圆300的任何数量的管芯区300A可以同时地进行处理和单个化，以从晶圆300的单个化的部分形成多个管芯堆叠件60A。
在图16中，获得或者形成晶圆300。晶圆300包括管芯区300A中的器件，其将在随后的处理中进行单个化，以包括在管芯堆叠件60A中。在一些实施例中，集成电路管芯50A形成在晶圆300中，其包括衬底52、互连结构54、管芯连接器56、和介电层58，它们类似于针对图1所描述的那些。
集成电路管芯50B通过直接接合连接至晶圆300。例如混合接合、熔融接合、介电接合、金属接合等，可以用于将集成电路管芯50A、50B的对应介电层58和/或管芯连接器56直接接合，而无需使用粘附剂或者焊料。任何期望数量的集成电路管芯50B可以连接至晶圆300。在一些实施例中，集成电路管芯50A、50B在其对应的互连结构54中还包括对准标记64，其可以用于在接合期间对准集成电路管芯50A、50B。集成电路管芯50B包括延伸至互连结构54和/或半导体衬底52中的导电通孔62。导电通孔62电连接至互连结构54的(一些)金属化层。
在图17中，导电通孔302可选地形成在晶圆300上，例如在管芯连接器56上。导电通孔302电连接至集成电路管芯50A。作为用以形成导电通孔302的示例，晶种层形成在晶圆300上方。在一些实施例中，晶种层是金属层，其可以是单层，或者是包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。晶种层可以使用例如PVD等来形成。光刻胶形成并且图案化在晶种层上。光刻胶可以通过旋涂等形成，并且可以暴露至光用于进行图案化。光刻胶的图案对应于导电通孔302。图案化形成穿过光刻胶以暴露晶种层的开口。然后导电材料形成在第一光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过镀敷形成，例如从晶种层等化学镀或者电镀。导电层可以由铜、钛、钨、铝等形成。去除光刻胶和其上未形成金属层的晶种层的部分。光刻胶可以通过可接受的灰化或者剥离工艺去除，例如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，例如通过使用可接受的蚀刻工艺，例如通过湿蚀刻或者干蚀刻。晶种层和金属层的所剩部分形成导电通孔302。
密封剂304形成在各种组件之上和周围。在形成之后，密封剂304密封导电通孔302(如果存在的话)和集成电路管芯50B。密封剂304可以是模制化合物、环氧树脂等。密封剂304可以通过压缩模制、传递模制等施加，并且可以形成在晶圆300上方，从而将导电通孔302(如果存在的话)和集成电路管芯50B掩埋或者覆盖。密封剂304进一步形成在导电通孔302(如果存在的话)和集成电路管芯50B之间的间隙区域中。密封剂304可以以流体或者半流体形式施加，并且随后进行固化。密封剂304可选地进行薄化，以暴露导电通孔302(如果存在的话)和集成电路管芯50B。薄化工艺可以是研磨工艺、化学机械抛光(CMP)、回蚀、其组合等。在薄化工艺之后，密封剂304、导电通孔302(如果存在的话)、和集成电路管芯50B的顶面共面(在工艺变化范围内)。薄化实施为直至期望量的密封剂304、导电通孔302(如果存在的话)、和集成电路管芯50B已经去除。例如，如果导电通孔302(如果存在的话)和集成电路管芯50B已经暴露，则密封剂304的薄化可以省略。
在图18中，密封剂304和集成电路管芯50B的半导体衬底52接地，以暴露导电通孔62。可以实施一个或者多个去除工艺，其也暴露导电通孔302，如果它们还没有暴露的话。去除工艺可以是平坦化工艺，例如化学机械抛光(CMP)、研磨工艺、回蚀、其组合等。在一些实施例中，实施去除工艺，以薄化集成电路管芯50B的半导体衬底52，并且暴露导电通孔62。阻挡层306可以可选地形成在导电通孔62周围。阻挡层306可以有助于将导电通孔62彼此电隔离，从而避免短路。作为用以形成阻挡层306的示例，集成电路管芯50B的半导体衬底52可以凹进，以暴露导电通孔62的侧壁部分。凹进可以是通过蚀刻工艺，例如干蚀刻。然后阻挡材料可以形成在凹进中。阻挡材料可以是介电材料，例如低温聚酰亚胺材料，但是也可以使用任何其他合适的介电材料，例如PBO、密封剂、其组合等。可以实施平坦化工艺，例如CMP、研磨、或者回蚀，以去除集成电路管芯50B的半导体衬底52上方的阻挡材料的多余部分。凹进中的阻挡材料的所剩部分形成阻挡层306。在形成阻挡层306之后，其由密封剂304横向地围绕。导电通孔302(如果存在的话)、密封剂304、阻挡层306(如果存在的话)、和导电通孔62的顶面共面(在工艺变化范围内)。
在图19中，再分布结构310形成在导电通孔302(如果存在的话)、密封剂304、阻挡层306(如果存在的话)、和导电通孔62的顶面上。再分布结构310包括介电层312，和介电层312之间的金属化层314(有时称为再分布层或者再分布线)。例如，再分布结构310可以包括通过相应的介电层312彼此分隔开的多个金属化层314。再分布结构310的金属化层314连接至导电通孔302(如果存在的话)和导电通孔62。具体地，金属化层314通过导电通孔302(如果存在的话)和导电通孔62连接至集成电路管芯50A、50B。
在一些实施例中，介电层312由聚合物形成，其可以是诸如PBO、聚酰亚胺、BCB基的聚合物等的光敏材料，并且可以使用光刻掩模进行图案化。在其他实施例中，介电层312由诸如氮化硅的氮化物、诸如氧化硅、PSG、BSG、BPSG等的氧化物、等等来形成。介电层312可以通过旋涂、层压、CVD等、或其组合来形成。在各个介电层312形成之后，然后其进行图案化，以暴露下面的导电部件，例如下面的导电通孔62、导电通孔302、或者金属化层314的部分。图案化可以通过可接受的工艺来进行，例如当介电层312是光敏材料时，通过将介电层暴露至光来进行，或者通过使用例如各向异性蚀刻的蚀刻来进行。如果介电层312是光敏材料，则介电层312可以在曝光之后进行显影。
金属化层314各自包括导电通孔和/或导线。导电通孔延伸穿过介电层312，并且导线沿着介电层312延伸。作为用以形成金属化层的示例，晶种层(未单独示出)形成在相应的下面的部件的上方。例如，晶种层可以形成在相应的介电层312上，和穿过相应的介电层312的开口中，或者可以形成在下面的导电通孔302(如果存在的话)或者下面的导电通孔62上。在一些实施例中，晶种层是金属层，其可以是单层，或者是包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。晶种层可以使用诸如PVD等的沉积工艺来形成。光刻胶然后形成并且图案化在晶种层上。光刻胶可以通过旋涂等形成，并且可以暴露至光用于进行图案化。光刻胶的图案对应于金属化层。图案化形成穿过光刻胶以暴露晶种层的开口。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过镀敷形成，例如电镀或者化学镀等。导电材料可以包括金属或者金属合金，例如铜、钛、钨、铝等、或其组合。然后，去除光刻胶和其上未形成导电材料的晶种层的部分。光刻胶可以通过可接受的灰化或者剥离工艺去除，例如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，例如通过使用可接受的蚀刻工艺，例如通过湿蚀刻或者干蚀刻。晶种层和导电材料的所剩部分形成金属化层。
再分布结构310示出为示例。比所示出的更多或者更少的介电层312和金属化层314，可以通过重复或省略先前所描述的步骤，形成在再分布结构310中。
导电连接器82(先前所描述的)形成在再分布结构310上。导电连接器82可以连接至再分布结构310的金属化层314。例如，导电连接器82可以形成在再分布结构310的凸块下金属化件(UBM)316上。
通过沿着划线区(例如在管芯区300A周围)进行切割，来实施单个化工艺。单个化工艺可以包括锯切、切割等。例如，单个化工艺可以包括锯切再分布结构310、密封剂304、和晶圆300。单个化工艺将管芯区300A从相邻的管芯区单个化。所得的、单个化的管芯堆叠件60A来自管芯区300A。单个化工艺从晶圆300的单个的化部分形成集成电路管芯50A。作为单个化工艺的结果，再分布结构310、密封剂304、和集成电路管芯50A的外侧壁横向地毗连(在工艺变化范围内)。集成电路管芯50B各自具有比集成电路管芯50A更小的宽度。
图20、图21、图22、和图23是根据一些实施例的集成电路封装件的截面图。这些实施例类似于针对图11、图12、图13、和他14所描述的实施例，不同之处在于，第一集成电路器件80A类似于如针对图16-图19所描述的管芯堆叠件60A。为了阐释清楚，管芯堆叠件60A的一些特征省略。在这些实施例中，管芯堆叠件60A的再分布结构310通过焊料接合，例如导电连接器82，连接至插件110。于是，再分布结构310连接至导电通孔62(参见图19)、导电通孔302(如果存在的话，参见图19)、和插件110。另外，在这些实施例中，管芯堆叠件60A包括一个集成电路管芯50B，而不是图16-图19中所示的三个集成电路管芯50B，但是应当理解的是，任何期望数量的集成电路管芯50B可以包括在管芯堆叠件60A中。散热器208可以连接至集成电路管芯50A的顶面。
图24-图29是根据一些实施例的管芯堆叠件60A的制造中的中间阶段的截面图。管芯堆叠件60A通过将集成电路管芯50A(其可能不具有导电通孔62)接合至晶圆400来形成。在一个实施例中，管芯堆叠件60A是集成芯片上系统(SoIC)器件，但是应当理解的是，实施例可以适用于其他三维集成电路(3DIC)封装件。晶圆400具有管芯区400A，其包括形成在其中的管芯，例如集成电路管芯50B(具有导电通孔62)。管芯区400A将在后续处理中进行单个化，以形成管芯堆叠件60A，其包括晶圆400的单个化的部分(例如集成电路管芯50B)，和接合至晶圆400的单个化的部分的集成电路管芯50A。如随后将更详细地描述的，管芯堆叠件60A可以用作集成电路封装件150中的第一集成电路器件80A。
示出了晶圆400的一个管芯区400A的处理。应当理解的是，晶圆400的任何数量的管芯区400A可以同时地进行处理和单个化，以从晶圆400的单个化的部分形成多个管芯堆叠件60A。
在图24中，获得或者形成晶圆400。晶圆400可以类似于针对图16所描述的晶圆300，并且包括管芯区400A中的集成电路管芯50B。集成电路管芯50B包括延伸至互连结构54和/或半导体衬底52中的导电通孔62。然后，集成电路管芯50A以与如针对图16所描述的类似的方式，连接至晶圆400。任何期望数量的集成电路管芯50A可以连接至晶圆400。
在图25中，密封剂404形成在各种组件之上和周围。密封剂404可以类似于针对图17所描述的密封剂96，并且可以通过类似的工艺来形成。密封剂404可选地进行薄化，以暴露集成电路管芯50A。密封剂404可以以与如针对图17所描述的类似的方式进行薄化。
在图26中，中间结构进行翻转(未单独示出)，以准备处理晶圆400的背面400B。中间结构可以放置在载体衬底406或者其他合适的支撑结构上，用于后续处理。载体衬底406可以类似于针对图8所描述的载体衬底98，并且可以以与如针对图8所描述的类似的方式，连接至密封剂404。
在图27中，晶圆400的衬底52进行薄化，以暴露导电通孔62。衬底52可以以与如针对图9所描述的类似的方式进行薄化。绝缘层408可以可选地形成在衬底52的背面上，围绕导电通孔62的凸出部分。绝缘层408可以类似于针对图9所描述的绝缘层102，并且可以通过类似的工艺来形成。
在图28中，再分布结构410形成在衬底52、导电通孔62、和绝缘层408(如果存在的话)上。再分布结构410可以类似于针对图19所描述的再分布结构310，并且可以通过类似的工艺来形成。导电连接器82(先前描述的)形成在再分布结构410上。导电连接器82可以连接至再分布结构410的金属化层。例如，导电连接器82可以形成在再分布结构410的凸块下金属化件(UBM)上。
在图29中，实施载体剥离，以从密封剂404分离(剥离)载体衬底406。载体衬底406可以以与如针对图11所描述的类似的方式来分离。
通过沿着划线区(例如在管芯区400A周围)进行切割，来实施单个化工艺。单个化工艺可以包括锯切、切割等。例如，单个化工艺可以包括锯切再分布结构410、密封剂404、和晶圆400。单个化工艺将管芯区400A从相邻的管芯区单个化。所得的、单个化的管芯堆叠件60A来自管芯区400A。单个化工艺从晶圆400的单个化的部分形成集成电路管芯50B。作为单个化工艺的结果，再分布结构410、密封剂404、和集成电路管芯50B的外侧壁横向地毗连(在工艺变化范围内)。集成电路管芯50A各自具有比集成电路管芯50B更小的宽度。
图30、图31、图32、和图33是根据一些实施例的集成电路封装件的截面图。这些实施例类似于针对图11、图12、图13、和图14所描述的实施例，不同之处在于，第一集成电路器件80A类似于如针对图24-图29所描述的管芯堆叠件60A。为了阐释清楚，管芯堆叠件60A的一些特征省略。在这些实施例中，管芯堆叠件60A的再分布结构320通过焊料接合，例如导电连接器82，连接至插件110。于是，再分布结构410连接至导电通孔62和插件110。另外，在这些实施例中，管芯堆叠件60A包括一个集成电路管芯50A，而不是图24-图29中所示的三个集成电路管芯50A，但是应当理解的是，任何期望数量的集成电路管芯50A可以包括在管芯堆叠件60A中。散热器208可以连接至集成电路管芯50A的顶面。
实施例可以实现优点。通过粘附层92(如果存在的话)和散热管芯94填充第一集成电路器件80A上方的间隙G1(参见图4)，有助于减少保留在集成电路封装件150中的第一集成电路器件80A上方的密封剂96的量。因此可以避免应力集中和管芯开裂。另外，散热器208可以连接至由具有高导热性的材料所形成的散热管芯94的顶面。散热管芯94因此增加了从第一集成电路器件80A至散热器208的导热性。集成电路封装件150中的散热效率可以因此提高。
在一个实施例中，一种器件包括：插件；第一集成电路器件，连接至插件；第二集成电路器件，连接至邻接第一集成电路器件的插件；散热管芯，位于第二集成电路器件上；以及密封剂，位于散热管芯、第二集成电路器件、和第一集成电路器件周围，密封剂的顶面与散热管芯的顶面和第一集成电路器件的顶面共面。在器件的一些实施例中，散热管芯的顶面设置成与第一集成电路器件的顶面距插件相同的距离。在器件的一些实施例中，散热管芯的宽度等于第二集成电路器件的宽度。在器件的一些实施例中，散热管芯的宽度大于第二集成电路器件的宽度。在器件的一些实施例中，散热管芯的宽度小于第二集成电路器件的宽度。在器件的一些实施例中，散热管芯是设置在第二集成电路器件上的多个散热管芯之一。在器件的一些实施例中，第一集成电路器件是第一管芯堆叠件，而第二集成电路器件是第二管芯堆叠件。在器件的一些实施例中，第一集成电路器件是管芯堆叠件，而第二集成电路器件是集成电路管芯。在一些实施例中，器件还包括：散热器，位于密封剂的顶面、散热管芯的顶面、和第一集成电路器件的顶面上。
在一个实施例中，一种器件包括：插件；第一管芯堆叠件，接合至插件的正面；第二管芯堆叠件，接合至插件的正面，第二管芯堆叠件的顶面设置成比第一管芯堆叠件的顶面更靠近插件；散热管芯，位于第二管芯堆叠件上，散热管芯的顶面设置成与第一管芯堆叠件的顶面距插件相同的距离；以及散热器，位于散热管芯的顶面和第二管芯堆叠件的顶面上。在器件的一些实施例中，第二管芯堆叠件包括：第一集成电路管芯；第二集成电路管芯，接合至第一集成电路管芯，第二集成电路管芯包括第一导电通孔；密封剂，位于第二集成电路管芯周围；以及再分布结构，位于密封剂和第二集成电路管芯上，再分布结构连接至第一导电通孔和插件。在器件的一些实施例中，第二管芯堆叠件还包括：第二导电通孔，延伸穿过密封剂，第二导电通孔连接至第一集成电路管芯和再分布结构。在器件的一些实施例中，第二管芯堆叠件包括：密封剂；第一集成电路管芯，位于密封剂中；第二集成电路管芯，接合至第一集成电路管芯，第二集成电路管芯包括导电通孔；以及再分布结构，位于第二集成电路管芯上，再分布结构连接至导电通孔和插件。在一些实施例中，器件还包括：密封剂，位于第一管芯堆叠件、第二管芯堆叠件、和散热管芯周围，密封剂的顶面设置成与第一管芯堆叠件的顶面和散热管芯的顶面距插件相同的距离。
在一个实施例中，一种方法包括：将第一集成电路器件和第二集成电路器件接合至插件的正面；将散热管芯粘附至第一集成电路器件上；通过密封剂密封散热管芯、第一集成电路器件、和第二集成电路器件；薄化密封剂、散热管芯、和第二集成电路器件，直至密封剂的顶面与散热管芯的顶面和第一集成电路器件的顶面共面；以及将散热器粘附至密封剂的顶面、散热管芯的顶面、和第二集成电路器件的顶面。在方法的一些实施例中，密封剂的第一部分覆盖散热管芯的顶面，并且薄化密封剂去除了密封剂的第一部分。在方法的一些实施例中，第二集成电路器件的顶面设置成比第一集成电路器件的顶面更远离插件，散热管芯的顶面设置成比薄化散热管芯之前的第二集成电路器件的顶面更远离插件，并且散热管芯的顶面设置成与薄化散热管芯之后的第二集成电路器件的顶面距插件相同的距离。在方法的一些实施例中，第二集成电路器件是高带宽存储器(HBM)器件。在方法的一些实施例中，第一集成电路器件是集成芯片上系统(SoIC)器件。在方法的一些实施例中，第一集成电路器件是集成电路管芯。
前面概述了若干实施例的特征，使得本领域的技术人员可以更好地理解本公开的各个方面。本领域的技术人员应该理解，他们可以容易地使用本公开作为用于设计或修改用于执行与本公开相同或类似的目的和/或实现相同或类似优点的其他工艺和结构的基础。本领域的技术人员还应该意识到，这种等效结构不背离本公开的精神和范围，并且可以进行各种改变、替换和变更而不背离本公开的精神和范围。

Claims (10)

1.一种集成电路封装件，包括：
插件；
第一集成电路器件，连接至所述插件；
第二集成电路器件，连接至邻接所述第一集成电路器件的所述插件；
散热管芯，位于所述第二集成电路器件上；以及
密封剂，位于所述散热管芯、所述第二集成电路器件、和所述第一集成电路器件周围，所述密封剂的顶面与所述散热管芯的顶面和所述第一集成电路器件的顶面共面。
2.根据权利要求1所述的集成电路封装件，其中，所述散热管芯的所述顶面设置成与所述第一集成电路器件的所述顶面距所述插件相同的距离。
3.根据权利要求1所述的集成电路封装件，其中，所述散热管芯的宽度等于所述第二集成电路器件的宽度。
4.根据权利要求1所述的集成电路封装件，其中，所述散热管芯的宽度大于所述第二集成电路器件的宽度。
5.根据权利要求1所述的集成电路封装件，其中，所述散热管芯的宽度小于所述第二集成电路器件的宽度。
6.根据权利要求1所述的集成电路封装件，其中，所述散热管芯是设置在所述第二集成电路器件上的多个散热管芯之一。
7.根据权利要求1所述的集成电路封装件，其中，所述第一集成电路器件是第一管芯堆叠件，所述第二集成电路器件是第二管芯堆叠件。
8.根据权利要求1所述的集成电路封装件，其中，所述第一集成电路器件是管芯堆叠件，而所述第二集成电路器件是集成电路管芯。
9.一种集成电路封装件，包括：
插件；
第一管芯堆叠件，接合至所述插件的正面；
第二管芯堆叠件，接合至所述插件的所述正面，所述第二管芯堆叠件的顶面设置成比所述第一管芯堆叠件的顶面更靠近所述插件；
散热管芯，位于所述第二管芯堆叠件上，所述散热管芯的顶面设置成与所述第一管芯堆叠件的所述顶面距所述插件相同的距离；以及
散热器，位于所述散热管芯的所述顶面和所述第二管芯堆叠件的所述顶面上。
10.一种形成集成电路封装件的方法，包括：
将第一集成电路器件和第二集成电路器件接合至插件的正面；
将散热管芯粘附至所述第一集成电路器件上；
通过密封剂密封所述散热管芯、所述第一集成电路器件、和所述第二集成电路器件；
薄化所述密封剂、所述散热管芯、和所述第二集成电路器件，直至所述密封剂的顶面与所述散热管芯的顶面和所述第一集成电路器件的顶面共面；以及
将散热器粘附至所述密封剂的所述顶面、所述散热管芯的所述顶面、和所述第二集成电路器件的所述顶面。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12087729B2 (en) * 2021-04-30 2024-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package having stress relief structure
US11610878B1 (en) * 2021-09-02 2023-03-21 Nanya Technology Corporation Semiconductor device with stacked chips and method for fabricating the same
US20240186274A1 (en) * 2022-12-01 2024-06-06 Micron Technology, Inc. Techniques for thermal distribution in coupled semiconductor systems

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8564124B2 (en) * 2006-03-07 2013-10-22 International Rectifier Corporation Semiconductor package
TWI361466B (en) * 2006-12-29 2012-04-01 Siliconware Precision Industries Co Ltd Method for fabricating heat-dissipating package and heat-dissipating structure applicable thereto
TWI398943B (zh) * 2010-08-25 2013-06-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8816495B2 (en) * 2012-02-16 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structures and formation methods of packages with heat sinks
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US10714378B2 (en) * 2012-11-15 2020-07-14 Amkor Technology, Inc. Semiconductor device package and manufacturing method thereof
US10032696B2 (en) * 2012-12-21 2018-07-24 Nvidia Corporation Chip package using interposer substrate with through-silicon vias
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
JP2014187346A (ja) * 2013-02-22 2014-10-02 Tokyo Electron Ltd 焼結銀被覆膜の作製方法及び焼成装置及び半導体装置
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
KR102424402B1 (ko) 2015-08-13 2022-07-25 삼성전자주식회사 반도체 패키지 및 그 제조방법
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10170457B2 (en) * 2016-12-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and method of forming the same
KR20180090527A (ko) 2017-02-03 2018-08-13 삼성전기주식회사 반도체 패키지와 그 제조 방법
US10290571B2 (en) 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
KR102404058B1 (ko) * 2017-12-28 2022-05-31 삼성전자주식회사 반도체 패키지
CN111133575A (zh) * 2017-12-29 2020-05-08 英特尔公司 具有通信网络的微电子组件
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US10672674B2 (en) * 2018-06-29 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device package having testing pads on a topmost die
KR102609445B1 (ko) 2018-10-22 2023-12-04 삼성전자주식회사 반도체 패키지
KR102480014B1 (ko) 2018-11-23 2022-12-21 삼성전자 주식회사 반도체 패키지 및 그의 제조 방법
US10770430B1 (en) * 2019-03-22 2020-09-08 Xilinx, Inc. Package integration for memory devices
US11282759B2 (en) * 2019-09-09 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure having warpage control and method of forming the same
US11164855B2 (en) * 2019-09-17 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure with a heat dissipating element and method of manufacturing the same
KR102702093B1 (ko) * 2019-11-27 2024-09-04 삼성전자주식회사 반도체 패키지
US11145639B2 (en) * 2019-12-17 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11450581B2 (en) * 2020-08-26 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11309291B2 (en) * 2020-09-20 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure and manufacturing method thereof

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US11848246B2 (en) 2023-12-19
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KR20240005646A (ko) 2024-01-12
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