CN112530913A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

Info

Publication number
CN112530913A
CN112530913A CN202010096503.9A CN202010096503A CN112530913A CN 112530913 A CN112530913 A CN 112530913A CN 202010096503 A CN202010096503 A CN 202010096503A CN 112530913 A CN112530913 A CN 112530913A
Authority
CN
China
Prior art keywords
semiconductor die
semiconductor
package structure
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010096503.9A
Other languages
English (en)
Inventor
陈伟铭
吴集锡
吴志伟
丁国强
卢思维
侯上勇
施应庆
邹贤儒
李澄杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112530913A publication Critical patent/CN112530913A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141—Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H01L2224/11424—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27416—Spin coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27422—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/27515—Curing and solidification, e.g. of a photosensitive layer material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/83409—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/83487—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83499—Material of the matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83598—Fillers
    • H01L2224/83599—Base material
    • H01L2224/836—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83598—Fillers
    • H01L2224/83599—Base material
    • H01L2224/836—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露实施例是有关于一种封装结构及其制造方法。一种封装结构包括电路元件、第一半导体管芯、第二半导体管芯、散热元件以及绝缘包封体。第一半导体管芯及第二半导体管芯位于电路元件上。散热元件连接到第一半导体管芯，且第一半导体管芯位于电路元件与散热元件之间，其中第一半导体管芯的第一厚度与散热元件的第三厚度之和实质上等于第二半导体管芯的第二厚度。绝缘包封体包封第一半导体管芯、第二半导体管芯及散热元件，其中散热元件的表面与绝缘包封体实质上齐平。

Description

封装结构及其制造方法
技术领域
本揭露实施例是有关于一种封装结构及其制造方法。
背景技术
半导体器件及集成电路(integrated circuit，IC)通常是在单个半导体晶片上制造。在晶片级工艺中，可对晶片的管芯进行加工并与其他半导体装置或其他管芯封装在一起，且用于晶片级封装的各种技术(例如，形成重布线路结构/层)已被开发。另外，这种封装可在切分(dicing)之后进一步集成/整合到半导体衬底或载体。
发明内容
本揭露实施例提供一种封装结构，所述封装结构包括电路元件、第一半导体管芯、第二半导体管芯、散热元件以及绝缘包封体。所述第一半导体管芯及所述第二半导体管芯位于所述电路元件上。所述散热元件连接到所述第一半导体管芯，且所述第一半导体管芯位于所述电路元件与所述散热元件之间，其中所述第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述第二半导体管芯的第二厚度。所述绝缘包封体包封所述第一半导体管芯、所述第二半导体管芯及所述散热元件，其中所述散热元件的表面与所述绝缘包封体的表面实质上齐平。
本揭露实施例提供一种制造封装结构的方法包括以下步骤，提供连接有散热元件的第一半导体管芯；提供第二半导体管芯；将所述第一半导体管芯、所述第二半导体管芯及所述散热元件包封在绝缘包封体中；以及将所述绝缘包封体平坦化，以使所述绝缘包封体暴露出所述散热元件，其中所述第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述第二半导体管芯的第二厚度。
本揭露实施例提供一种制造封装结构的方法包括以下步骤，提供至少一个第一半导体管芯及至少一个第二半导体管芯；在所述至少一个第一半导体管芯的表面上设置虚设元件，所述至少一个第一半导体管芯位于所述虚设元件之上；将所述至少一个第一半导体管芯、所述至少一个第二半导体管芯及所述虚设元件包封在绝缘包封体中；将所述绝缘包封体平坦化，以使所述绝缘包封体的表面暴露出所述虚设元件；移除所述虚设元件，以在所述绝缘包封体中形成凹槽；以及在所述至少一个第一半导体管芯上及在所述凹槽中设置散热元件，其中所述至少一个第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述至少一个第二半导体管芯的第二厚度。
附图说明
接合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的尺寸。
图1到图13及图14A是根据本公开一些实施例的封装结构的制造方法中的各个阶段的示意性剖面图。
图14B是根据本公开一些实施例的封装结构的示意性剖面图。
图15是根据本公开一些实施例的封装结构的示意性剖面图。
图16是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图17是根据本公开一些实施例的封装结构的示意性剖面图。
图18到图19是根据本公开一些实施例的封装结构的制造方法中的各个阶段的示意性剖面图。
图20是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图21A及图21B是根据本公开一些实施例的封装结构的示意性剖面图。
图22是根据本公开一些实施例的封装结构的示意性剖面图。
图23是根据本公开一些实施例的封装结构的示意性剖面图。
图24到图33A是根据本公开一些实施例的封装结构的制造方法中的各个阶段的示意性剖面图。
图33B是根据本公开一些实施例的封装结构的示意性剖面图。
图34是根据本公开一些实施例的封装结构的示意性剖面图。
图35是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图36是根据本公开一些实施例的封装结构的示意性剖面图。
图37是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图38是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图39是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图40是根据本公开一些实施例的封装结构的示意性剖面图。
图41是根据本公开一些实施例的封装结构的示意性剖面图。
图42是根据本公开一些实施例的封装结构的示意性剖面图。
图43是根据本公开一些实施例的封装结构的示意性剖面图。
图44是根据本公开一些实施例的封装结构的示意性剖面图。
图45是根据本公开一些实施例的封装结构的示意性剖面图。
图46是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图47是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图48是示出根据本公开一些实施例的制造封装结构的方法的流程图。
图49是根据本公开一些实施例的封装结构的示意性剖面图。
[符号的说明]
10a、10b、10c、10d、10e、10f、30：半导体组件
20：第二半导体组件/半导体组件
20b、110b、210b、320b、S1：底表面
22、33、140、CP1、CP2：导通孔
31、110：半导体衬底
31a：有源表面
32、120：内连结构
32a、122：层间介电层
32b、124：图案化导电层
41、310、500：衬底
42、340、800：重布线路结构
42a、342：介电结构
42b、344、530、804：金属化层
43、320：穿孔
100：第一半导体管芯/半导体管芯
110a、210a、220a：顶表面
130：钝化层
130a、310a、310b、400a、700a、700b、702a、S2、S3：表面
210：基底层
220：粘着层
360、380：导电连接件
400、400m、700、702：绝缘包封体
510、520：接合垫
540、550：表面器件
560：导电元件
600：散热盖
610：热界面材料
620：接合元件
802、PM1：介电层
900：导电端子
BE：桥接元件
C1：载体
D1、D2、D3：偏移
DE：虚设元件
HD1、HD2：固持器件
HDE：散热元件
O1：开口
P1A、P1B、P1C、P1D、P1E、P1F、P2A、P2C、P2E、P2F、P3A、P3C、P3E、P4A、P4B、P5A、P5B、P6A、P6B、P7A、P7B：封装结构
R：凹槽
S10、S11、S12、S13、S14、S15、S16、S17、S18、S19、S20、S21、S22、S23、S24、S25、S26、S27、S30、S31、S32、S33、S34、S35、S36、S37、S38、S40、S41、S42、S43、S44、S45、S46、S50、S51、S52、S53、S54、S55、S60、S61、S62、S63、S64、S65、S66、S70、S71、S72、S73、S74、S75、S76、S77、S78、S79、S80、S81、S82、S83、S84、S85、S86、S87、S88、S90、S91、S92、S93、S94、S95、S96、S97、S98、S99：步骤
T1、T1’：总厚度
u1：球下金属(UBM)图案
UF1、UF2：底部填充胶
W1、W2：晶片
Z：堆叠方向
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件、值、操作、材料、布置等的具体实例以简化本公开。当然，这些仅为实例而非旨在进行限制。预期存在其他组件、值、操作、材料、布置等。举例来说，以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例，且还可包括其中第一特征与第二特征之间可形成有附加特征从而使得所述第一特征与所述第二特征可不直接接触的实施例。另外，本公开可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身指示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性描述语可同样相应地进行解释。
另外，为易于说明，本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”、“第四(fourth)”、“第五(fifth)”等用语来阐述图中所示的相似的元件或特征或者不同的元件或特征，且可依据呈现次序或说明的上下文而互换地使用。
本公开还可包括其他特征及工艺。举例来说，可包括测试结构以帮助对三维(three-dimensional，3D)封装或三维集成电路(three-dimensional integratedcircuit，3DIC)器件进行验证测试。所述测试结构可包括例如在重布线层中或在衬底上形成的测试焊盘，以使得能够对3D封装或3DIC进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法来使用，以提高良率(yield)并降低成本。
图1到图13及图14A是根据本公开一些实施例的封装结构的制造方法中的各个阶段的示意性剖面图。图14B是根据本公开一些实施例的封装结构的示意性剖面图。图15是根据本公开一些实施例的封装结构的示意性剖面图。图16是示出根据本公开一些实施例的制造封装结构的方法的流程图。图17是根据本公开一些实施例的封装结构的示意性剖面图。在图1到图14A、图14B、图15及图17中，示出一个或多于一个(半导体)芯片或管芯来表示晶片的多个(半导体)芯片或管芯，且示出一个(半导体)封装结构来表示在(半导体)制造方法之后获得的多个(半导体)封装结构，本公开并非仅限于此。在其他实施例中，示出一个或多于一个(半导体)芯片或管芯来表示晶片的多个(半导体)芯片或管芯，且示出一个或多于一个(半导体)封装结构来表示在(半导体)制造方法之后获得的多个(半导体)封装结构。
参照图1，在一些实施例中，根据图16的步骤S10，提供包括布置成阵列的多个半导体管芯100的晶片W1。在对晶片W1执行晶片锯切(sawing)或切分(dicing)工艺之前，晶片W1的半导体管芯100为彼此连接，如图1中所示。在一些实施例中，晶片W1包括半导体衬底110、设置在半导体衬底110上的内连结构120以及覆盖内连结构120的钝化层130。如图1中所示，例如，半导体衬底110具有顶表面110a以及与顶表面110a相对的底表面110b，且内连结构120位于半导体衬底110的顶表面110a上且夹置在半导体衬底110与钝化层130之间。
在一些实施例中，半导体衬底110可为硅衬底，所述硅衬底包括形成在其中的有源组件(例如晶体管和/或存储器(例如N型金属氧化物半导体(N-type metal-oxidesemiconductor，NMOS)和/或P型金属氧化物半导体(P-type metal-oxide semiconductor，PMOS)器件等))和/或无源组件(例如电阻器、电容器、电感器等)。在一些实施例中，此种有源组件及无源组件可在前段(front-end-of-line，FEOL)工艺中形成。在替代实施例中，半导体衬底110可为块状硅衬底，例如块状单晶硅衬底、经掺杂的硅衬底、未经掺杂的硅衬底或绝缘体上有硅(silicon-on-insulator，SOI)衬底，其中经掺杂的硅衬底的掺杂剂可为N型掺杂剂、P型掺杂剂或其组合。本公开并非仅限于此。
半导体衬底110可包含例如以下其他半导体材料：锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP；或者其组合。也可使用其他衬底，例如多层式(multi-layered)衬底或梯度衬底(gradient substrate)。半导体衬底110具有有时被称为前侧的有源表面(例如，顶表面110a)以及有时被称为背侧的非有源表面(例如，底表面110b)。
在一些实施例中，内连结构120可包括交替地堆叠的一个或多个层间介电层122与一个或多个图案化导电层124。举例来说，层间介电层122可为氧化硅层、氮化硅层、氮氧化硅层或由其他合适的介电材料形成的介电层，且层间介电层122可通过沉积等形成。举例来说，图案化导电层124可为图案化铜层或其他合适的图案化金属层，且图案化导电层124可通过电镀或沉积形成。然而，本公开并非仅限于此。在一些实施例中，图案化导电层124可通过双镶嵌方法形成。层间介电层122的数目及图案化导电层124的数目可小于或大于图1中所绘示的数目，且可基于需要和/或设计布局来指定；本公开并非特别限制于此。在说明通篇中，用语“铜”旨在包括实质上纯的元素铜、包含不可避免的杂质的铜、以及包含少量元素(例如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆等)的铜合金。
在某些实施例中，如图1中所示，图案化导电层124夹置在层间介电层122之间，其中图案化导电层124的最顶层的顶表面至少局部地被形成在层间介电层122的最顶层中的多个开口O1暴露出以连接到稍后形成的组件以进行电连接，且图案化导电层124的最低层的底表面至少局部地被形成在层间介电层122的最低层中的多个开口(未标记)暴露出且电连接到半导体衬底110中所包括的有源组件和/或无源组件。开口O1及形成在层间介电层122的最低层中的开口的形状及数目在本公开中不受限制，且可基于需要和/或设计布局来指定。
本公开并非仅限于此。在替代实施例(未示出)中，图案化导电层124可夹置在层间介电层122之间，其中图案化导电层124的最顶层的顶表面可被层间介电层122完全覆盖以防止由后续工艺引起的损坏，且图案化导电层124的最低层的底表面可至少局部地被形成在层间介电层122的最低层中的开口暴露出且电连接到下伏的有源组件和/或无源组件。举例来说，通过后续图案化工艺，被层间介电层122的最顶层覆盖的图案化导电层124的最顶层的顶表面可被形成在层间介电层122的最顶层中的多个开口暴露出以电连接到稍后形成的上覆在图案化导电层124的最顶层的顶表面上的组件。
在一些实施例中，如图1中所示，钝化层130形成在内连结构120上，其中内连结构120被钝化层130覆盖且与钝化层130接触。如图1中所示，例如，钝化层130具有实质上平坦的表面130a。在某些实施例中，钝化层130的表面130a可为齐平的且可具有高平坦度及高平面度，这对于稍后形成的层是有益的。在一些实施例中，钝化层130可为聚酰亚胺(polyimide，PI)层、聚苯并恶唑(polybenzoxazole，PBO)层、二氧化硅系(非有机)层或其他合适的聚合物(或有机)层，且可通过沉积等形成。本公开并非仅限于此。在一些实施例中，钝化层130完全覆盖图案化导电层124的最顶层及层间介电层122的最顶层，其中内连结构120被钝化层130良好地保护起来，免受由后续工艺引起的损坏。如图1中所示，例如，内连结构120位于半导体衬底110的顶表面110a与钝化层130之间。本公开并不特别限制钝化层130的厚度，只要钝化层130的表面130a可保持其高平坦度及高平面度即可。在本公开中，钝化层的表面130a可被称为半导体管芯100的顶表面。
继续图1，在一些实施例中，根据图16的步骤S11，还提供包括布置成阵列的多个散热元件HDE的晶片W2。在对晶片W2执行晶片锯切或切分工艺之前，晶片W2的散热元件HDE为彼此连接，如图1中所示。在本公开中，散热元件HDE还被称为散热器元件(heat spreaderelement)。在一些实施例中，晶片W2包括基底层210及涂布在基底层(base layer)210上的粘着层220。如图1中所示，例如，基底层210具有顶表面210a及与顶表面210a相对的底表面210b，且粘着层220形成在基底层210的顶表面210a上。在本公开中，基底层210的材料与粘着层220的材料不同。在晶片W2包括基底层210及粘着层220的实施例中，晶片W2中所包括的基底层210与粘着层220在本公开中一起被称为一个散热元件HDE。
然而，本公开并非仅限于此；在替代实施例中，可从晶片W2省略粘着层220。也就是说，在晶片W2不包括粘着层220的实施例中，晶片W2中所包括的基底层210在本公开中被单独称为一个散热元件HDE。
在一些实施例中，给定基底层210具有比稍后形成的绝缘包封体大的导热系数(thermal conductivity coefficient)，基底层210可包括硅系层(例如硅衬底或氧化硅层)、陶瓷层、金属膜(例如铜(Cu)膜、铝(Al)膜、铟(In)膜或银(Ag)膜)、由金属膏(例如Ag膏、Cu膏、纳米Ag膏或纳米Cu膏)形成的层、聚合物层、化合物层或由任何合适的其他材料制成的层。
在一些实施例中，给定粘着层220具有比稍后形成的绝缘包封体大的导热系数且能够将基底层210粘着到将设置在基底层210上方的任何层或任何晶片(例如晶片W1)，粘着层220可包括硅系层(例如氧化硅层、氮化硅层)、由金属膏形成的层、聚合物层或由任何合适的其他材料制成的层。举例来说，粘着层220可为管芯贴合膜(die attach film，DAF)、液态DAF、胶层或粘着条带(adhesive tape)。在一些实施例中，粘着层220可通过叠层(lamination)、旋转涂布方法、浸渍涂布方法或合适的涂布方法形成在基底层210上。举例来说，粘着层220可作为液体(例如液态DAF)分配在基底层210上并被固化，或者可为叠层到基底层210上的叠层膜(例如DAF)。本公开并非仅限于此。粘着层220的顶表面220a可为齐平的且可具有高共面度。
一起参照图1与图2，在一些实施例中，根据图16的步骤S11，将晶片W1拾取并放置在晶片W2上，且将晶片W1接合到晶片W2。举例来说，图2中所绘示的结构的总厚度T1介于从100微米(μm)到2000μm的范围内。如图2中所示，半导体衬底110位于内连结构120与基底层210之间，内连结构120位于钝化层130与半导体衬底110之间，且粘着层220位于半导体衬底110与基底层210之间。在本公开中，基底层210与粘着层220(如果有的话)独立地热耦合到晶片W1的半导体衬底110。换句话说，晶片W2中所包括的散热元件HDE热耦合到晶片W1中所包括的半导体管芯100中的每一者。
在一些实施例中，如图1及图2中所示，晶片W1的半导体衬底110的底表面110b面朝晶片W2的粘着层220的顶表面220a，其中晶片W1是通过借助粘着层220将半导体衬底110接合到基底层210(例如间接接合方法)而接合到晶片W2。在一个实施例中，在使用由具有粘着特性的材料(例如金属膏、聚合物等)制成的粘着层220将晶片W1的半导体衬底110接合到晶片W2的基底层210时，晶片W1是通过黏合(adhesion)而接合到晶片W2。在替代实施例中，在使用由材料(例如硅系层)制成的粘着层220将晶片W1的半导体衬底110接合到晶片W2的基底层210时，晶片W1是通过熔合接合(fusion bonding)而接合到晶片W2。也就是说，通过粘着层220，晶片W1的半导体衬底110通过黏合或熔合接合而间接接合到晶片W2的基底层210。应理解，在本公开的实施例中，由于粘着层220的存在，基底层210的材料与粘着层220的材料不同。
然而，本公开并非仅限于此；在省略粘着层220的替代实施例中，晶片W1可通过粘着或熔合接合而直接接合到晶片W2。也就是说，晶片W1的半导体衬底110的底表面110b面朝晶片W2的基底层210的顶表面210a，其中晶片W1通过将半导体衬底110的底表面110b实体地接合到基底层210的顶表面210a(例如，直接接合方法)而接合到晶片W2。在一个实施例中，在将由具有粘着特性的材料(例如金属膏、聚合物等)制成的基底层210用于直接接合到晶片W1的半导体衬底110时，晶片W1是通过粘合而接合到晶片W2。在替代实施例中，在将由材料(例如硅系层)制成的基底层210用于直接接合到晶片W1的半导体衬底110时，晶片W1是通过熔合接合而接合到晶片W2。也就是说，由于基底层210，晶片W1的半导体衬底110通过粘合或熔合接合而直接接合到晶片W2的基底层210。
参照图3，在一些实施例中，对基底层210的底表面210b执行平坦化步骤。在平坦化之后，基底层210可被认为是经平坦化的基底层或经薄化的基底层。在一些实施例中，图3中所绘示的平坦化结构的总厚度T1’可介于从100μm到1200μm的范围内。在一些实施例中，平坦化步骤可包括研磨工艺或化学机械抛光(chemical mechanical polishing，CMP)工艺。在平坦化步骤之后，可视需要执行清洁步骤，例如清洁及移除平坦化步骤所产生的残留物。然而，本公开并非仅限于此，且平坦化步骤可通过任何其他合适的方法来执行。
在某些实施例中，为了促进前述于图3中所绘示的工艺，可通过使钝化层130与粘着膜(未示出)接触，而使图2中所绘示的结构与支撑件(未示出)临时粘合或与临时载体(未示出，例如粘着条带、粘着载体、吸力垫等)临时粘合。然而，本公开并非仅限于此。在一个实施例中，在半导体衬底110的厚度足够厚以执行前述于图3中所绘示的工艺而不会产生损坏(例如裂纹或破碎的晶片)时，则无需将钝化层130与支撑件临时粘合。
参照图4，在一些实施例中，在内连结构120上及半导体衬底110之上形成多个导通孔140，且导通孔140的侧壁被钝化层130包绕。在一些实施例中，如图4中所示，导通孔140各自穿透钝化层130且延伸到形成在层间介电层122的最顶层中的开口O1中以实体地接触被开口O1暴露出的图案化导电层124的最顶层的顶表面。通过内连结构120，导通孔140电连接到半导体衬底110中所包括的有源组件和/或无源组件。
应理解，半导体管芯100各自至少包括半导体衬底110、内连结构120、钝化层130及导通孔140。在一些实施例中，本文中所阐述的半导体管芯100中的每一者可被称为半导体芯片或集成电路(IC)。在一些实施例中，半导体管芯100各自为逻辑芯片，例如中央处理器(central processing unit，CPU)、图形处理单元(graphic processing unit，GPU)、系统芯片(system-on-a-chip，SoC)、微控制器等。然而，本公开并非仅限于此；在替代实施例中，半导体管芯100可独立地包括一个或多个数字芯片、模拟芯片或混合信号芯片，例如应用专用集成电路(application-specific integrated circuit，“ASIC”)芯片、传感器芯片、无线及射频(radio frequency，RF)芯片、存储器芯片或电压调节器芯片。在一些替代实施例中，半导体管芯100可独立地被称为组合类型的芯片或IC，例如同时包括RF芯片及数字芯片二者的WiFi芯片。
在一些实施例中，如图4中所示，对于每一半导体管芯100，与内连结构120实体地接触的导通孔140远离钝化层130的表面130a延伸。为了简化起见，出于例示目的，在图4中在每一半导体管芯100中仅呈现出两个导通孔140，然而应注意，可形成多于两个导通孔140；本公开并非仅限于此。在一些实施例中，在半导体衬底110的顶表面110a上沿半导体衬底110、内连结构120及钝化层130的堆叠方向Z的垂直投影中，导通孔140可独立地为圆形、椭圆形、三角形、矩形等。导通孔140的形状在本公开中不受限制。导通孔140的数目及形状可基于需要来指定及选择，且通过改变开口O1的数目及形状来进行调整。
在一些实施例中，导通孔140是通过光刻、镀覆、光刻胶剥除工艺(photoresiststripping process)或任何其他合适的方法形成。举例来说，镀覆工艺可包括电镀、无电镀覆等。在一个实施例中，导通孔140可通过以下方式形成：形成覆盖钝化层130的掩模图案(未示出)，所述掩模图案具有多个开口(未示出)，所述开口与被开口O1暴露出的图案化导电层124的最顶层的顶表面对应；将钝化层130图案化以在钝化层130中形成多个接触开口(未示出)，从而暴露出被开口O1暴露出的图案化导电层124的最顶层的顶表面；通过电镀或沉积形成填充形成在掩模图案中的开口、形成在钝化层130中的接触开口以及开口O1的金属材料以形成多个导通孔140；以及接着移除掩模图案。在一些实施例中，可通过刻蚀工艺(例如干式刻蚀工艺、湿式刻蚀工艺或其组合)来将钝化层130图案化。应注意，形成在钝化层130中的接触开口与位于钝化层130之下的相应的一个开口O1在空间上彼此连通以形成导通孔140。在一个实施例中，掩模图案可通过可接受的灰化工艺和/或光刻胶剥除工艺(例如使用氧等离子体等)来移除。在一个实施例中，导通孔140的材料可包括金属材料，例如铜或铜合金等。
在一些替代实施例中，导通孔140可通过以下方式形成：形成覆盖钝化层130的第一掩模图案(未示出)，所述第一掩模图案具有多个开口(未示出)，所述开口与被开口O1暴露出的图案化导电层124的最顶层的顶表面对应；将钝化层130图案化以在钝化层130中形成多个接触开口(未示出)，从而暴露出被开口O1暴露出的图案化导电层124的最顶层的顶表面；移除第一掩模图案；在钝化层130之上共形地形成金属晶种层；形成覆盖钝化层130与金属晶种层的第二掩模图案(未示出)，所述第二掩模图案具有暴露出形成在钝化层130中的接触开口以及开口O1的多个开口(未示出)；通过电镀或沉积形成填充形成在第二掩模图案中的开口、形成在钝化层130中的接触开口以及开口O1的金属材料；移除第二掩模图案；以及接着移除未被金属材料覆盖的金属晶种层以形成多个导通孔140。在一些实施例中，金属晶种层被称为金属层，所述金属层可为单个层或包括由不同材料形成的多个子层的组合层。在一些实施例中，金属晶种层包含钛、铜、钼、钨、氮化钛、钛钨、其组合等。举例来说，金属晶种层可包括钛层及位于钛层之上的铜层。金属晶种层可使用例如溅镀、物理气相沉积(physical vapor deposition，PVD)等来形成。
参照图5，在一些实施例中，根据图16的步骤S12，对图4中所绘示的结构执行切分(单体化)工艺，以使得图4中所绘示的结构被切割成单独且分开的多个半导体组件10a。在一些实施例中，如图5中所示，采用固持器件HD1来固定图4中所绘示的结构以防止在切分(单体化)工艺期间对半导体组件10a的任何损坏。在一个实施例中，在切分(单体化)工艺期间，固持器件HD1不被切割，然而本公开并非仅限于此。在替代实施例(未示出)中，在切分(单体化)工艺期间，固持器件HD1可被局部地切割。举例来说，固持器件HD1可为粘着条带、粘着载体或吸力垫，本公开并非仅限于此。在一个实施例中，切分(单体化)工艺是晶片切分工艺或晶片单体化工艺，所述晶片切分工艺或晶片单体化工艺可包括机械锯切或激光切割。本公开并非仅限于此。至此，半导体组件10a得以制造完成，其中半导体组件10a中的每一者包括连接有一个散热元件HDE的一个半导体管芯100。在本公开中，在半导体组件10a中的每一者中，散热元件HDE热耦合到半导体管芯100。如图5中所示，散热元件HDE的侧壁与半导体管芯100的侧壁对齐。
参照图6，在一些实施例中，根据图16的步骤S13，提供衬底310，其中半导体组件10a(图5中所绘示的半导体组件10a)及至少一个半导体组件20被拾取并放置在衬底310上，且通过倒装芯片接合而接合到衬底310。在一些实施例中，衬底310可为晶片，例如块状半导体衬底、SOI衬底、多层式半导体衬底等。在一些实施例中，衬底310的半导体材料可为：硅、锗；化合物半导体，包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP；或者其组合。在替代实施例中，也可使用其他衬底，例如多层式衬底或梯度衬底。衬底310例如可为经掺杂的或未经掺杂的且可还包括有源器件和/或无源器件，例如形成在衬底310中和/或衬底310的表面310a上的晶体管、电容器、电阻器、二极管等。在一些实施例中，表面310a可被称为衬底310的有源表面(或前侧)。在某些实施例中，衬底310可实质上不包含有源器件和/或无源器件，本公开并非仅限于此。
在一些实施例中，在衬底310中形成从衬底310的表面310a延伸的多个穿孔320。举例来说，由于衬底310是硅衬底，因此穿孔320有时被称为衬底穿孔(through-substrate-via)或硅穿孔(through-silicon-via)。穿孔320可通过例如刻蚀、铣削(milling)、激光技术、其组合、和/或类似技术在衬底310中形成凹槽来形成。可例如通过使用氧化技术在凹槽中形成薄的介电材料。可例如通过化学气相沉积(chemical vapor deposition，CVD)、原子层沉积(atomic layer deposition，ALD)、PVD、热氧化、其组合、和/或类似技术在衬底310的表面310a之上及开口中共形地沉积薄的阻挡层。阻挡层可包含氮化物或氮氧化物，例如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、其组合、和/或类似材料。可在薄的阻挡层之上及开口中沉积导电材料。导电材料可通过电化学镀覆工艺、CVD、ALD、PVD、其组合、和/或类似工艺形成。导电材料的实例是铜、钨、铝、银、金、其组合、和/或类似材料。通过例如CMP从衬底310的表面310a移除多余的导电材料及阻挡层。因此，穿孔320可包含导电材料以及位于导电材料与衬底310之间的薄的阻挡层。
在一些实施例中，在衬底310的表面310a上形成重布线路结构340，且将重布线路结构340电连接到衬底310。在某些实施例中，重布线路结构340用于提供布线功能且包括介电结构342及布置在介电结构342中的一个或多个金属化层344。在一些实施例中，介电结构342包括一个或多个介电层，以使得介电层及金属化层344依序形成，且一个金属化层344夹置在两个介电层之间。如图6中所示，金属化层344的最顶层的顶表面的部分分别被形成在介电结构342的最顶部介电层中的多个开口暴露出，且金属化层344的最底层的底表面的部分分别被形成在介电结构342的最底部介电层中的多个开口暴露出。然而，本公开并非仅限于此。重布线路结构340中所包括的金属化层的数目及介电层的数目并非仅限于此，且可基于需要来指定及选择。介电结构342的材料及形成可与层间介电层122的材料及形成相同或相似，金属化层344的材料及形成可与图案化导电层124的材料及形成相同或相似，且因此在本文中不再重复。如图6中所示，穿孔320连接到金属化层344的最底层的底表面的分别被形成在介电结构342的最底部介电层中的开口暴露出的部分。换句话说，重布线路结构340电连接到穿孔320。在替代实施例中，重布线路结构340可还电连接到嵌置在衬底310中或形成在衬底310的表面310a上的有源器件和/或无源器件。
在一些实施例中，在重布线路结构340上形成多个导电连接件360。如图6中所示，例如，导电连接件360形成在金属化层344的最顶层的顶表面的分别被形成在介电结构342的最顶部介电层中的开口暴露出的部分上且连接到金属化层344的最顶层的顶表面的分别被形成在介电结构342的最顶部介电层中的开口暴露出的部分。换句话说，导电连接件360电连接到重布线路结构340。在替代实施例中，通过重布线路结构340，导电连接件360中的一些导电连接件360可还电连接到衬底310(例如，嵌置在衬底310中或形成在表面310a上的有源器件和/或无源器件)及穿孔320。
在一些实施例中，导电连接件360可包括球栅阵列(ball grid array，BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、微凸块、无电镀镍钯浸金(electroless nickel-electroless palladium-immersiongold，ENEPIG)技术形成的凸块等。导电连接件360的材料例如可包括导电材料，例如焊料、铜、铝、金、镍、银、钯、锡等、或者其组合。在一个实施例中，导电连接件360的材料例如可为不包含焊料的。导电连接件360的剖面图并非仅限于所述实施例，且可基于需要具有任何合适的形状。
继续图6，在一些实施例中，本文中所阐述的半导体组件20中的每一者可被称为具有多个导通孔22的半导体芯片或集成电路(IC)，其中导通孔22用作半导体组件20的导电端子以电连接到外部组件。在一些实施例中，半导体组件20各自为存储器芯片或器件，例如动态随机存取存储器(dynamic random access memory，DRAM)管芯、静态随机存取存储器(static random access memory，SRAM)管芯、混合存储器立方体(hybrid memory cube，HMC)模块、高带宽存储器(high bandwidth memory，HBM)模块等。然而，本公开并非仅限于此；在替代实施例中，半导体组件20可独立地包括一个或多个数字芯片、模拟芯片或混合信号芯片，例如应用专用集成电路(“ASIC”)芯片、传感器芯片、无线及射频(RF)芯片、逻辑芯片或电压调节器芯片。在一些替代实施例中，半导体组件20可独立地被称为组合类型的芯片或IC，例如同时包括RF芯片及数字芯片二者的WiFi芯片。
在一个实施例中，半导体组件10a的半导体管芯100与半导体组件20可为相同类型或不同类型的管芯。在一个实施例中，半导体组件10a的半导体管芯100与半导体组件20可在相同技术节点的工艺中形成，或者可在不同技术节点的工艺中形成。举例来说，半导体组件10a的半导体管芯100可具有比半导体组件20先进的工艺节点；反之亦然。
在一些实施例中，半导体组件10a的半导体管芯100与半导体组件20具有不同的大小(例如，沿堆叠方向Z测量的不同高度和/或不同表面积)。举例来说，如图6中所示，半导体组件10a的半导体管芯100的高度小于半导体组件20的高度，且半导体组件10a的高度大于半导体组件20的高度。然而，本公开并非仅限于此；对于另一实例，半导体组件10a的半导体管芯100的高度小于半导体组件20的高度，且半导体组件10a的高度实质上等于半导体组件20的高度。
在一些实施例中，如图6中所示，半导体组件10a通过导通孔140及导电连接件360电连接到衬底310，而半导体组件20通过导通孔22及导电连接件360电连接到衬底310。在一些实施例中，半导体组件10a与半导体组件20通过重布线路结构340及导电连接件360彼此电连通(electrical communicated)。
在一些实施例中，底部填充胶UF1至少填充半导体组件10a与重布线路结构340之间的间隙以及半导体组件20与重布线路结构340之间的间隙，且包绕导通孔140的侧壁、导通孔22的侧壁及导电连接件360的侧壁。在一个实施例中，填充在半导体组件10a、20与重布线路结构340之间的间隙中的底部填充胶UF1彼此不连接。在另一实施例中，填充在半导体组件10a、20与重布线路结构340之间的间隙中的底部填充胶UF1彼此连接，本公开并非仅限于此。在一些替代实施例中，半导体组件10a的侧壁及半导体组件20的侧壁可被底部填充胶UF1覆盖。举例来说，底层填充胶UF1可为任何可接受的材料，例如聚合物、环氧树脂、模塑底部填充胶等。在一个实施例中，底部填充胶UF1可通过底部填充胶分配(underfilldispensing)、毛细流动工艺(capillary flow process)或任何其他合适的方法形成。
参照图7，在一些实施例中，根据图16的步骤S14，在衬底310之上形成绝缘包封体400m。举例来说，如图7中所示，半导体组件10a、半导体组件20被包封在绝缘包封体400m中，且被底部填充胶UF1暴露出的重布线路结构340被绝缘包封体400m覆盖。举例来说，绝缘包封体400m至少填充半导体组件10a、半导体组件20之间的间隙以及分别位于半导体组件10a、20之下的底部填充胶UF1之间的间隙。如图7中所示，例如，半导体组件10a、20及底部填充胶UF1被绝缘包封体400m环绕及覆盖。也就是说，半导体组件10a、20及底部填充胶UF1嵌置在绝缘包封体400m中。换句话说，半导体组件10a、20不被绝缘包封体400m以可触及的方式显露出且嵌置在绝缘包封体400m中。
在一些实施例中，绝缘包封体400m是通过模塑工艺形成的模塑化合物。在一些实施例中，绝缘包封体400m例如可包含聚合物(例如环氧树脂、酚醛树脂、含硅树脂或其他合适的树脂)、介电材料或其他合适的材料。在替代实施例中，绝缘包封体400m可包含可接受的绝缘包封体材料。在一些实施例中，绝缘包封体400m可还包含可被添加在绝缘包封体400m中以优化绝缘包封体400m的热膨胀系数(coefficient of thermal expansion，CTE)的无机填料或无机化合物(例如二氧化硅、粘土等)。本公开并非仅限于此。
一起参照图7与图8，在一些实施例中，根据图16的步骤S15，将绝缘包封体400m平坦化直到暴露出半导体组件10a的底表面(例如，基底层210的底表面210b)及半导体组件20的底表面20b。在将绝缘包封体400m平坦化之后，形成(经平坦化的)绝缘包封体400，且半导体组件10a的底表面(例如，基底层210的底表面210b)及半导体组件20的底表面20b被绝缘包封体400的表面400a暴露出。
在绝缘包封体400m的平坦化工艺期间中，也可独立将半导体组件10a、20平坦化。举例来说，绝缘包封体400可通过机械研磨或CMP形成。在平坦化工艺之后，可视需要执行清洁步骤，例如清洁及移除平坦化步骤所产生的残留物。然而，本公开并非仅限于此，且平坦化步骤可通过任何其他合适的方法来执行。如图8中所示，半导体组件10a的底表面(例如基底层210的底表面210b)及半导体组件20的底表面20b与绝缘包封体400的表面400a实质上齐平。也就是说，半导体组件10a的底表面(例如基底层210的底表面210b)、半导体组件20的底表面20b及绝缘包封体400的表面400a实质上彼此共面(coplanar)。换句话说，半导体组件10a、20被绝缘包封体400以可触及的方式显露出。
参照图9，在一些实施例中，在形成绝缘包封体400之后，将图8中所绘示的结构翻转(沿着堆叠方向Z颠倒)，且将绝缘包封体400放置在载体C1上。在一些替代实施例中，载体C1可还涂布有剥离层(未示出)。举例来说，剥离层设置在载体C1上，且剥离层的材料可为适合用于将载体C1从设置在载体C1上的上方层(例如，绝缘包封体400)或任何晶片进行接合及剥离的任何材料。在一些实施例中，剥离层可包括释放层(例如光热转换(light-to-heatconversion，“LTHC”)层)或粘着层(例如紫外可固化粘着层(ultra-violet curableadhesive layer)或热可固化粘着层(heat curable adhesive layer))。
参照图10，在一些实施例中，根据图16的步骤S16，然后将衬底310平坦化直到暴露出嵌置在衬底310中的穿孔320的底表面320b。在将衬底310平坦化之后，穿孔320的底表面320b被衬底310的表面310b暴露出。在衬底310的平坦化工艺期间，也可将穿孔320平坦化。举例来说，可通过机械研磨或CMP来将衬底310平坦化。在平坦化工艺之后，可视需要执行清洁步骤，例如清洁及移除平坦化步骤所产生的残留物。然而，本公开并非仅限于此，且平坦化步骤可通过任何其他合适的方法来执行。如图10中所示，穿孔320的底表面320b与衬底310的表面310b实质上齐平且共面。也就是说，穿孔320的底表面320b被衬底310以可触及的方式暴露出。
参照图11，在一些实施例中，根据图16的步骤S17，在衬底310上形成多个导电连接件380，其中导电连接件380连接到穿孔320。如图11中所示，例如，导电连接件380对应于穿孔320的定位位置而形成在衬底310上，且因此导电连接件380分别与穿孔320的底表面320b实体地接触。在一些实施例中，通过穿孔320、重布线路结构340及导电连接件360，导电连接件380中的一些导电连接件380电连接到半导体组件10a。在一些实施例中，通过穿孔320、重布线路结构340及导电连接件360，导电连接件380中的一些导电连接件380电连接到半导体组件20。在替代实施例中，导电连接件380中的一些导电连接件380可还电连接到嵌置在衬底310中或形成在衬底310的表面310a上的有源器件及无源器件。导电连接件380的材料及形成与导电连接件360的材料及形成相同或相似，且因此本文中可不再重复。在一个实施例中，导电连接件380可与导电连接件360相同。在替代实施例中，导电连接件380可与导电连接件360不同。
参照图12，在一些实施例中，将图11中所绘示的整个结构连同载体C1翻转(颠倒)且接着将载体C1从绝缘包封体400及半导体组件10a、20剥离。在一些实施例中，载体C1通过剥离工艺从绝缘包封体400及半导体组件10a、20分离(detached)，其中载体C1被移除，且绝缘包封体400及半导体组件10a、20被暴露出。如图12中所示，绝缘包封体400的表面400a、半导体组件10a的底表面(例如底表面210b)及半导体组件20的底表面20b被暴露出。
在一个实施例中，剥离工艺是激光剥离工艺。在剥离步骤期间，在对载体C1进行剥离之前，采用固持器件HD2来固定图11中所绘示的整个结构，其中导电连接件380由固持器件HD2固持。如图12中所示，例如，固持器件HD2可为粘着条带、载体膜或吸力垫。
参照图13，在一些实施例中，根据图16的步骤S18，依序执行切分(或单体化)工艺以将图12中所绘示的整个结构切割成单独且分开的多个封装结构P1A。在一个实施例中，切分工艺是晶片切分工艺，所述晶片切分工艺包括机械刀片锯切或激光切割。本公开并非仅限于此。至此，封装结构P1A得以制造完成。另外，衬底310与穿孔320一起被认为是中介体(interposer)。
参照图13及图14A，在一些实施例中，出于例示目的示出封装结构P1A中所包括的一个半导体组件10a及两个半导体组件20，然而本公开并非仅限于此。基于需要及设计布局，半导体组件10a的数目及半导体组件20的数目可独立地为一个或多于一个。如图13及图14A中所示，在被包封在绝缘包封体400中的每一半导体组件10a中，从半导体管芯100产生的热量能够通过热耦合到半导体管芯100的散热元件HDE而容易地发散到外部环境，从而有助于在封装结构P1A内保持较低温度。也就是说，基于封装结构P1A中所包括的每一半导体组件10a的散热元件HDE，可通过对散热元件HDE的材料进行调节来控制半导体组件10a的散热效率，从而确保封装结构P1A的可靠性。换句话说，由于散热元件HDE的存在，可确保封装结构P1A的整体热特性(例如散热、耐热性)。
另外，对于图14A中所示的封装结构P1A，由于图16的制造方法，散热元件HDE的侧壁(例如，基底层210的侧壁及粘着层220的侧壁)与位于散热元件HDE之下的半导体管芯100的侧壁对齐。也就是说，在图14A中所示的半导体组件10a中，散热元件HDE的侧壁与半导体管芯100的侧壁实质上彼此共面。
另一方面，在替代实施例中，可从散热元件HDE省略粘着层220，参见图14B中所绘示的封装结构P1B。图14B中所绘示的封装结构P1B与图14A中所绘示的封装结构P1A相似，不同之处在于，封装结构P1B包括半导体组件10b而不是半导体组件10a，其中半导体组件10b包括具有仅基底层210的散热元件。也就是说，在图14B中所示的半导体组件10b中，散热元件HDE的侧壁(例如，基底层210的侧壁)与位于散热元件HDE之下的半导体管芯100的侧壁对齐且实质上共面。
参照图15，在一些实施例中，根据图16的步骤S19，通过导电连接件380将封装结构P1A接合在衬底500上以形成(堆叠的)封装结构P2A。衬底500可由例如硅、锗、金刚石等半导体材料制成。在一些实施例中，也可使用化合物材料，例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些材料的组合等。在一些实施例中，衬底500可为SOI衬底，其中SOI衬底可包括半导体材料(例如外延硅、锗、硅锗、SOI、绝缘体上有硅锗(silicon germanium on insulator，SGOI)或其组合)层。在替代实施例中，衬底500可基于绝缘芯(insulating core)，例如玻璃纤维增强树脂芯(fiberglass reinforced resincore)。一种示例性芯材料(core material)是玻璃纤维树脂，例如阻燃剂级4(flameretardant class 4，FR4)。芯材料的替代物包括双马来酰亚胺三嗪(bismaleimidetriazine，BT)树脂，或者作为另外一种选择，其他印刷电路板(printed circuit board，PCB)材料或膜。在再一替代实施例中，衬底500可为构成膜(build-up film)，例如味之素构成膜(Ajinomoto build-up film，ABF)或其他合适的叠层。
在一个实施例中，衬底500可包括可用于产生针对半导体封装设计的结构及功能要求的有源器件和/或无源器件(未示出)，例如晶体管、电容器、电阻器、其组合等。有源器件和/或无源器件可使用任何合适的方法形成。然而，本公开并非仅限于此；在替代实施例中，衬底500可实质上不包含有源器件和/或无源器件。
在一些实施例中，衬底500包括彼此内连的多个金属化层530及多个通孔(未示出)以及连接到金属化层530及通孔的多个接合垫510、520。金属化层530与通孔一起形成为衬底500提供布线的功能电路系统。嵌置在衬底500中的金属化层530及通孔可由交替的介电(例如低介电常数介电材料)层与导电材料(例如铜)层和内连导电材料层的通孔形成且可通过任何合适的工艺(例如沉积、镶嵌、双镶嵌等)形成。接合垫510、520是用于为衬底500提供与外部组件的电连接。在一些实施例中，接合垫510、520通过金属化层530及通孔彼此电连接。如图15中所示，例如，封装结构P1A的导电连接件380分别连接到衬底500的接合垫510。如图15中所示，在一些实施例中，通过接合垫510及导电连接件380，封装结构P1A电连接到衬底500。
在一些实施例中，可视需要在衬底500的底表面上设置多个导电元件560，如图15中所示。在一些实施例中，可使用导电元件560将衬底500实体地连接到及电连接到其他器件、封装、连接组件等。在本公开中，导电元件560被称为衬底500的导电端子以提供与外部组件的实体连接和/或电连接。如图15中所示，导电元件560及封装结构P1A分别位于衬底500的两个相对的侧上，其中导电元件560中的一些导电元件560通过接合垫510、520及导电连接件380电连接到封装结构P1A。
在一些实施例中，可视需要将一个或多个表面器件540、550连接到衬底500。表面器件540、550可例如用于向封装结构P2A提供附加功能或编程。在实施例中，表面器件540、550可包括期望连接到封装结构P2A且与封装结构P2A接合利用的表面安装器件(surfacemount device，SMD)或集成无源器件(integrated passive device，IPD)，所述集成无源器件包括无源器件，例如电阻器、电感器、电容器、跳线器(jumper)、这些器件的组合等。
举例来说，如图15中所示，表面器件540被放置在其中设置有封装结构P1A的衬底500的表面上，且表面器件550被放置在其中设置有导电元件560的衬底500的表面上。表面器件540的数目及表面器件550的数目并非仅限于所述实施例，且可基于需要及设计布局来选择。本公开并非仅限于此。在一个实施例中，仅表面器件540形成在衬底500上，其中表面器件540的数目可为一个或多于一个。在替代实施例中，仅表面器件550形成在衬底500上，其中表面器件550的数目可为一个或多于一个。如图15中所示，表面器件540、550例如通过接合垫510、520、金属化层530及通孔、以及导电连接件380电连接到封装结构P1A。
在一些实施例中，在衬底500上形成底部填充胶UF2。如图15中所示，例如，底部填充胶UF2填充封装结构P1A与衬底500之间的间隙，且包绕导电连接件380的侧壁。底部填充胶UF2的材料及形成可与图6中所阐述的底部填充胶UF1的材料及形成相同或相似，且因此为了简洁性起见本文中不再重复。
至此，封装结构P2A得以制造完成。另外，衬底500被认为是电路结构(例如，嵌置有电路系统结构的有机衬底，例如印刷电路板(PCB))。然而，本公开并非仅限于此；在替代实施例中，图15中所绘示的封装结构P2A中所包括的封装结构P1A可用图14B中所绘示的封装结构P1B代替。
参照图17，在一些实施例中，提供散热盖600且将散热盖600接合到封装结构P2A的衬底500以形成封装结构P3A。在一些实施例中，在封装结构P3A中，除了散热的功能之外，散热盖600可向封装结构P2A中所包括的封装结构P1A提供实体保护。散热盖600可具有高导热率(例如，大于或处于约200W/m·K到约400W/m·K之间)，且可使用金属、金属合金等形成。在一些实施例中，使用例如粘着剂等接合元件620将散热盖600贴合到衬底500，以使得封装结构P1A布置在由散热盖600及衬底500限定的内腔中。然而，本公开并非仅限于此；在替代实施例中，图17所绘示的封装结构P3A中所包括的封装结构P1A可用图14B中所绘示的封装结构P1B代替。
在一些实施例中，在封装结构P1A与散热盖600之间施加热界面材料(thermalinterface material)610，其中热界面材料610热耦合到封装结构P1A的散热元件HDE，这进一步有助于将热量从封装结构P1A发散到散热盖600，从而有助于在封装结构P3A内保持较低温度。热界面材料610可包括任何合适的导热材料，例如，具有大于或可处于约3W/m·K到约10W/m·K之间约3W/m·K之间的良好导热率的聚合物。
图18到图19是根据本公开一些实施例的封装结构的制造方法中的各个阶段的示意性剖面图。图20是示出根据本公开一些实施例的制造封装结构的方法的流程图。图21A及图21B是根据本公开一些实施例的封装结构的示意性剖面图。图22是根据本公开一些实施例的封装结构的示意性剖面图。图23是根据本公开一些实施例的封装结构的示意性剖面图。在一些实施例中，图1到图6中所阐述的工艺可用图18到图19中所阐述的工艺取代。与上述元件相似或实质上相同的元件将使用相同的参考编号，且相同元件的某些细节或说明(例如，形成及材料)及其关系(例如，相对定位配置及电连接)在本文中将不再重复。
参照图18，在一些实施例中，根据图20的步骤S20，提供至少一个半导体管芯100及至少一个半导体组件20且将所述至少一个半导体管芯100及所述至少一个半导体组件20接合到衬底310(其中嵌置有多个穿孔320且在其上方设置有重布线路结构340及多个导电连接件360)。如图18中所示，例如，半导体管芯100通过实体地连接导通孔140与导电连接件360而接合到衬底310，且半导体组件20通过实体地连接导通孔22与导电连接件360而接合到衬底310。在一些实施例中，施加底部填充胶UF1来填充重布线路结构340与半导体管芯100之间的间隙以及重布线路结构340与半导体组件20之间的间隙，从而进一步增强重布线路结构340与半导体管芯100之间的接合强度以及重布线路结构340与半导体组件20之间的接合强度。在图1到图4中阐述了半导体管芯100的细节，在图6中阐述了半导体组件20的细节、衬底310的细节及底部填充胶UF1的细节，且因此本文中不再重复。如图18中所示，例如，当沿着堆叠方向Z测量时，第一半导体管芯100的厚度小于第二半导体组件20的厚度。
参照图19，在一些实施例中，根据图20的步骤S21，提供散热元件HDE且将散热元件HDE接合到半导体管芯100中的相应的一个半导体管芯100来形成半导体组件10c。如图19所示，例如，当沿着堆叠方向Z测量时，半导体组件10c的厚度大于第二半导体组件20的厚度。然而，本公开并非仅限于此；在替代实施例中，半导体组件10c的厚度实质上等于第二半导体组件20的厚度。在一些实施例中，对于图19中所示的每一半导体组件10c，散热元件HDE连接到位于其之下的半导体管芯100，且散热元件HDE与位于其之下的半导体管芯100彼此热耦合。如图19中所示，散热元件HDE包括基底层210及设置在基底层210上的粘着层220，其中粘着层220夹置在散热元件HDE的基底层210与半导体管芯100之间。然后，对图19中所绘示的结构执行如上方先前在图7到图13中所阐述的制造工艺以获得图21A中所绘示的封装结构P1C，先前所阐述的制造工艺也在图20中的制造方法的步骤S22到步骤S27中示出。由于散热元件HDE，从半导体管芯100产生的热量能够通过散热元件HDE而容易地发散到外部环境，从而有助于在封装结构P1C内保持较低温度。
也就是说，基于封装结构P1C中所包括的每一半导体组件10c的散热元件HDE，可通过对散热元件HDE的材料进行调节来控制半导体组件10c的散热效率，从而确保封装结构P1C的可靠性。换句话说，由于散热元件HDE的存在，可确保封装结构P1C的整体热特性(例如，散热、耐热性)。
在一些实施例中，由于图20的制造方法，对于图21A中绘示的每一半导体组件10c，散热元件HDE的侧壁(例如，基底层210的侧壁及粘着层220的侧壁)可不与位于散热元件HDE之下的半导体管芯100的侧壁对齐，而基底层210的侧壁也可不与粘着层220的侧壁对齐。也就是说，在图21A中，例如，在散热元件HDE内，基底层210的侧壁与粘着层220的侧壁之间存在偏移D1；且在半导体组件10c内，粘着层220的侧壁与半导体管芯100的侧壁之间存在偏移D2。在一些实施例中，偏移D1与偏移D2独立地介于从5μm到5000μm的范围内。
然而，本公开并非仅限于此。在一个实施例中，散热元件HDE的侧壁(例如，基底层210的侧壁及粘着层220的侧壁)可不与位于散热元件HDE之下的半导体管芯100的侧壁对齐，而基底层210的侧壁可与粘着层220的侧壁对齐。或者，在另一实施例中，散热元件HDE的侧壁可与位于散热元件HDE之下的半导体管芯100的侧壁局部地对齐(例如，基底层210的侧壁及粘着层220的侧壁中的一者可与位于其之下的半导体管芯100的侧壁局部地对齐)，而基底层210的侧壁可不与粘着层220的侧壁对齐。或者，在再一实施例中，与半导体组件10a相同，散热元件HDE的侧壁(例如，基底层210的侧壁及粘着层220的侧壁)可与位于散热元件HDE之下的半导体管芯100的侧壁对齐，而基底层210的侧壁可与粘着层220的侧壁对齐。
另一方面，在封装结构P1C的替代实施例中，可从散热元件HDE省略粘着层220，参见图21B中所绘示的封装结构P1D。在一些实施例中，封装结构P1D包括半导体组件10d而不是半导体组件10c，其中封装结构P1D中的半导体组件10d包括具有仅基底层210的散热元件HDE。在一些实施例中，由于图20的制造方法，对于图21B中所绘示的每一半导体组件10d，散热元件HDE的侧壁(例如，基底层210的侧壁)可不与位于散热元件HDE之下的半导体管芯100的侧壁对齐。也就是说，在图21B中，例如，在半导体组件10d内在基底层210的侧壁与半导体管芯100的侧壁之间存在偏移D3。在一些实施例中，偏移D3介于从5μm到5000μm的范围内。或者，在一个实施例中，与半导体组件10b相同，散热元件HDE的侧壁(例如，基底层210的侧壁)可与位于散热元件HDE之下的半导体管芯100的侧壁对齐。
另外，可对图21A中所绘示的结构执行如上方先前在图15中所阐述的制造工艺以获得图22中所绘示的(堆叠的)封装结构P2C，且可对图22中所绘示的结构执行如上方先前在图17中所阐述的制造工艺以获得图23中所绘示的(堆叠的)封装结构P3C。然而，本公开并非仅限于此；在替代实施例中，图22中所绘示的封装结构P2C中所包括的封装结构P1C或图23中所绘示的封装结构P3C中所包括的封装结构P1C可用图21B中所绘示的封装结构P1D代替。
图24到图33A是根据本公开一些实施例的封装结构的制造方法中的各个阶段的示意性剖面图。图33B是根据本公开一些实施例的封装结构的示意性剖面图。图34是根据本公开一些实施例的封装结构的示意性剖面图。图35是示出根据本公开一些实施例的制造封装结构的方法的流程图。与上述元件相似或实质上相同的元件将使用相同的参考编号，且相同元件的某些细节或说明(例如，形成及材料)及其关系(例如，相对定位配置及电连接)在本文中将不再重复。
参照图24，在一些实施例中，在图18中阐述的工艺(根据图35的步骤S30)之后，在半导体管芯100中的每一者上依序形成虚设元件DE(根据图35的步骤S31)。虚设元件DE可包括由玻璃、聚合物或化合物制成的可移除层，且可通过粘合或任何其他合适的技术形成在半导体管芯100上。本公开并非仅限于此。如图24中所示，例如，当沿着堆叠方向Z测量时，具有相应的一个虚设元件DE的每一半导体管芯的厚度大于第二半导体组件20的厚度。然而，本公开并非仅限于此；在替代实施例中，具有相应的一个虚设元件DE的每一半导体管芯的厚度实质上等于第二半导体组件20的厚度。
参照图25，在一些实施例中，根据图35的步骤S32，在衬底310之上形成绝缘包封体400m。在图7的工艺中已阐述了绝缘包封体400m的形成及材料，且因此本文中不再重复。如图25中所示，例如，上面设置有虚设元件DE的半导体管芯100、半导体组件20及底部填充胶UF1被绝缘包封体400m环绕及覆盖。也就是说，上面设置有虚设元件DE的半导体管芯100、半导体组件20及底部填充胶UF1嵌置在绝缘包封体400m中。换句话说，上面设置有虚设元件DE的半导体管芯100、半导体组件20及底部填充胶UF1不被绝缘包封体400m以可触及的方式显露出且嵌置在绝缘包封体400m中。
参照图25及图26，在一些实施例中，根据图35的步骤S33，将绝缘包封体400m平坦化直到暴露出设置在半导体管芯100上的虚设元件DE的底表面S1及半导体组件20的底表面20b。在将绝缘包封体400m平坦化之后，形成(经平坦化的)绝缘包封体400，且虚设元件DE的底表面S1及半导体组件20的底表面20b被绝缘包封体400的表面400a暴露出。在图8的工艺中已阐述了绝缘包封体400的形成，且因此本文中不再重复。
参照图27，在一些实施例中，在形成绝缘包封体400之后，将图26中所绘示的结构翻转(沿着堆叠方向Z颠倒)，且将绝缘包封体400放置在载体C1上。在图9的工艺中已阐述了载体C1的材料，且因此本文中不再重复。
参照图28，在一些实施例中，根据图35的步骤S34，接着将衬底310平坦化直到暴露出嵌置在衬底310中的穿孔320的底表面320b。在图10的工艺中已阐述了图案化工艺的细节，且因此本文中不再重复。如图28中所示，穿孔320的底表面320b与衬底310的表面310b实质上齐平且共面。也就是说，穿孔320的底表面320b被衬底310以可触及的方式暴露出。
参照图29，在一些实施例中，根据图35的步骤S35，在衬底310上形成多个导电连接件380，其中导电连接件380连接到穿孔320。在图29的工艺中已阐述了导电连接件380的形成及材料，且因此本文中不再重复。在一些实施例中，通过穿孔320、重布线路结构340及导电连接件360，导电连接件380中的一些导电连接件380电连接到半导体管芯100。在一些实施例中，通过穿孔320、重布线路结构340及导电连接件360，导电连接件380中的一些导电连接件380电连接到半导体组件20。在替代实施例中，导电连接件380中的一些导电连接件380可还电连接到嵌置在衬底310中或形成在衬底310的表面310a上的有源器件及无源器件。
参照图30，在一些实施例中，将图29中所绘示的整个结构连同载体C1翻转(颠倒)且放置到固持器件HD2上，且然后将载体C1从绝缘包封体400、虚设元件DE及半导体组件20剥离。在一些实施例中，载体C1通过剥离工艺与绝缘包封体400、虚设元件DE及半导体组件20分离，其中载体C1被移除，且绝缘包封体400、虚设元件DE及半导体组件20被暴露出。如图30中所示，绝缘包封体400的表面400a、虚设元件DE的底表面S1及半导体组件20的底表面20b被暴露出。在图12的工艺中已阐述了剥离工艺的细节及固持器件HD2的材料，且因此本文中不再重复。
参照图31，在一些实施例中，根据图35的步骤S36，依序执行切分(或单体化)工艺以将图30中所绘示的整个结构切割成上面设置有虚设元件DE的单独且分开的多个结构。在一个实施例中，切分工艺是晶片切分工艺，所述晶片切分工艺包括机械刀片锯切或激光切割。本公开并非仅限于此。另外，衬底310与穿孔320一起被认为是中介体。
参照图32，在一些实施例中，根据图35的步骤S37，通过多个导电连接件380将上面设置有虚设元件DE的结构接合在衬底500(包括多个接合垫510、520、彼此内连的多个金属化层530及多个通孔、多个表面器件540、550以及多个导电元件560)上。在图15的工艺中已阐述了接合工艺的细节以及衬底500(包括接合垫510、520、彼此内连的金属化层530及通孔、表面器件540、550以及导电元件560)的形成及材料，且因此本文中不再重复。在一些实施例中，在衬底500上形成底部填充胶UF2。如图32中所示，例如，底部填充胶UF2填充上面设置有虚设元件DE的结构与衬底500之间的间隙，且包绕导电连接件380的侧壁。底部填充胶UF2的材料及形成可与图6中所阐述的底部填充胶UF1的材料及形成相同或相似，且因此为了简洁性起见本文中不再重复。另外，衬底500被认为是电路结构(例如，嵌置有电路系统结构的有机衬底，例如印刷电路板(PCB))。
参照图33A，在一些实施例中，根据图35的步骤S38，移除虚设元件DE，且然后在半导体管芯100上设置散热元件HDE以形成具有封装结构P1E的(堆叠的)封装结构P2E，封装结构P1E包括设置在衬底500上的半导体组件10e。举例来说，虚设元件DE的移除可通过刻蚀、紫外去粘着(UV de-adhesion)或热去粘着来执行，本公开并非仅限于此。在一些实施例中，从图32中所绘示的结构移除虚设元件DE以在半导体管芯100上方形成凹槽R，且接着在凹槽R中设置散热元件HDE以与半导体管芯100及绝缘包封体400实体地接触。换句话说，凹槽R由半导体管芯100及绝缘包封体400限定。在一些实施例中，半导体组件10e包括散热元件HDE及位于散热元件HDE之下的半导体管芯100，其中散热元件HDE与半导体管芯100热耦合。举例来说，如图33A中所示，散热元件HDE包括基底层210及设置在基底层210上的粘着层220，其中粘着层220夹置在半导体组件10e的半导体管芯100与基底层210之间。在图1中已阐述了散热元件HDE中所包括的基底层210的材料及粘着层220的材料，且在图1到图5中已阐述了半导体管芯100的细节，且因此本文中不再重复。如图33A中所示，在被包封在绝缘包封体400中的每一半导体组件10e中，从半导体管芯100产生的热量能够通过散热元件HDE而容易地发散到外部环境，从而有助于在封装结构P1E内保持较低温度。也就是说，基于封装结构P1E中所包括的每一半导体组件10e的散热元件HDE，可通过对散热元件HDE的材料进行调节来控制半导体组件10e的散热效率，从而确保封装结构P1E的可靠性。换句话说，由于散热元件HDE的存在，可确保封装结构P1E的整体热特性(例如，散热、耐热性)。
由于图35的制造方法，在剖面图中，封装结构P2E中的封装结构P1E所包括的半导体组件10e的轮廓可与图14A中所绘示的半导体组件10a或图21A中所绘示的半导体组件10c的轮廓相同。举例来说，如图33A中所示，与半导体组件10a相同，基底层210的侧壁及粘着层220的侧壁与半导体管芯100的侧壁对齐且实质上共面。然而，本公开并非仅限于此。在一些实施例中，与半导体组件10c相同，散热元件HDE的侧壁(例如，基底层210的侧壁及粘着层220的侧壁)可不与位于散热元件HDE之下的半导体管芯100的侧壁对齐，而基底层210的侧壁也可不与粘着层220的侧壁对齐。也就是说，例如，在散热元件HDE内，基底层210的侧壁与粘着层220的侧壁之间可存在介于从5μm到5000μm的范围内的偏移；且在半导体组件10e内，粘着层220的侧壁与半导体管芯100的侧壁之间可存在介于从5μm到5000μm的范围内的另一偏移。在一些实施例中，散热元件HDE的侧壁(例如，基底层210的侧壁及粘着层220的侧壁)可不与位于散热元件HDE之下的半导体管芯100的侧壁对齐，而基底层210的侧壁可与粘着层220的侧壁对齐。或者，在另一实施例中，散热元件HDE的侧壁可与位于散热元件HDE之下的半导体管芯100的侧壁局部地对齐(例如，基底层210的侧壁及粘着层220的侧壁中的一者可与半导体管芯100的侧壁对齐)，而基底层210的侧壁可不与粘着层220的侧壁对齐。
另一方面，在封装结构P1E的替代实施例中，可从散热元件HDE省略粘着层220，参见图33B中所绘示的(堆叠的)封装结构P2F中所包括的封装结构P1F。在一些实施例中，封装结构P1F包括半导体组件10f而不是半导体组件10e，其中封装结构P1F的半导体组件10f包括具有仅基底层210的散热元件HDE。在一些实施例中，由于图35的制造方法，对于图33B中所绘示的每一半导体组件10f，在剖面图中，封装结构P2F的封装结构P1F中包括的半导体组件10f的轮廓可与图14B中所绘示的半导体组件10b或图21B中所绘示的半导体组件10d的轮廓相同。举例来说，如图33B所示，与半导体组件10b相同，基底层210的侧壁可与位于基底层210之下的半导体管芯100的侧壁对齐。然而，本公开并非仅限于此。在一些实施例中，与半导体组件10d相同，基底层210的侧壁可不与位于基底层210之下的半导体管芯100的侧壁对齐。也就是说，例如，在半导体组件10f内在基底层210的侧壁与半导体管芯100的侧壁之间可存在介于从5μm到5000μm的范围内的偏移。
参照图34，在一些实施例中，提供散热盖600以及热界面材料610且将散热盖600以及热界面材料610接合到封装结构P2E的衬底500以形成封装结构P3E。在图17中已阐述了散热盖600及热界面材料610的材料及形成，且因此为了简洁性起见本文中不再重复。在一些实施例中，热界面材料610位于封装结构P1E与散热盖600之间，其中热界面材料610热耦合到封装结构P1E的半导体组件10e中所包括的散热元件HDE，这进一步有助于将热量从封装结构P1E发散到散热盖600，从而有助于在封装结构P3E内保持较低温度。然而，本公开并非仅限于此；在替代实施例中，图34中所绘示的封装结构P3E中所包括的封装结构P2E可用图33B中所绘示的封装结构P2F代替。
图36是根据本公开一些实施例的封装结构的示意性剖面图。图37是示出根据本公开一些实施例的制造封装结构的方法的流程图。图38是示出根据本公开一些实施例的制造封装结构的方法的流程图。图39是示出根据本公开一些实施例的制造封装结构的方法的流程图。图40是根据本公开一些实施例的封装结构的示意性剖面图。与上述元件相似或实质上相同的元件将使用相同的参考编号，且相同元件的某些细节或说明(例如，形成及材料)及其关系(例如，相对定位配置及电连接)在本文中将不再重复。
参照图36，在一些实施例中，封装结构P4A包括半导体组件10a、半导体组件30、绝缘包封体700、重布线路结构800及多个导电端子900。在一些实施例中，半导体组件10a及半导体组件30被包封在绝缘包封体700中，其中半导体组件10a的表面S2及半导体组件30的表面S3被绝缘包封体700的表面700b暴露出。在一些实施例中，重布线路结构800位于绝缘包封体700的表面700a上，其中表面700a沿重布线路结构800与绝缘包封体700的堆叠方向Z与表面700b相对。如图36中所示，例如，重布线路结构800电连接到半导体组件10a及半导体组件30。在本公开中，重布线路结构800向半导体组件10a、30提供布线功能。在一些实施例中，导电端子900位于重布线路结构800上且连接到重布线路结构800，其中重布线路结构800位于绝缘包封体700与导电端子900之间。如图36中所示，导电端子900中的一些导电端子900电连接到半导体组件10a，导电端子900中的一些导电端子900电连接到半导体组件30。
在图1到图5中已阐述了半导体组件10a的形成及材料，且因此本文中不再重复。如图36中所示，半导体组件10a包括第一半导体管芯100及设置在第一半导体管芯100上的散热元件HDE，其中散热元件HDE热耦合到第一半导体管芯100。由于散热元件HDE，从半导体管芯100产生的热量能够通过散热元件HDE而容易地发散到外部环境，从而有助于在封装结构P4A内保持较低温度。也就是说，基于封装结构P4A中所包括的半导体组件10a的散热元件HDE，可通过对散热元件HDE的材料进行调节来控制半导体组件10a的散热效率，从而确保封装结构P4A的可靠性。换句话说，由于散热元件HDE的存在，可确保封装结构P4A的整体热特性(例如散热、耐热性)。然而，本公开并非仅限于此；在替代实施例中，半导体组件10a可用图21A所绘示的半导体组件10c或图33A中所绘示的半导体组件10e来代替；或者，半导体组件10a可由图14B中所绘示的半导体组件10b(参见图40中所示的封装P4B)、图21B中所绘示的半导体组件10d或图33B中所绘示的半导体组件10f代替。
在一些实施例中，半导体组件30包括具有有源表面31a的半导体衬底31、形成在有源表面31a上的内连结构32以及电连接到内连结构32的多个导通孔33。在一些实施例中，半导体衬底31可为硅衬底，所述硅衬底包括形成在其中的有源组件(例如晶体管等)和/或无源组件(例如电阻器、电容器、电感器等)。本公开并非仅限于此。在一个实施例中，半导体衬底31的形成及材料可与半导体衬底110的形成及材料相同；然而，本公开并非仅限于此。
在一些实施例中，内连结构32包括交替地堆叠的一个或多个层间介电层32a与一个或多个图案化导电层32b。在某些实施例中，图案化导电层32b夹置在层间介电层32a之间，其中图案化导电层32b的最顶层的顶表面的部分被层间介电层32a的最顶层暴露出且实体地连接到导通孔33，且图案化导电层32b的最底层的一些部分被层间介电层32a的最底层暴露出且电连接到半导体衬底31中所形成的有源组件和/或无源组件(未示出)。如图36中所示，层间介电层32a的最底层位于半导体衬底31的有源表面31a上，且层间介电层32a的最顶层至少局部地与导通孔33接触。层间介电层32a的数目及图案化导电层32b的数目可基于需要来选择，且在本公开中不受限制。层间介电层32a的数目及图案化导电层32b的数目可小于或大于图36中所绘示的数目，且可基于需要和/或设计布局来指定；本公开并非仅限于此。在一个实施例中，层间介电层32a的形成及材料可与图1中所阐述的层间介电层122的形成及材料相同或相似，且图案化导电层32b的形成及材料可与图1中所阐述的图案化导电层124的形成及材料相同或相似，且因此本文中不再重复。在本公开中，导通孔33用作半导体组件30的导电端子以电连接到外部组件。在一些实施例中，尽管出于例示目的，图36中呈现出仅四个导通孔33，但应理解，导通孔33的数目可基于需要及设计布局来选择或指定；本公开并非仅限于此。在一个实施例中，导通孔33的形成及材料可与图1中所阐述的导通孔140的形成及材料相同，且因此本文中不再重复。如图36中所示，导通孔33实体地连接到及电连接到内连电路结构32。在一些实施例中，半导体组件10a的导通孔140的表面及半导体组件30的导通孔33的表面与绝缘包封体700的表面700a实质上齐平且实质上共面，其中半导体组件10a的导通孔140的表面及半导体组件30的导通孔33的表面被绝缘包封体700暴露出且与重布线路结构800接触。
在一些实施例中，本文中所阐述的半导体组件30可被称为半导体芯片或集成电路(IC)。在一个实施例中，半导体组件30可与半导体管芯100相同或相似。在替代实施例中，半导体组件30可与半导体管芯100不同。在再一个实施例中，半导体组件30可与半导体组件20相同或相似。在再一替代实施例中，半导体组件30可与半导体组件20不同。
在一些实施例中，如图36中所示，重布线路结构800包括交替地堆叠的多个介电层802与多个金属化层804，金属化层804夹置在介电层802之间，其中金属化层804的最顶层的顶表面至少局部地被形成在介电层802的最顶层中的多个开口(未标记)暴露出以连接到稍后形成的组件以进行电连接，且金属化层804的最低层的底表面至少局部地被形成在介电层802的最低层中的多个开口(未标记)暴露出且通过导通孔140电连接到半导体组件10a，且通过导通孔33电连接到半导体组件30。金属化层804的数目及介电层802的数目在本公开中不受限制，且可基于需要和/或设计布局来指定。也就是说，被绝缘包封体700暴露出的半导体组件10a的导通孔140的表面及半导体组件30的导通孔33的表面与被介电层802的最底层暴露出的金属化层804的最底层实体地接触。在一些实施例中，被绝缘包封体700暴露出的半导体组件10a的导通孔140的表面及半导体组件30的导通孔33的表面被介电层802的最底层局部地覆盖。
继续图36，在一些实施例中，封装结构P4A可还包括多个球下金属(under-ballmetallurgy，UBM)图案u1，其中UBM图案u1可设置在金属化层804的最顶层的被暴露的顶表面上以与多个导电元件(例如，导电球或导电凸块，例如导电端子900)电连接。如图36中所示，例如，UBM图案u1形成在重布线路结构800上且电连接到重布线路结构800。举例来说，UBM图案u1的材料可包括铜、镍、钛、钨或其合金等，且可通过电镀工艺形成。UBM图案u1的数目在本公开中不受限制，且与金属化层804的最顶层的顶表面的被介电层802的最顶层暴露出的部分的数目对应。在一些实施例中，导电端子900通过UBM图案u1电连接到重布线路结构800。在一些实施例中，导电端子900可通过植球工艺(ball placement process)或回焊工艺(reflow process)设置在UBM图案u1上。在一些实施例中，导电端子900是例如焊料球或球栅阵列(ball grid array，BGA)球。导电端子900的数目并不仅限于本公开，且可基于UBM图案u1的数目来指定及选择。
在一个实施例中，可通过图37的方法来制造封装结构P4A。应理解，在图37的方法的所示动作之前、期间及之后可发生附加处理(additional treatment)以完成封装结构P4A的形成。图37的方法包括至少步骤S40到步骤S46。举例来说，图37中所示的方法从步骤S40开始，步骤S40提供包括多个第一半导体管芯的晶片；步骤S41，将包括所述多个第一半导体管芯的晶片接合到包括多个散热元件的晶片；步骤S42，对接合结构进行切分以形成各自具有一个第一半导体管芯及设置在所述一个第一半导体管芯上的一个相应的散热元件的多个单独且分开的第一半导体组件，其中第一半导体管芯热耦合到相应的一个散热元件；步骤S43，将所述多个第一半导体组件中的至少一者以及至少一个第二半导体组件包封在绝缘包封体中；步骤S44，将绝缘包封体平坦化，以使绝缘包封体的第一表面暴露出第一半导体组件中所包括的散热元件；步骤S45，在绝缘包封体的第二表面上形成电连接到第一半导体组件及第二半导体组件的重布线路结构，其中第一表面与第二表面相对；以及步骤S46，在重布线路结构上设置多个导电端子，导电端子通过重布线路结构电连接到第一半导体组件及第二半导体组件，其中重布线路结构夹置在导电端子与绝缘包封体之间。然而，本公开并非仅限于此。
在替代实施例中，可通过图38的方法来制造封装结构P4A。应理解，在图38的方法的所示动作之前、期间及之后可发生附加处理以完成封装结构P4A的形成。图38的方法包括至少步骤S50到步骤S55。举例来说，图38中所示的方法从步骤S50开始，步骤S50提供至少一个第一半导体管芯及至少一个第二半导体组件，其中第一半导体管芯的厚度小于第二半导体组件的厚度；步骤S51，在第一半导体管芯上设置散热元件以形成第一半导体组件，其中散热元件实体地连接到第一半导体管芯，且散热元件热耦合到第一半导体管芯；步骤S52，将第一半导体组件及第二半导体组件包封在绝缘包封体中；步骤S53，将绝缘包封体平坦化，以使绝缘包封体的第一表面暴露出第一半导体组件中所包括的散热元件；步骤S54，在绝缘包封体的第二表面上形成电连接到第一半导体组件及第二半导体组件的重布线路结构，其中第一表面与第二表面相对；以及步骤S55，在重布线路结构上设置多个导电端子，导电端子通过重布线路结构电连接到第一半导体组件及第二半导体组件，其中重布线路结构夹置在导电端子与绝缘包封体之间。然而，本公开并非仅限于此。
在一些替代实施例中，可通过图39的方法来制造封装结构P4A。应理解，在图39的方法的所示动作之前、期间及之后可发生附加处理以完成封装结构P4A的形成。图39的方法包括至少步骤S60到步骤S66。举例来说，图39中所示的方法从步骤S60开始，步骤S60提供至少一个第一半导体管芯及至少一个第二半导体组件，其中第一半导体管芯的厚度小于第二半导体组件的厚度；步骤S61，在第一半导体管芯上设置虚设元件；步骤S62，将上面设置有虚设元件的第一半导体管芯及第二半导体组件包封在绝缘包封体中；步骤S63，将绝缘包封体平坦化，以使绝缘包封体的第一表面暴露出虚设元件；步骤S64，在绝缘包封体的第二表面上形成电连接到第一半导体管芯及第二半导体组件的重布线路结构，其中第一表面与第二表面相对；步骤S65，在重布线路结构上设置多个导电端子，导电端子通过重布线路结构电连接到第一半导体管芯及第二半导体组件，其中重布线路结构夹置在导电端子与绝缘包封体之间；以及步骤S66，从第一半导体管芯移除虚设元件且在第一半导体管芯上直接设置散热元件以形成第一半导体组件，其中散热元件实体地连接到第一半导体管芯，且散热元件热耦合到第一半导体管芯。
在一些实施例中，图36中所示的半导体组件10a的数目及半导体组件30的数目和/或图40中所示的半导体组件10b的数目及半导体组件30的数目并非仅限于此，且可为一个或多于一个。另外，以上半导体组件30也可用图6中所阐述的半导体组件20代替。图41是根据本公开一些实施例的封装结构的示意性剖面图。图42是根据本公开一些实施例的封装结构的示意性剖面图。图43是根据本公开一些实施例的封装结构的示意性剖面图。图44是根据本公开一些实施例的封装结构的示意性剖面图。与上述元件相似或实质上相同的元件将使用相同的参考编号，且相同元件的某些细节或说明(例如，形成及材料)及其关系(例如，相对定位配置及电连接)在本文中将不再重复。
一起参照图36与图41，图36中所绘示的封装结构P4A与图41中所绘示的封装结构P5A相似；不同之处在于，对于图41中所绘示的半导体封装P5A，以两个半导体组件20代替一个半导体组件30。一起参照图40与图42，图40中所绘示的封装结构P4B与图42中所绘示的封装结构P5B相似；不同之处在于，对于图42中所绘示的半导体封装P5B，以两个半导体组件20代替一个半导体组件30。
一起参照图36与图43，图36中所绘示的封装结构P4A与图43中所绘示的封装结构P6A相似；不同之处在于，对于图43中所绘示的半导体封装P6A，以两个半导体组件10a代替一个半导体组件10a，且以一个半导体组件20代替一个半导体组件30。一起参照图40与图44，图40中所绘示的封装结构P4B与图44中所绘示的封装结构P6B相似；不同之处在于，对于图44中所绘示的半导体封装P6B，以两个半导体组件10b代替一个半导体组件10b，且以一个半导体组件20代替一个半导体组件30。
然而，本公开并非仅限于此。在替代实施例中，可以图21A中所绘示的半导体组件10c或图33A中所绘示的半导体组件10e独立地代替图41及图43中所绘示的半导体组件10a，且图42及图44中所绘示的半导体组件10b可独立地被图21B中所绘示的半导体组件10d或图33B中所绘示的半导体组件10f代替。
图45是根据本公开一些实施例的封装结构的示意性剖面图。图46是示出根据本公开一些实施例的制造封装结构的方法的流程图。图47是示出根据本公开一些实施例的制造封装结构的方法的流程图。图48是示出根据本公开一些实施例的制造封装结构的方法的流程图。图49是根据本公开一些实施例的封装结构的示意性剖面图。一起参照图36与图45，图36中所绘示的封装结构P4A与图45中所绘示的封装结构P7A相似；以使得与上述元件相似或实质上相同的元件将使用相同的参考编号，且相同元件的某些细节或说明(例如，形成及材料)及其关系(例如，相对定位配置及电连接)在本文中将不再重复。
一起参照图36与图45，不同之处在于，对于图45中所绘示的封装结构P7A，还包括附加元件(例如，介电层PM1、多个导通孔CP1、多个导通孔CP2、绝缘包封体702及桥接元件(bridge element)BE)，其中桥接元件BE被包封在绝缘包封体702中且设置在重布线路结构800与绝缘包封体700之间，且桥接元件BE通过导通孔CP2电连接到半导体组件10a及半导体组件30。也就是说，例如，半导体组件10a与半导体组件30通过桥接元件BE电连通。
在一些实施例中，如图45中所示，介电层PM1形成在绝缘包封体700上且实体地接触绝缘包封体700，其中介电层PM1具有多个开口(未标记)，所述多个开口暴露出半导体组件30的导通孔33的表面及半导体组件10a的导通孔140的表面。介电层PM1的材料可包括可使用光刻和/或刻蚀工艺图案化的聚酰亚胺、PBO、苯并环丁烯(benzocyclobutene，BCB)、氮化物(例如氮化硅)、氧化物(例如氧化硅)、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、硼掺杂磷硅酸盐玻璃(boron-dopedphosphosilicate glass，BPSG)、其组合等。在一些实施例中，导通孔CP1及导通孔CP2形成在介电层PM1上且通过介电层PM1的开口连接到导通孔33及导通孔140。导通孔CP1及导通孔CP2的材料及形成与图4中所阐述的导通孔140的材料及形成相同或相似，因此本文中可不再重复。
在一些实施例中，桥接元件BE设置在导通孔CP2上且被导通孔CP1环绕。在一些实施例中，当在堆叠方向Z上测量时，桥接元件BE的高度小于导通孔CP1的高度。如图45中所示，桥接元件BE在重布线路结构800与绝缘包封体700的堆叠方向Z上与半导体组件10a及半导体组件30交叠，且在重布线路结构800上的垂直投影中从半导体组件10a延伸到半导体组件30(或者说，从半导体组件30延伸到半导体组件10a)。由于所述配置，半导体组件10a与半导体组件30之间的短的电性路径(short electrical path)得以实现，从而降低了其信号损耗。
在一些实施例中，导通孔CP1、导通孔CP2及桥接元件BE被包封在绝缘包封体702中，且被导通孔CP1及导通孔CP2暴露出的介电层PM1被绝缘包封体702覆盖。如图45中所示，桥接元件BE的表面、导通孔CP1的表面及绝缘包封体142的表面702a实质上彼此齐平且实质上彼此共面。在一些实施例中，重布线路结构800位于桥接元件BE、导通孔CP1及绝缘包封体702(在表面702a处)上，且实体地连接到以及电连接到导通孔CP1。绝缘包封体702的材料及形成与图36中所阐述的绝缘包封体700的材料及形成相同或相似，因此本文中可不再重复。也就是说，例如，重布线路结构800通过导通孔CP1、导通孔33及导通孔140电连接到半导体组件10a及半导体组件30。
在一些实施例中，桥接元件BE包括衬底41、设置在衬底41上的重布线路结构42(其中布置有介电结构42a及一个或多个金属化层42b)以及嵌置到衬底41且电连接到重布线路结构42的多个穿孔43。衬底41的形成及材料与衬底310的形成及材料相同或相似，重布线路结构42的形成及材料与重布线路结构340的形成及材料相同或相似，且穿孔43的形成及材料与穿孔320的形成及材料相同或相似，且因此为了简洁性起见本文中不再重复。
如图45中所示，桥接元件BE通过导通孔33、140、CP2及重布线路结构42电连接到半导体组件10a及半导体组件30。换句话说，半导体组件10a与半导体组件30通过桥接元件BE彼此电连通。在一些实施例中，如图45中所示，桥接元件BE的穿孔43实体地连接到以及电连接到重布线路结构800的金属化层804的最底层。也就是说，例如，重布线路结构800可还通过桥接元件BE、导通孔CP2、导通孔33及导通孔140电连接到半导体组件10a及半导体组件30。在一些实施例中，导电元件900中的一些导电元件900通过UBM图案u1中的一些UBM图案u1、重布线路结构800及导通孔CP1中的一些导通孔CP1或者通过UBM图案u1中的一些UBM图案u1、重布线路结构800、桥接元件BE及导通孔CP2中的一些导通孔CP2电连接到半导体组件10a，且导电元件900中的一些导电元件900通过UBM图案u1中的一些UBM图案u1、重布线路结构800及导通孔CP1中的一些导通孔CP1或者通过UBM图案u1中的一些UBM图案u1、重布线路结构800、桥接元件BE及导通孔CP2中的一些导通孔CP2电连接到半导体组件30。
在一个实施例中，可通过图46的方法来制造封装结构P7A。应理解，在图46的方法的所示动作之前、期间及之后可发生附加处理以完成封装结构P7A的形成。图46的方法包括至少步骤S70到步骤S79。举例来说，图46中所示的方法从步骤S70开始，步骤S70提供包括多个第一半导体管芯的晶片；步骤S71，将包括所述多个第一半导体管芯的晶片接合到包括多个散热元件的晶片；步骤S72，对接合结构进行切分以形成各自具有一个第一半导体管芯及设置在所述一个第一半导体管芯上的一个相应的散热元件的多个单独且分开的第一半导体组件，其中第一半导体管芯热耦合到相应的一个散热元件；步骤S73，将所述多个第一半导体组件中的至少一者及至少一个第二半导体组件包封在绝缘包封体的第一部分中；步骤S74，将绝缘包封体的第一部分平坦化，以使绝缘包封体的第一部分的第一表面暴露出第一半导体组件中所包括的散热元件；步骤S75，在第一半导体组件及第二半导体组件上设置多个第一导通孔及多个第二导通孔；步骤S76，在第一半导体组件及第二半导体组件之上且在第二导通孔上方设置连接元件(例如图45中所绘示的桥接元件BE)以电连接第一半导体组件与第二半导体组件，其中连接元件实体地连接到以及电连接到与第一半导体组件及第二半导体组件连接的第二导通孔，以使得第一半导体组件与第二半导体组件通过连接元件及第二导通孔彼此电连通；步骤S77，将第一导通孔、第二导通孔及连接元件包封在绝缘包封体的第二部分中，其中第一导通孔的表面及连接元件的表面与绝缘包封体的第二部分的第二表面实质上齐平且实质上共面；步骤S78，在绝缘包封体的第二部分的第二表面上形成重布线路结构，以通过第一导通孔和/或连接到第二导通孔的连接元件电连接到第一半导体组件及第二半导体组件，其中绝缘包封体的第二部分夹置在重布线路结构与绝缘包封体的第一部分之间；以及步骤S79，在重布线路结构上设置多个导电端子，导电端子通过重布线路结构电连接到第一半导体组件及第二半导体组件，其中重布线路结构夹置在导电端子与绝缘包封体的第二部分之间。然而，本公开并非仅限于此。
在替代实施例中，可通过图47的方法来制造封装结构P7A。应理解，在图47的方法的所示动作之前、期间及之后可发生附加处理以完成封装结构P7A的形成。图47的方法包括至少步骤S80到步骤S88。举例来说，图47中所示的方法从步骤S80开始，步骤S80提供至少一个第一半导体管芯及至少一个第二半导体组件，其中第一半导体管芯的厚度小于第二半导体组件的厚度；步骤S81，在第一半导体管芯上设置散热元件以形成第一半导体组件，其中散热元件实体地连接到第一半导体管芯，且散热元件热耦合到第一半导体管芯；步骤S82，将第一半导体组件及第二半导体组件包封在绝缘包封体的第一部分中；步骤S83，将绝缘包封体的第一部分平坦化，以使绝缘包封体的第一部分的第一表面暴露出第一半导体组件中所包括的散热元件；步骤S84，在第一半导体组件及第二半导体组件上设置多个第一导通孔及多个第二导通孔；步骤S85，在第一半导体组件及第二半导体组件之上且在第二导通孔上方设置连接元件(例如图45中所绘示的桥接元件BE)以电连接第一半导体组件与第二半导体组件，其中连接元件实体地连接到以及电连接到与第一半导体组件及第二半导体组件连接的第二导通孔，以使得第一半导体组件与第二半导体组件通过连接元件及第二导通孔彼此电连通；步骤S86，将第一导通孔、第二导通孔及连接元件包封在绝缘包封体的第二部分中，其中第一导通孔的表面及连接元件的表面与绝缘包封体的第二部分的第二表面实质上齐平且实质上共面；步骤S87，在绝缘包封体的第二部分的第二表面上形成重布线路结构，以通过第一导通孔和/或连接到第二导通孔的连接元件电连接到第一半导体组件及第二半导体组件，其中绝缘包封体的第二部分夹置在重布线路结构与绝缘包封体的第一部分之间；以及步骤S88，在重布线路结构上设置多个导电端子，导电端子通过重布线路结构电连接到第一半导体组件及第二半导体组件，其中重布线路结构夹置在导电端子与绝缘包封体的第二部分之间。然而，本公开并非仅限于此。
在一些替代实施例中，可通过图48的方法来制造封装结构P7A。应理解，在图48的方法的所示动作之前、期间及之后可发生附加处理以完成封装结构P7A的形成。图48的方法包括至少步骤S90到步骤S99。举例来说，图48所示的方法从步骤S90开始，步骤S90提供至少一个第一半导体管芯及至少一个第二半导体组件，其中第一半导体管芯的厚度小于第二半导体组件的厚度；步骤S91，在第一半导体管芯上设置虚设元件；步骤S92，将上面设置有虚设元件的第一半导体管芯及第二半导体组件包封在绝缘包封体的第一部分中；步骤S93，将绝缘包封体的第一部分平坦化，以使绝缘包封体的第一部分的第一表面暴露出设置在第一半导体管芯上的虚设元件；步骤S94，在第一半导体管芯及第二半导体组件上设置多个第一导通孔及多个第二导通孔；步骤S95，在第一半导体管芯及第二半导体组件之上且在第二导通孔上方设置连接元件(例如图45中所绘示的桥接元件BE)以电连接第一半导体管芯与第二半导体组件，其中连接元件实体地连接到以及电连接到与第一半导体管芯及第二半导体组件连接的第二导通孔，以使得第一半导体管芯与第二半导体组件通过连接元件及第二导通孔彼此电连通；步骤S96，通过绝缘包封体的第二部分包封第一导通孔、第二导通孔及连接元件，其中第一导通孔的表面及连接元件的表面与绝缘包封体的第二部分的第二表面实质上齐平且实质上共面；步骤S97，在绝缘包封体的第二部分的第二表面上形成重布线路结构，以通过第一导通孔和/或连接到第二导通孔的连接元件电连接到第一半导体管芯及第二半导体组件，其中绝缘包封体的第二部分夹置在重布线路结构与绝缘包封体的第一部分之间；步骤S98，在重布线路结构上设置多个导电端子，导电端子通过重布线路结构电连接到第一半导体管芯及第二半导体组件，其中重布线路结构夹置在导电端子与绝缘包封体的第二部分之间；以及步骤S99，从第一半导体管芯移除虚设元件且在第一半导体管芯上直接设置散热元件以形成第一半导体组件，其中散热元件实体地连接到第一半导体管芯，且散热元件热耦合到第一半导体管芯。
然而，本公开并非仅限于此；在一些替代实施例中，可用图21A中所绘示的半导体组件10c或图33A中所绘示的半导体组件10e代替封装结构P7A的半导体组件10a；或者，封装结构P7A的半导体组件10a可被图14B中所绘示的半导体组件10b(参见图49中所示的封装结构P7B)、图21B中所绘示的半导体组件10d或图33B中所绘示的半导体组件10f代替。
在一些替代实施例中，除了图36、图40到图45、及图49中的导电端子900之外，可通过替代UBM图案u1的接合垫(未示出)在重布线路结构800上设置附加半导体元件(未示出)。附加半导体元件可包括无源组件或有源组件。附加半导体元件的数目在本公开中不受限制，且可基于需要及设计布局来指定。在一些实施例中，封装结构P4A到封装结构P7B可进一步安装有附加封装、芯片/管芯、其他电子器件或合适的衬底(例如有机衬底)，以形成堆叠的封装结构，本公开并非仅限于此。
根据一些实施例，一种封装结构包括电路元件、第一半导体管芯、第二半导体管芯、散热元件以及绝缘包封体。所述第一半导体管芯及所述第二半导体管芯位于所述电路元件上。所述散热元件连接到所述第一半导体管芯，且所述第一半导体管芯位于所述电路元件与所述散热元件之间，其中所述第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述第二半导体管芯的第二厚度。所述绝缘包封体包封所述第一半导体管芯、所述第二半导体管芯及所述散热元件，其中所述散热元件的表面与所述绝缘包封体的表面实质上齐平。
在一些实施例中，在所述封装结构中，其中在剖面图中，所述散热元件的侧壁与所述第一半导体管芯的侧壁实质上对齐。在一些实施例中，在所述封装结构中，其中所述散热元件包括粘着基底层，且所述粘着基底层的导热系数大于所述绝缘包封体的导热系数。在一些实施例中，在所述封装结构中，其中在剖面图中，在所述散热元件的侧壁与所述第一半导体管芯的侧壁之间存在偏移，且所述偏移介于从5μm到5000μm的范围内。在一些实施例中，在所述封装结构中，其中所述散热元件包括基底层及位于所述基底层与所述第一半导体管芯之间的粘着层，其中所述基底层的导热系数大于所述绝缘包封体的导热系数，且所述粘着层的导热系数大于所述绝缘包封体的所述导热系数。在一些实施例中，在所述封装结构中，其中在剖面图中，在所述基底层的侧壁与所述粘着层的侧壁之间存在第一偏移，且在所述粘着层的所述侧壁与所述第一半导体管芯的侧壁之间存在第二偏移，且所述第一偏移与所述第二偏移独立地介于从5μm到5000μm的范围内。在一些实施例中，在所述封装结构中，其中所述电路元件是不与所述绝缘包封体相接触的电路衬底，且所述封装结构还包括：中介体结构，位于所述第一半导体管芯与所述电路元件之间且连接到所述第一半导体管芯及所述电路元件；以及多个导电端子，位于所述电路元件上，所述电路元件位于所述中介体结构与所述多个导电端子之间。在一些实施例中，在所述封装结构中，其中所述电路元件是重布线路结构，所述重布线路结构的被所述第一半导体管芯及所述第二半导体管芯暴露出的部分被所述绝缘包封体覆盖，且所述封装结构还包括：多个导电端子，位于所述电路元件上，所述电路元件位于所述绝缘包封体与所述多个导电端子之间。在一些实施例中，在所述封装结构中，其中所述电路元件是重布线路结构，所述重布线路结构的被所述第一半导体管芯及所述第二半导体管芯暴露出的部分被所述绝缘包封体覆盖，且所述封装结构还包括：连接元件，具有半导体衬底及穿透所述半导体衬底的多个穿孔，所述连接元件位于所述第一半导体管芯及所述第二半导体管芯上，所述第一半导体管芯与所述第二半导体管芯通过所述连接元件电连通；多个导电柱，位于所述第一半导体管芯及所述第二半导体管芯上且连接到所述第一半导体管芯及所述第二半导体管芯，并位于所述连接元件旁边；以及多个导电端子，位于所述电路元件上，所述电路元件位于所述绝缘包封体与所述多个导电端子之间，其中所述绝缘包封体包括包封所述第一半导体管芯及所述第二半导体管芯的第一部分以及包封所述连接元件及所述多个导电柱的第二部分，所述第二部分位于所述第一部分与所述电路元件之间。
根据一些实施例，一种制造封装结构的方法包括以下步骤，提供连接有散热元件的第一半导体管芯；提供第二半导体管芯；将所述第一半导体管芯、所述第二半导体管芯及所述散热元件包封在绝缘包封体中；以及将所述绝缘包封体平坦化，以使所述绝缘包封体暴露出所述散热元件，其中所述第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述第二半导体管芯的第二厚度。
在一些实施例中，在所述制造封装结构的方法中，其中提供连接有所述散热元件的所述第一半导体管芯包括：提供具有电路系统的第一晶片及包括所述散热元件的第二晶片；将所述第一晶片接合到所述第二晶片，以形成堆叠结构；以及对所述堆叠结构进行切分，以形成连接有所述散热元件的所述第一半导体管芯。在一些实施例中，在所述制造封装结构的方法中，其中提供连接有所述散热元件的所述第一半导体管芯包括：提供所述第一半导体管芯；将所述第一半导体管芯设置在电路元件上；以及将所述散热元件设置在所述第一半导体管芯上。在一些实施例中，所述制造封装结构的方法还包括：在所述绝缘包封体上形成电连接到所述第一半导体管芯及所述第二半导体管芯的重布线路结构；以及在所述重布线路结构上设置多个导电端子，其中所述重布线路结构夹置在所述多个导电端子与所述绝缘包封体之间。在一些实施例中，在所述制造封装结构的方法中，其中所述绝缘包封体包括包封所述第一半导体管芯及所述第二半导体管芯的第一部分及堆叠在所述第一部分上的第二部分，在形成所述重布线路结构之前，所述方法还包括：在被包封在所述第一部分中的所述第一半导体管芯及所述第二半导体管芯上设置连接元件，以电连通所述第一半导体管芯与所述第二半导体管芯；在所述第一半导体管芯及所述第二半导体管芯上形成多个导电柱；以及将所述连接元件及所述多个导电柱包封在所述绝缘包封体的所述第二部分中，所述第二部分位于所述第一部分与所述重布线路结构之间。在一些实施例中，所述制造封装结构的方法还包括：提供其中具有多个穿孔的中介体；在将所述第一半导体管芯及所述第二半导体管芯包封在所述绝缘包封体中之前，通过倒装芯片接合将所述第一半导体管芯及所述第二半导体管芯设置在所述中介体上；在将所述绝缘包封体平坦化之后，将所述中介体图案化以显露出所述多个穿孔；在被显露出的所述多个穿孔上形成多个连接件，所述中介体夹置在所述绝缘包封体与所述多个连接件之间；以及通过所述中介体的所述多个连接件，将所述第一半导体管芯与所述第二半导体管芯接合在具有多个导电端子的电路结构上，所述电路衬底夹置在所述多个导电端子与所述多个连接件之间。在一些实施例中，所述制造封装结构的方法还包括：提供盖；将所述盖设置在所述电路衬底上，所述第一半导体管芯、所述第二半导体管芯及所述中介体位于由所述盖及所述电路结构包围的空间中；以及在所述盖和与所述绝缘包封体的表面实质上齐平的所述散热元件的表面之间设置热粘着层。
根据一些实施例，一种制造封装结构的方法包括以下步骤，提供至少一个第一半导体管芯及至少一个第二半导体管芯；在所述至少一个第一半导体管芯的表面上设置虚设元件，所述至少一个第一半导体管芯位于所述虚设元件之上；将所述至少一个第一半导体管芯、所述至少一个第二半导体管芯及所述虚设元件包封在绝缘包封体中；将所述绝缘包封体平坦化，以使所述绝缘包封体的表面暴露出所述虚设元件；移除所述虚设元件，以在所述绝缘包封体中形成凹槽；以及在所述至少一个第一半导体管芯上及在所述凹槽中设置散热元件，其中所述至少一个第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述至少一个第二半导体管芯的第二厚度。
在一些实施例中，在所述制造封装结构的方法中，在移除所述虚设元件之前，还包括：在所述绝缘包封体上形成电连接到所述至少一个第一半导体管芯及所述至少一个第二半导体管芯的重布线路结构；以及在所述重布线路结构上设置多个导电端子，其中所述重布线路结构夹置在所述多个导电端子与所述绝缘包封体之间。在一些实施例中，在所述制造封装结构的方法中，其中所述绝缘包封体包括包封所述至少一个第一半导体管芯及所述至少一个第二半导体管芯的第一部分及堆叠在所述第一部分上的第二部分，在形成所述重布线路结构之前，所述方法还包括：在被包封在所述第一部分中的所述至少一个第一半导体管芯及所述至少一个第二半导体管芯上设置连接元件，以电连通所述至少一个第一半导体管芯与所述至少一个第二半导体管芯；在所述至少一个第一半导体管芯及所述至少一个第二半导体管芯上形成多个导电柱；以及将所述连接元件及所述多个导电柱包封在所述绝缘包封体的所述第二部分中，所述第二部分位于所述第一部分与所述重布线路结构之间。在一些实施例中，所述制造封装结构的方法还包括：提供其中具有多个穿孔的中介体；在所述至少一个第一半导体管芯上设置所述虚设元件之前，通过倒装芯片接合将所述至少一个第一半导体管芯及所述至少一个第二半导体管芯设置在所述中介体上；在将所述绝缘包封体平坦化之后，将所述中介体图案化以显露出所述多个穿孔；在被显露出的所述多个穿孔上形成多个连接件，所述中介体夹置在所述绝缘包封体与所述多个连接件之间；以及通过所述中介体的所述多个连接件，将所述第一半导体管芯与所述第二半导体管芯接合在具有多个导电端子的电路结构上，所述电路衬底夹置在所述多个导电端子与所述多个连接件之间。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、取代及变更。

Claims (10)

1.一种封装结构，包括：
电路元件；
第一半导体管芯及第二半导体管芯，位于所述电路元件上；
散热元件，连接到所述第一半导体管芯，所述第一半导体管芯位于所述电路元件与所述散热元件之间，其中所述第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述第二半导体管芯的第二厚度；以及
绝缘包封体，包封所述第一半导体管芯、所述第二半导体管芯及所述散热元件，其中所述散热元件的表面与所述绝缘包封体的表面实质上齐平。
2.根据权利要求1所述的封装结构，其中在剖面图中，所述散热元件的侧壁与所述第一半导体管芯的侧壁实质上对齐。
3.根据权利要求1所述的封装结构，其中所述散热元件包括基底层及位于所述基底层与所述第一半导体管芯之间的粘着层，其中所述基底层的导热系数大于所述绝缘包封体的导热系数，且所述粘着层的导热系数大于所述绝缘包封体的所述导热系数。
4.根据权利要求3所述的封装结构，其中在剖面图中，在所述基底层的侧壁与所述粘着层的侧壁之间存在第一偏移，且在所述粘着层的所述侧壁与所述第一半导体管芯的侧壁之间存在第二偏移，且所述第一偏移与所述第二偏移独立地介于从5μm到5000μm的范围内。
5.一种制造封装结构的方法，包括：
提供连接有散热元件的第一半导体管芯；
提供第二半导体管芯；
将所述第一半导体管芯、所述第二半导体管芯及所述散热元件包封在绝缘包封体中；以及
将所述绝缘包封体平坦化，以使所述绝缘包封体暴露出所述散热元件，其中所述第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述第二半导体管芯的第二厚度。
6.根据权利要求5所述的方法，其中提供连接有所述散热元件的所述第一半导体管芯包括：
提供具有电路系统的第一晶片及包括所述散热元件的第二晶片；
将所述第一晶片接合到所述第二晶片，以形成堆叠结构；以及
对所述堆叠结构进行切分，以形成连接有所述散热元件的所述第一半导体管芯。
7.根据权利要求5所述的方法，其中提供连接有所述散热元件的所述第一半导体管芯包括：
提供所述第一半导体管芯；
将所述第一半导体管芯设置在电路元件上；以及
将所述散热元件设置在所述第一半导体管芯上。
8.一种制造封装结构的方法，包括：
提供至少一个第一半导体管芯及至少一个第二半导体管芯；
在所述至少一个第一半导体管芯的表面上设置虚设元件，所述至少一个第一半导体管芯位于所述虚设元件之上；
将所述至少一个第一半导体管芯、所述至少一个第二半导体管芯及所述虚设元件包封在绝缘包封体中；
将所述绝缘包封体平坦化，以使所述绝缘包封体的表面暴露出所述虚设元件；
移除所述虚设元件，以在所述绝缘包封体中形成凹槽；以及
在所述至少一个第一半导体管芯上及在所述凹槽中设置散热元件，其中所述至少一个第一半导体管芯的第一厚度与所述散热元件的第三厚度之和实质上等于所述至少一个第二半导体管芯的第二厚度。
9.根据权利要求8所述的方法，在移除所述虚设元件之前，还包括：
在所述绝缘包封体上形成电连接到所述至少一个第一半导体管芯及所述至少一个第二半导体管芯的重布线路结构；以及
在所述重布线路结构上设置多个导电端子，其中所述重布线路结构夹置在所述多个导电端子与所述绝缘包封体之间。
10.根据权利要求9所述的方法，其中所述绝缘包封体包括包封所述至少一个第一半导体管芯及所述至少一个第二半导体管芯的第一部分及堆叠在所述第一部分上的第二部分，
在形成所述重布线路结构之前，所述方法还包括：
在被包封在所述第一部分中的所述至少一个第一半导体管芯及所述至少一个第二半导体管芯上设置连接元件，以电连通所述至少一个第一半导体管芯与所述至少一个第二半导体管芯；
在所述至少一个第一半导体管芯及所述至少一个第二半导体管芯上形成多个导电柱；以及
将所述连接元件及所述多个导电柱包封在所述绝缘包封体的所述第二部分中，所述第二部分位于所述第一部分与所述重布线路结构之间。
CN202010096503.9A 2019-09-17 2020-02-17 封装结构及其制造方法 Pending CN112530913A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/572,619 US11164855B2 (en) 2019-09-17 2019-09-17 Package structure with a heat dissipating element and method of manufacturing the same
US16/572,619 2019-09-17

Publications (1)

Publication Number Publication Date
CN112530913A true CN112530913A (zh) 2021-03-19

Family

ID=74869057

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010096503.9A Pending CN112530913A (zh) 2019-09-17 2020-02-17 封装结构及其制造方法

Country Status (3)

Country Link
US (1) US11164855B2 (zh)
CN (1) CN112530913A (zh)
TW (1) TWI727523B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI778691B (zh) * 2021-03-24 2022-09-21 台灣積體電路製造股份有限公司 積體電路封裝及其製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11728238B2 (en) * 2019-07-29 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with heat dissipation films and manufacturing method thereof
US11404379B2 (en) * 2020-11-17 2022-08-02 International Business Machines Corporation Structure and method for bridge chip assembly with capillary underfill
US11862590B2 (en) 2021-04-14 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of forming thereof
US20230014913A1 (en) * 2021-07-15 2023-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. Heat Dissipation Structures for Integrated Circuit Packages and Methods of Forming the Same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
KR101942744B1 (ko) 2017-11-03 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI778691B (zh) * 2021-03-24 2022-09-21 台灣積體電路製造股份有限公司 積體電路封裝及其製造方法
US11848246B2 (en) 2021-03-24 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method

Also Published As

Publication number Publication date
US11164855B2 (en) 2021-11-02
US20210082894A1 (en) 2021-03-18
TW202113995A (zh) 2021-04-01
TWI727523B (zh) 2021-05-11

Similar Documents

Publication Publication Date Title
TWI681466B (zh) 半導體結構及積體電路封裝的形成方法
US11189603B2 (en) Semiconductor packages and methods of forming same
US11495573B2 (en) Package structure and manufacturing method thereof
TW202017131A (zh) 封裝結構、晶粒及其製造方法
CN110112115B (zh) 集成电路封装件及其形成方法
TWI727523B (zh) 封裝結構及其製造方法
US11756855B2 (en) Method of fabricating package structure
CN110610907B (zh) 半导体结构和形成半导体结构的方法
CN112242383A (zh) 芯片结构
US11264362B2 (en) Semiconductor structure and method of fabricating the same
KR102564124B1 (ko) 집적 회로 패키지 및 그 형성 방법
KR20240005646A (ko) 집적 회로 패키지 및 방법
CN115295507A (zh) 集成电路器件和其形成方法
US11756854B2 (en) Package structure and method of fabricating the same
US20220165675A1 (en) Semiconductor structure and method of fabricating the same
TWI790702B (zh) 半導體封裝及製造半導體封裝的方法
CN219873491U (zh) 具有热增强性能的封装结构
US20230065941A1 (en) Semiconductor package and method of manufacturing the same
US20230317585A1 (en) Package structure and manufacturing method thereof
TW202341399A (zh) 積體電路封裝及其形成方法
CN115377074A (zh) 内存装置、封装结构及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination