TWI727523B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

Info

Publication number
TWI727523B
TWI727523B TW108143536A TW108143536A TWI727523B TW I727523 B TWI727523 B TW I727523B TW 108143536 A TW108143536 A TW 108143536A TW 108143536 A TW108143536 A TW 108143536A TW I727523 B TWI727523 B TW I727523B
Authority
TW
Taiwan
Prior art keywords
semiconductor die
semiconductor
heat dissipation
layer
package structure
Prior art date
Application number
TW108143536A
Other languages
English (en)
Other versions
TW202113995A (zh
Inventor
陳偉銘
吳集錫
吳志偉
丁國強
盧思維
侯上勇
施應慶
鄒賢儒
李澄傑
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202113995A publication Critical patent/TW202113995A/zh
Application granted granted Critical
Publication of TWI727523B publication Critical patent/TWI727523B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141—Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H01L2224/11424—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27416—Spin coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27422—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/27515—Curing and solidification, e.g. of a photosensitive layer material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/83409—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/83487—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83499—Material of the matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83598—Fillers
    • H01L2224/83599—Base material
    • H01L2224/836—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/83598—Fillers
    • H01L2224/83599—Base material
    • H01L2224/836—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

一種封裝結構包括電路元件、第一半導體晶粒、第二半導體晶粒、散熱元件以及絕緣包封體。第一半導體晶粒及第二半導體晶粒位於電路元件上。散熱元件連接到第一半導體晶粒，且第一半導體晶粒位於電路元件與散熱元件之間，其中第一半導體晶粒的第一厚度與散熱元件的第三厚度之和實質上等於第二半導體晶粒的第二厚度。絕緣包封體包封第一半導體晶粒、第二半導體晶粒及散熱元件，其中散熱元件的表面與絕緣包封體實質上齊平。

Description

封裝結構及其製造方法
本揭露實施例是有關於一種封裝結構及其製造方法。
半導體元件及積體電路(integrated circuit，IC)通常是在單個半導體晶圓上製造。在晶圓級製程中，可對晶圓的晶粒進行加工並與其他半導體裝置或其他晶粒封裝在一起，且用於晶圓級封裝的各種技術(例如，形成重佈線路結構/層)已被開發。另外，這種封裝可在切分(dicing)之後進一步積體/整合到半導體基底或載體。
本揭露實施例提供一種封裝結構，所述封裝結構包括電路元件、第一半導體晶粒、第二半導體晶粒、散熱元件以及絕緣包封體。所述第一半導體晶粒及所述第二半導體晶粒位於所述電路元件上。所述散熱元件連接到所述第一半導體晶粒，且所述第一半導體晶粒位於所述電路元件與所述散熱元件之間，其中所述第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述第二半導體晶粒的第二厚度。所述絕緣包封體包封所述第 一半導體晶粒、所述第二半導體晶粒及所述散熱元件，其中所述散熱元件的表面與所述絕緣包封體的表面實質上齊平。
本揭露實施例提供一種製造封裝結構的方法包括以下步驟，提供連接有散熱元件的第一半導體晶粒；提供第二半導體晶粒；將所述第一半導體晶粒、所述第二半導體晶粒及所述散熱元件包封在絕緣包封體中；以及將所述絕緣包封體平坦化，以使所述絕緣包封體暴露出所述散熱元件，其中所述第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述第二半導體晶粒的第二厚度。
本揭露實施例提供一種製造封裝結構的方法包括以下步驟，提供至少一個第一半導體晶粒及至少一個第二半導體晶粒；在所述至少一個第一半導體晶粒的表面上設置虛設元件，所述至少一個第一半導體晶粒位於所述虛設元件之上；將所述至少一個第一半導體晶粒、所述至少一個第二半導體晶粒及所述虛設元件包封在絕緣包封體中；將所述絕緣包封體平坦化，以使所述絕緣包封體的表面暴露出所述虛設元件；移除所述虛設元件，以在所述絕緣包封體中形成凹槽；以及在所述至少一個第一半導體晶粒上及在所述凹槽中設置散熱元件，其中所述至少一個第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述至少一個第二半導體晶粒的第二厚度。
10a、10b、10c、10d、10e、10f、30:半導體元件
20:第二半導體元件/半導體元件
20b、110b、210b、320b、S1:底表面
22、33、140、CP1、CP2:導通孔
31、110:半導體基底
31a:主動表面
32、120:內連結構
32a、122:層間介電層
32b、124:圖案化導電層
41、310、500:基底
42、340、800:重佈線路結構
42a、342:介電結構
42b、344、530、804:金屬化層
43、320:穿孔
100:第一半導體晶粒/半導體晶粒
110a、210a、220a:頂表面
130:鈍化層
130a、310a、310b、400a、700a、700b、702a、S2、S3:表面
210:基底層
220:黏著層
360、380:導電連接件
400、400m、700、702:絕緣包封體
510、520:接合墊
540、550:表面元件
560:導電元件
600:散熱蓋
610:熱介面材料
620:接合元件
802、PM1:介電層
900:導電端子
BE:橋接元件
C1:載體
D1、D2、D3:偏移
DE:虛設元件
HD1、HD2:固持元件
HDE:散熱元件
O1:開口
P1A、P1B、P1C、P1D、P1E、P1F、P2A、P2C、P2E、P2F、P3A、P3C、P3E、P4A、P4B、P5A、P5B、P6A、P6B、P7A、P7B:封裝結構
R:凹槽
S10、S11、S12、S13、S14、S15、S16、S17、S18、S19、S20、S21、S22、S23、S24、S25、S26、S27、S30、S31、S32、S33、S34、S35、S36、S37、S38、S40、S41、S42、S43、S44、S45、S46、S50、S51、S52、S53、S54、S55、S60、S61、S62、S63、S64、S65、S66、S70、S71、S72、S73、S74、S75、S76、S77、S78、S79、S80、S81、 S82、S83、S84、S85、S86、S87、S88、S90、S91、S92、S93、S94、S95、S96、S97、S98、S99:步驟
T1、T1’:總厚度
u1:球下金屬(UBM)圖案
UF1、UF2:底部填充膠
W1、W2:晶圓
Z:堆疊方向
當結合附圖閱讀時，自以下詳細描述最佳地理解本發明之態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪 製。實際上，可出於論述清楚起見，任意地增加或減小各種特徵之尺寸。
圖1到圖13及圖14A是根據本公開一些實施例的封裝結構的製造方法中的各個階段的示意性剖面圖。
圖14B是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖15是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖16是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖17是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖18到圖19是根據本公開一些實施例的封裝結構的製造方法中的各個階段的示意性剖面圖。
圖20是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖21A及圖21B是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖22是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖23是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖24到圖33A是根據本公開一些實施例的封裝結構的製造方法中的各個階段的示意性剖面圖。
圖33B是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖34是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖35是示出根據本公開一些實施例的製造封裝結構的方法 的流程圖。
圖36是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖37是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖38是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖39是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖40是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖41是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖42是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖43是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖44是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖45是根據本公開一些實施例的封裝結構的示意性剖面圖。
圖46是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖47是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖48是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。
圖49是根據本公開一些實施例的封裝結構的示意性剖面圖。
以下揭露內容提供用以實施本發明的不同特徵的許多不 同實施例或實例。以下描述組件及配置的具體實例以簡化本發明。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡化及清楚之目的，且自身並不規定所論述之各種實施例及/或組態之間的關係。
此外，可在本文中使用空間相對術語，諸如「在...下方」、「在...之下」、「下部」、「在...上方」、「上部」以及類似術語，以描述如在圖式中所說明的一個元件或特徵與另一(一些)元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
另外，為易於說明，本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”、“第四(fourth)”、“第五(fifth)”等用語來闡述圖中所示的相似的元件或特徵或者不同的元件或特徵，且可依據呈現次序或說明的上下文而互換地使用。
本公開還可包括其他特徵及製程。舉例來說，可包括測試結構以說明對三維(three-dimensional，3D)封裝或三維積體電路(three-dimensional integrated circuit，3DIC)元件進行驗證測試。所述測試結構可包括例如在重佈線層中或在基底上形成的測試 墊，以使得能夠對3D封裝或3DIC進行測試、對探針和/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒(known good die)進行中間驗證的測試方法來使用，以提高良率(yield)並降低成本。
圖1到圖13及圖14A是根據本公開一些實施例的封裝結構的製造方法中的各個階段的示意性剖面圖。圖14B是根據本公開一些實施例的封裝結構的示意性剖面圖。圖15是根據本公開一些實施例的封裝結構的示意性剖面圖。圖16是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖17是根據本公開一些實施例的封裝結構的示意性剖面圖。在圖1到圖14A、圖14B、圖15及圖17中，示出一個或多於一個(半導體)晶片或晶粒來表示晶圓的多個(半導體)晶片或晶粒，且示出一個(半導體)封裝結構來表示在(半導體)製造方法之後獲得的多個(半導體)封裝結構，本公開並非僅限於此。在其他實施例中，示出一個或多於一個(半導體)晶片或晶粒來表示晶圓的多個(半導體)晶片或晶粒，且示出一個或多於一個(半導體)封裝結構來表示在(半導體)製造方法之後獲得的多個(半導體)封裝結構。
參照圖1，在一些實施例中，根據圖16的步驟S10，提供包括佈置成陣列的多個半導體晶粒100的晶圓W1。在對晶圓W1執行晶圓鋸切(sawing)或切分(dicing)製程之前，晶圓W1的半導體晶粒100為彼此連接，如圖1中所示。在一些實施例中，晶圓W1包括半導體基底110、設置在半導體基底110上的內連結構120以及覆蓋內連結構120的鈍化層130。如圖1中所示，例 如，半導體基底110具有頂表面110a以及與頂表面110a相對的底表面110b，且內連結構120位於半導體基底110的頂表面110a上且夾置在半導體基底110與鈍化層130之間。
在一些實施例中，半導體基底110可為矽基底，所述矽基底包括形成在其中的主動元件(例如電晶體和/或記憶體(例如N型金屬氧化物半導體(N-type metal-oxide semiconductor，NMOS)和/或P型金屬氧化物半導體(P-type metal-oxide semiconductor，PMOS)元件等))和/或被動元件(例如電阻器、電容器、電感器等)。在一些實施例中，此種主動元件及被動元件可在前段(front-end-of-line，FEOL)製程中形成。在替代實施例中，半導體基底110可為塊狀矽基底，例如塊狀單晶矽基底、經摻雜的矽基底、未經摻雜的矽基底或絕緣體上有矽(silicon-on-insulator，SOI)基底，其中經摻雜的矽基底的摻雜劑可為N型摻雜劑、P型摻雜劑或其組合。本公開並非僅限於此。
半導體基底110可包含例如以下其他半導體材料：鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、和/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP；或者其組合。也可使用其他基底，例如多層式(multi-layered)基底或梯度基底(gradient substrate)。半導體基底110具有有時被稱為前側的主動表面(例如，頂表面110a)以及有時被稱為背側的非主動表面(例如，底表面110b)。
在一些實施例中，內連結構120可包括交替地堆疊的一個或多個層間介電層122與一個或多個圖案化導電層124。舉例來說，層間介電層122可為氧化矽層、氮化矽層、氮氧化矽層或由其 他合適的介電材料形成的介電層，且層間介電層122可通過沉積等形成。舉例來說，圖案化導電層124可為圖案化銅層或其他合適的圖案化金屬層，且圖案化導電層124可通過電鍍或沉積形成。然而，本公開並非僅限於此。在一些實施例中，圖案化導電層124可通過雙鑲嵌方法形成。層間介電層122的數目及圖案化導電層124的數目可小於或大於圖1中所繪示的數目，且可基於需要和/或設計佈局來指定；本公開並非特別限制於此。在說明通篇中，用語“銅”旨在包括實質上純的元素銅、包含不可避免的雜質的銅、以及包含少量元素(例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯等)的銅合金。
在某些實施例中，如圖1中所示，圖案化導電層124夾置在層間介電層122之間，其中圖案化導電層124的最頂層的頂表面至少局部地被形成在層間介電層122的最頂層中的多個開口O1暴露出以連接到稍後形成的元件以進行電連接，且圖案化導電層124的最低層的底表面至少局部地被形成在層間介電層122的最低層中的多個開口(未標記)暴露出且電連接到半導體基底110中所包括的主動元件和/或被動組件。開口O1及形成在層間介電層122的最低層中的開口的形狀及數目在本公開中不受限制，且可基於需要和/或設計佈局來指定。
本公開並非僅限於此。在替代實施例(未示出)中，圖案化導電層124可夾置在層間介電層122之間，其中圖案化導電層124的最頂層的頂表面可被層間介電層122完全覆蓋以防止由後續製程引起的損壞，且圖案化導電層124的最低層的底表面可至少局部地被形成在層間介電層122的最低層中的開口暴露出且電 連接到下伏的主動元件和/或被動組件。舉例來說，通過後續圖案化製程，被層間介電層122的最頂層覆蓋的圖案化導電層124的最頂層的頂表面可被形成在層間介電層122的最頂層中的多個開口暴露出以電連接到稍後形成的上覆在圖案化導電層124的最頂層的頂表面上的元件。
在一些實施例中，如圖1中所示，鈍化層130形成在內連結構120上，其中內連結構120被鈍化層130覆蓋且與鈍化層130接觸。如圖1中所示，例如，鈍化層130具有實質上平坦的表面130a。在某些實施例中，鈍化層130的表面130a可為齊平的且可具有高平坦度及高平面度，這對於稍後形成的層是有益的。在一些實施例中，鈍化層130可為聚醯亞胺(polyimide，PI)層、聚苯並噁唑(polybenzoxazole，PBO)層、二氧化矽系(非有機)層或其他合適的聚合物(或有機)層，且可通過沉積等形成。本公開並非僅限於此。在一些實施例中，鈍化層130完全覆蓋圖案化導電層124的最頂層及層間介電層122的最頂層，其中內連結構120被鈍化層130良好地保護起來，免受由後續製程引起的損壞。如圖1中所示，例如，內連結構120位於半導體基底110的頂表面110a與鈍化層130之間。本公開並不特別限制鈍化層130的厚度，只要鈍化層130的表面130a可保持其高平坦度及高平面度即可。在本公開中，鈍化層的表面130a可被稱為半導體晶粒100的頂表面。
繼續圖1，在一些實施例中，根據圖16的步驟S11，還提供包括佈置成陣列的多個散熱元件HDE的晶圓W2。在對晶圓W2執行晶圓鋸切或切分製程之前，晶圓W2的散熱元件HDE為 彼此連接，如圖1中所示。在本公開中，散熱元件HDE還被稱為散熱器元件(heat spreader element)。在一些實施例中，晶圓W2包括基底層210及塗布在基底層(base layer)210上的黏著層220。如圖1中所示，例如，基底層210具有頂表面210a及與頂表面210a相對的底表面210b，且黏著層220形成在基底層210的頂表面210a上。在本公開中，基底層210的材料與黏著層220的材料不同。在晶圓W2包括基底層210及黏著層220的實施例中，晶圓W2中所包括的基底層210與黏著層220在本公開中一起被稱為一個散熱元件HDE。
然而，本公開並非僅限於此；在替代實施例中，可從晶圓W2省略黏著層220。也就是說，在晶圓W2不包括黏著層220的實施例中，晶圓W2中所包括的基底層210在本公開中被單獨稱為一個散熱元件HDE。
在一些實施例中，給定基底層210具有比稍後形成的絕緣包封體大的導熱係數(thermal conductivity coefficient)，基底層210可包括矽系層(例如矽基底或氧化矽層)、陶瓷層、金屬膜(例如銅(Cu)膜、鋁(Al)膜、銦(In)膜或銀(Ag)膜)、由金屬膏(例如Ag膏、Cu膏、奈米Ag膏或奈米Cu膏)形成的層、聚合物層、化合物層或由任何合適的其他材料製成的層。
在一些實施例中，給定黏著層220具有比稍後形成的絕緣包封體大的導熱係數且能夠將基底層210黏著到將設置在基底層210上方的任何層或任何晶圓(例如晶圓W1)，黏著層220可包括矽系層(例如氧化矽層、氮化矽層)、由金屬膏形成的層、聚合物層或由任何合適的其他材料製成的層。舉例來說，黏著層220 可為晶粒貼合膜(die attach film，DAF)、液態DAF、膠層或黏著條帶(adhesive tape)。在一些實施例中，黏著層220可通過疊層(lamination)、旋轉塗布方法、浸漬塗布方法或合適的塗布方法形成在基底層210上。舉例來說，黏著層220可作為液體(例如液態DAF)分配在基底層210上並被固化，或者可為疊層到基底層210上的疊層膜(例如DAF)。本公開並非僅限於此。黏著層220的頂表面220a可為齊平的且可具有高共面度。
一起參照圖1與圖2，在一些實施例中，根據圖16的步驟S11，將晶圓W1拾取並放置在晶圓W2上，且將晶圓W1接合到晶圓W2。舉例來說，圖2中所繪示的結構的總厚度T1介於從100微米(micrometer)到2000微米的範圍內。如圖2中所示，半導體基底110位於內連結構120與基底層210之間，內連結構120位於鈍化層130與半導體基底110之間，且黏著層220位於半導體基底110與基底層210之間。在本公開中，基底層210與黏著層220(如果有的話)獨立地熱耦合到晶圓W1的半導體基底110。換句話說，晶圓W2中所包括的散熱元件HDE熱耦合到晶圓W1中所包括的半導體晶粒100中的每一者。
在一些實施例中，如圖1及圖2中所示，晶圓W1的半導體基底110的底表面110b面朝晶圓W2的黏著層220的頂表面220a，其中晶圓W1是通過借助黏著層220將半導體基底110接合到基底層210(例如間接接合方法)而接合到晶圓W2。在一個實施例中，在使用由具有黏著特性的材料(例如金屬膏、聚合物等)製成的黏著層220將晶圓W1的半導體基底110接合到晶圓W2的基底層210時，晶圓W1是通過黏合(adhesion)而接合到 晶圓W2。在替代實施例中，在使用由材料(例如矽系層)製成的黏著層220將晶圓W1的半導體基底110接合到晶圓W2的基底層210時，晶圓W1是通過熔合接合(fusion bonding)而接合到晶圓W2。也就是說，通過黏著層220，晶圓W1的半導體基底110通過黏合或熔合接合而間接接合到晶圓W2的基底層210。應理解，在本公開的實施例中，由於黏著層220的存在，基底層210的材料與黏著層220的材料不同。
然而，本公開並非僅限於此；在省略黏著層220的替代實施例中，晶圓W1可通過黏著或熔合接合而直接接合到晶圓W2。也就是說，晶圓W1的半導體基底110的底表面110b面朝晶圓W2的基底層210的頂表面210a，其中晶圓W1通過將半導體基底110的底表面110b實體地接合到基底層210的頂表面210a(例如，直接接合方法)而接合到晶圓W2。在一個實施例中，在將由具有黏著特性的材料(例如金屬膏、聚合物等)製成的基底層210用於直接接合到晶圓W1的半導體基底110時，晶圓W1是通過粘合而接合到晶圓W2。在替代實施例中，在將由材料(例如矽系層)製成的基底層210用於直接接合到晶圓W1的半導體基底110時，晶圓W1是通過熔合接合而接合到晶圓W2。也就是說，由於基底層210，晶圓W1的半導體基底110通過粘合或熔合接合而直接接合到晶圓W2的基底層210。
參照圖3，在一些實施例中，對基底層210的底表面210b執行平坦化步驟。在平坦化之後，基底層210可被認為是經平坦化的基底層或經薄化的基底層。在一些實施例中，圖3中所繪示的平坦化結構的總厚度T1’可介於從100微米到1200微米的範圍 內。在一些實施例中，平坦化步驟可包括研磨製程或化學機械拋光(chemical mechanical polishing，CMP)製程。在平坦化步驟之後，可視需要執行清潔步驟，例如清潔及移除平坦化步驟所產生的殘留物。然而，本公開並非僅限於此，且平坦化步驟可通過任何其他合適的方法來執行。
在某些實施例中，為了促進前述於圖3中所繪示的製程，可通過使鈍化層130與黏著膜(未示出)接觸，而使圖2中所繪示的結構與支撐件(未示出)臨時粘合或與臨時載體(未示出，例如黏著條帶、黏著載體、吸力墊等)臨時粘合。然而，本公開並非僅限於此。在一個實施例中，在半導體基底110的厚度足夠厚以執行前述於圖3中所繪示的製程而不會產生損壞(例如裂紋或破碎的晶圓)時，則無需將鈍化層130與支撐件臨時粘合。
參照圖4，在一些實施例中，在內連結構120上及半導體基底110之上形成多個導通孔140，且導通孔140的側壁被鈍化層130包繞。在一些實施例中，如圖4中所示，導通孔140各自穿透鈍化層130且延伸到形成在層間介電層122的最頂層中的開口O1中以實體地接觸被開口O1暴露出的圖案化導電層124的最頂層的頂表面。通過內連結構120，導通孔140電連接到半導體基底110中所包括的主動元件和/或被動組件。
應理解，半導體晶粒100各自至少包括半導體基底110、內連結構120、鈍化層130及導通孔140。在一些實施例中，本文中所闡述的半導體晶粒100中的每一者可被稱為半導體晶片或積體電路(IC)。在一些實施例中，半導體晶粒100各自為邏輯晶片，例如中央處理器(central processing unit，CPU)、圖形處理單元 (graphic processing unit，GPU)、系統晶片(system-on-a-chip，SoC)、微控制器等。然而，本公開並非僅限於此；在替代實施例中，半導體晶粒100可獨立地包括一個或多個數位晶片、類比晶片或混合訊號晶片，例如應用專用積體電路(application-specific integrated circuit，“ASIC”)晶片、感測器晶片、無線及射頻(radio frequency，RF)晶片、記憶體晶片或電壓調節器晶片。在一些替代實施例中，半導體晶粒100可獨立地被稱為組合類型的晶片或IC，例如同時包括RF晶片及數位晶片二者的WiFi晶片。
在一些實施例中，如圖4中所示，對於每一半導體晶粒100，與內連結構120實體地接觸的導通孔140遠離鈍化層130的表面130a延伸。為了簡化起見，出於例示目的，在圖4中在每一半導體晶粒100中僅呈現出兩個導通孔140，然而應注意，可形成多於兩個導通孔140；本公開並非僅限於此。在一些實施例中，在半導體基底110的頂表面110a上沿半導體基底110、內連結構120及鈍化層130的堆疊方向Z的垂直投影中，導通孔140可獨立地為圓形、橢圓形、三角形、矩形等。導通孔140的形狀在本公開中不受限制。導通孔140的數目及形狀可基於需要來指定及選擇，且通過改變開口O1的數目及形狀來進行調整。
在一些實施例中，導通孔140是通過顯影、鍍覆、光阻剝除製程(photoresist stripping process)或任何其他合適的方法形成。舉例來說，鍍覆製程可包括電鍍、無電鍍覆等。在一個實施例中，導通孔140可通過以下方式形成：形成覆蓋鈍化層130的罩幕圖案(未示出)，所述罩幕圖案具有多個開口(未示出)，所述開口與被開口O1暴露出的圖案化導電層124的最頂層的頂表面對應；將 鈍化層130圖案化以在鈍化層130中形成多個接觸開口(未示出)，從而暴露出被開口O1暴露出的圖案化導電層124的最頂層的頂表面；通過電鍍或沉積形成填充形成在罩幕圖案中的開口、形成在鈍化層130中的接觸開口以及開口O1的金屬材料以形成多個導通孔140；以及接著移除罩幕圖案。在一些實施例中，可通過蝕刻製程(例如乾式蝕刻製程、濕式蝕刻製程或其組合)來將鈍化層130圖案化。應注意，形成在鈍化層130中的接觸開口與位於鈍化層130之下的相應的一個開口O1在空間上彼此連通以形成導通孔140。在一個實施例中，罩幕圖案可通過可接受的灰化製程和/或光阻剝除製程(例如使用氧電漿等)來移除。在一個實施例中，導通孔140的材料可包括金屬材料，例如銅或銅合金等。
在一些替代實施例中，導通孔140可通過以下方式形成：形成覆蓋鈍化層130的第一罩幕圖案(未示出)，所述第一罩幕圖案具有多個開口(未示出)，所述開口與被開口O1暴露出的圖案化導電層124的最頂層的頂表面對應；將鈍化層130圖案化以在鈍化層130中形成多個接觸開口(未示出)，從而暴露出被開口O1暴露出的圖案化導電層124的最頂層的頂表面；移除第一罩幕圖案；在鈍化層130之上共形地形成金屬晶種層；形成覆蓋鈍化層130與金屬晶種層的第二罩幕圖案(未示出)，所述第二罩幕圖案具有暴露出形成在鈍化層130中的接觸開口以及開口O1的多個開口(未示出)；通過電鍍或沉積形成填充形成在第二罩幕圖案中的開口、形成在鈍化層130中的接觸開口以及開口O1的金屬材料；移除第二罩幕圖案；以及接著移除未被金屬材料覆蓋的金屬晶種層以形成多個導通孔140。在一些實施例中，金屬晶種層被稱為 金屬層，所述金屬層可為單個層或包括由不同材料形成的多個子層的組合層。在一些實施例中，金屬晶種層包含鈦、銅、鉬、鎢、氮化鈦、鈦鎢、其組合等。舉例來說，金屬晶種層可包括鈦層及位於鈦層之上的銅層。金屬晶種層可使用例如濺鍍、物理氣相沉積(physical vapor deposition，PVD)等來形成。
參照圖5，在一些實施例中，根據圖16的步驟S12，對圖4中所繪示的結構執行切分(單體化)製程，以使得圖4中所繪示的結構被切割成單獨且分開的多個半導體元件10a。在一些實施例中，如圖5中所示，採用固持元件HD1來固定圖4中所繪示的結構以防止在切分(單體化)製程期間對半導體元件10a的任何損壞。在一個實施例中，在切分(單體化)製程期間，固持元件HD1不被切割，然而本公開並非僅限於此。在替代實施例(未示出)中，在切分(單體化)製程期間，固持元件HD1可被局部地切割。舉例來說，固持元件HD1可為黏著條帶、黏著載體或吸力墊，本公開並非僅限於此。在一個實施例中，切分(單體化)製程是晶圓切分製程或晶圓單體化製程，所述晶圓切分製程或晶圓單體化製程可包括機械鋸切或雷射切割。本公開並非僅限於此。至此，半導體元件10a得以製造完成，其中半導體元件10a中的每一者包括連接有一個散熱元件HDE的一個半導體晶粒100。在本公開中，在半導體元件10a中的每一者中，散熱元件HDE熱耦合到半導體晶粒100。如圖5中所示，散熱元件HDE的側壁與半導體晶粒100的側壁對齊。
參照圖6，在一些實施例中，根據圖16的步驟S13，提供基底310，其中半導體元件10a(圖5中所繪示的半導體元件 10a)及至少一個半導體元件20被拾取並放置在基底310上，且通過倒裝晶片接合而接合到基底310。在一些實施例中，基底310可為晶圓，例如塊狀半導體基底、SOI基底、多層式半導體基底等。在一些實施例中，基底310的半導體材料可為：矽、鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、和/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP；或者其組合。在替代實施例中，也可使用其他基底，例如多層式基底或梯度基底。基底310例如可為經摻雜的或未經摻雜的且可還包括主動元件和/或被動元件，例如形成在基底310中和/或基底310的表面310a上的電晶體、電容器、電阻器、二極體等。在一些實施例中，表面310a可被稱為基底310的主動表面(或前側)。在某些實施例中，基底310可實質上不包含主動元件和/或被動元件，本公開並非僅限於此。
在一些實施例中，在基底310中形成從基底310的表面310a延伸的多個穿孔320。舉例來說，由於基底310是矽基底，因此穿孔320有時被稱為基底穿孔(through-substrate-via)或矽穿孔(through-silicon-via)。穿孔320可通過例如蝕刻、銑削(milling)、雷射技術、其組合、和/或類似技術在基底310中形成凹槽來形成。可例如通過使用氧化技術在凹槽中形成薄的介電材料。可例如通過化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)、PVD、熱氧化、其組合、和/或類似技術在基底310的表面310a之上及開口中共形地沉積薄的阻擋層。阻擋層可包含氮化物或氮氧化物，例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合、和/或類似材料。可在薄的阻 擋層之上及開口中沉積導電材料。導電材料可通過電化學鍍覆製程、CVD、ALD、PVD、其組合、和/或類似製程形成。導電材料的實例是銅、鎢、鋁、銀、金、其組合、和/或類似材料。通過例如CMP從基底310的表面310a移除多餘的導電材料及阻擋層。因此，穿孔320可包含導電材料以及位於導電材料與基底310之間的薄的阻擋層。
在一些實施例中，在基底310的表面310a上形成重佈線路結構340，且將重佈線路結構340電連接到基底310。在某些實施例中，重佈線路結構340用於提供佈線功能且包括介電結構342及佈置在介電結構342中的一個或多個金屬化層344。在一些實施例中，介電結構342包括一個或多個介電層，以使得介電層及金屬化層344依序形成，且一個金屬化層344夾置在兩個介電層之間。如圖6中所示，金屬化層344的最頂層的頂表面的部分分別被形成在介電結構342的最頂部介電層中的多個開口暴露出，且金屬化層344的最底層的底表面的部分分別被形成在介電結構342的最底部介電層中的多個開口暴露出。然而，本公開並非僅限於此。重佈線路結構340中所包括的金屬化層的數目及介電層的數目並非僅限於此，且可基於需要來指定及選擇。介電結構342的材料及形成可與層間介電層122的材料及形成相同或相似，金屬化層344的材料及形成可與圖案化導電層124的材料及形成相同或相似，且因此在本文中不再重複。如圖6中所示，穿孔320連接到金屬化層344的最底層的底表面的分別被形成在介電結構342的最底部介電層中的開口暴露出的部分。換句話說，重佈線路結構340電連接到穿孔320。在替代實施例中，重佈線路結構340 可還電連接到嵌置在基底310中或形成在基底310的表面310a上的主動元件和/或被動元件。
在一些實施例中，在重佈線路結構340上形成多個導電連接件360。如圖6中所示，例如，導電連接件360形成在金屬化層344的最頂層的頂表面的分別被形成在介電結構342的最頂部介電層中的開口暴露出的部分上且連接到金屬化層344的最頂層的頂表面的分別被形成在介電結構342的最頂部介電層中的開口暴露出的部分。換句話說，導電連接件360電連接到重佈線路結構340。在替代實施例中，通過重佈線路結構340，導電連接件360中的一些導電連接件360可還電連接到基底310(例如，嵌置在基底310中或形成在表面310a上的主動元件和/或被動元件)及穿孔320。
在一些實施例中，導電連接件360可包括球柵陣列(ball grid array，BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold，ENEPIG)技術形成的凸塊等。導電連接件360的材料例如可包括導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等、或者其組合。在一個實施例中，導電連接件360的材料例如可為不包含焊料的。導電連接件360的剖面圖並非僅限於所述實施例，且可基於需要具有任何合適的形狀。
繼續圖6，在一些實施例中，本文中所闡述的半導體元件20中的每一者可被稱為具有多個導通孔22的半導體晶片或積體電路(IC)，其中導通孔22用作半導體元件20的導電端子以電連 接到外部元件。在一些實施例中，半導體元件20各自為記憶體晶片或元件，例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒、混合記憶體立方體(hybrid memory cube，HMC)模組、高頻寬記憶體(high bandwidth memory，HBM)模組等。然而，本公開並非僅限於此；在替代實施例中，半導體元件20可獨立地包括一個或多個數位晶片、類比晶片或混合訊號晶片，例如應用專用積體電路(“ASIC”)晶片、感測器晶片、無線及射頻(RF)晶片、邏輯晶片或電壓調節器晶片。在一些替代實施例中，半導體元件20可獨立地被稱為組合類型的晶片或IC，例如同時包括RF晶片及數位晶片二者的WiFi晶片。
在一個實施例中，半導體元件10a的半導體晶粒100與半導體元件20可為相同類型或不同類型的晶粒。在一個實施例中，半導體元件10a的半導體晶粒100與半導體元件20可在相同技術節點的製程中形成，或者可在不同技術節點的製程中形成。舉例來說，半導體元件10a的半導體晶粒100可具有比半導體元件20先進的製程節點；反之亦然。
在一些實施例中，半導體元件10a的半導體晶粒100與半導體元件20具有不同的大小(例如，沿堆疊方向Z測量的不同高度和/或不同表面積)。舉例來說，如圖6中所示，半導體元件10a的半導體晶粒100的高度小於半導體元件20的高度，且半導體元件10a的高度大於半導體元件20的高度。然而，本公開並非僅限於此；對於另一實例，半導體元件10a的半導體晶粒100的高度小於半導體元件20的高度，且半導體元件10a的高度實質上 等於半導體元件20的高度。
在一些實施例中，如圖6中所示，半導體元件10a通過導通孔140及導電連接件360電連接到基底310，而半導體元件20通過導通孔22及導電連接件360電連接到基底310。在一些實施例中，半導體元件10a與半導體元件20通過重佈線路結構340及導電連接件360彼此電連通(electrical communicated)。
在一些實施例中，底部填充膠UF1至少填充半導體元件10a與重佈線路結構340之間的間隙以及半導體元件20與重佈線路結構340之間的間隙，且包繞導通孔140的側壁、導通孔22的側壁及導電連接件360的側壁。在一個實施例中，填充在半導體元件10a、20與重佈線路結構340之間的間隙中的底部填充膠UF1彼此不連接。在另一實施例中，填充在半導體元件10a、20與重佈線路結構340之間的間隙中的底部填充膠UF1彼此連接，本公開並非僅限於此。在一些替代實施例中，半導體元件10a的側壁及半導體元件20的側壁可被底部填充膠UF1覆蓋。舉例來說，底層填充膠UF1可為任何可接受的材料，例如聚合物、環氧樹脂、模塑底部填充膠等。在一個實施例中，底部填充膠UF1可通過底部填充膠分配(underfill dispensing)、毛細流動製程(capillary flow process)或任何其他合適的方法形成。
參照圖7，在一些實施例中，根據圖16的步驟S14，在基底310之上形成絕緣包封體400m。舉例來說，如圖7中所示，半導體元件10a、半導體元件20被包封在絕緣包封體400m中，且被底部填充膠UF1暴露出的重佈線路結構340被絕緣包封體400m覆蓋。舉例來說，絕緣包封體400m至少填充半導體元件10a、 半導體元件20之間的間隙以及分別位於半導體元件10a、20之下的底部填充膠UF1之間的間隙。如圖7中所示，例如，半導體元件10a、20及底部填充膠UF1被絕緣包封體400m環繞及覆蓋。也就是說，半導體元件10a、20及底部填充膠UF1嵌置在絕緣包封體400m中。換句話說，半導體元件10a、20不被絕緣包封體400m以可觸及的方式顯露出且嵌置在絕緣包封體400m中。
在一些實施例中，絕緣包封體400m是通過模塑製程形成的模塑化合物。在一些實施例中，絕緣包封體400m例如可包含聚合物(例如環氧樹脂、酚醛樹脂、含矽樹脂或其他合適的樹脂)、介電材料或其他合適的材料。在替代實施例中，絕緣包封體400m可包含可接受的絕緣包封體材料。在一些實施例中，絕緣包封體400m可還包含可被添加在絕緣包封體400m中以優化絕緣包封體400m的熱膨脹係數(coefficient of thermal expansion，CTE)的無機填料或無機化合物(例如二氧化矽、粘土等)。本公開並非僅限於此。
一起參照圖7與圖8，在一些實施例中，根據圖16的步驟S15，將絕緣包封體400m平坦化直到暴露出半導體元件10a的底表面(例如，基底層210的底表面210b)及半導體元件20的底表面20b。在將絕緣包封體400m平坦化之後，形成(經平坦化的)絕緣包封體400，且半導體元件10a的底表面(例如，基底層210的底表面210b)及半導體元件20的底表面20b被絕緣包封體400的表面400a暴露出。
在絕緣包封體400m的平坦化製程期間中，也可獨立將半導體元件10a、20平坦化。舉例來說，絕緣包封體400可通過機 械研磨或CMP形成。在平坦化製程之後，可視需要執行清潔步驟，例如清潔及移除平坦化步驟所產生的殘留物。然而，本公開並非僅限於此，且平坦化步驟可通過任何其他合適的方法來執行。如圖8中所示，半導體元件10a的底表面(例如基底層210的底表面210b)及半導體元件20的底表面20b與絕緣包封體400的表面400a實質上齊平。也就是說，半導體元件10a的底表面(例如基底層210的底表面210b)、半導體元件20的底表面20b及絕緣包封體400的表面400a實質上彼此共面(coplanar)。換句話說，半導體元件10a、20被絕緣包封體400以可觸及的方式顯露出。
參照圖9，在一些實施例中，在形成絕緣包封體400之後，將圖8中所繪示的結構翻轉(沿著堆疊方向Z顛倒)，且將絕緣包封體400放置在載體C1上。在一些替代實施例中，載體C1可還塗布有剝離層(未示出)。舉例來說，剝離層設置在載體C1上，且剝離層的材料可為適合用於將載體C1從設置在載體C1上的上方層(例如，絕緣包封體400)或任何晶圓進行接合及剝離的任何材料。在一些實施例中，剝離層可包括釋放層(例如光熱轉換(light-to-heat conversion，“LTHC”)層)或黏著層(例如紫外可固化黏著層(ultra-violet curable adhesive layer)或熱可固化黏著層(heat curable adhesive layer))。
參照圖10，在一些實施例中，根據圖16的步驟S16，然後將基底310平坦化直到暴露出嵌置在基底310中的穿孔320的底表面320b。在將基底310平坦化之後，穿孔320的底表面320b被基底310的表面310b暴露出。在基底310的平坦化製程期間，也可將穿孔320平坦化。舉例來說，可通過機械研磨或CMP來將 基底310平坦化。在平坦化製程之後，可視需要執行清潔步驟，例如清潔及移除平坦化步驟所產生的殘留物。然而，本公開並非僅限於此，且平坦化步驟可通過任何其他合適的方法來執行。如圖10中所示，穿孔320的底表面320b與基底310的表面310b實質上齊平且共面。也就是說，穿孔320的底表面320b被基底310以可觸及的方式暴露出。
參照圖11，在一些實施例中，根據圖16的步驟S17，在基底310上形成多個導電連接件380，其中導電連接件380連接到穿孔320。如圖11中所示，例如，導電連接件380對應於穿孔320的定位位置而形成在基底310上，且因此導電連接件380分別與穿孔320的底表面320b實體地接觸。在一些實施例中，通過穿孔320、重佈線路結構340及導電連接件360，導電連接件380中的一些導電連接件380電連接到半導體元件10a。在一些實施例中，通過穿孔320、重佈線路結構340及導電連接件360，導電連接件380中的一些導電連接件380電連接到半導體元件20。在替代實施例中，導電連接件380中的一些導電連接件380可還電連接到嵌置在基底310中或形成在基底310的表面310a上的主動元件及被動元件。導電連接件380的材料及形成與導電連接件360的材料及形成相同或相似，且因此本文中可不再重複。在一個實施例中，導電連接件380可與導電連接件360相同。在替代實施例中，導電連接件380可與導電連接件360不同。
參照圖12，在一些實施例中，將圖11中所繪示的整個結構連同載體C1翻轉(顛倒)且接著將載體C1從絕緣包封體400及半導體元件10a、20剝離。在一些實施例中，載體C1通過剝離 製程從絕緣包封體400及半導體元件10a、20分離(detached)，其中載體C1被移除，且絕緣包封體400及半導體元件10a、20被暴露出。如圖12中所示，絕緣包封體400的表面400a、半導體元件10a的底表面(例如底表面210b)及半導體元件20的底表面20b被暴露出。
在一個實施例中，剝離製程是雷射剝離製程。在剝離步驟期間，在對載體C1進行剝離之前，採用固持元件HD2來固定圖11中所繪示的整個結構，其中導電連接件380由固持元件HD2固持。如圖12中所示，例如，固持元件HD2可為黏著條帶、載體膜或吸力墊。
參照圖13，在一些實施例中，根據圖16的步驟S18，依序執行切分(或單體化)製程以將圖12中所繪示的整個結構切割成單獨且分開的多個封裝結構P1A。在一個實施例中，切分製程是晶圓切分製程，所述晶圓切分製程包括機械刀片鋸切或雷射切割。本公開並非僅限於此。至此，封裝結構P1A得以製造完成。另外，基底310與穿孔320一起被認為是中介體(interposer)。
參照圖13及圖14A，在一些實施例中，出於例示目的示出封裝結構P1A中所包括的一個半導體元件10a及兩個半導體元件20，然而本公開並非僅限於此。基於需要及設計佈局，半導體元件10a的數目及半導體元件20的數目可獨立地為一個或多於一個。如圖13及圖14A中所示，在被包封在絕緣包封體400中的每一半導體元件10a中，從半導體晶粒100產生的熱量能夠通過熱耦合到半導體晶粒100的散熱元件HDE而容易地發散到外部環境，從而有助於在封裝結構P1A內保持較低溫度。也就是說，基 於封裝結構P1A中所包括的每一半導體元件10a的散熱元件HDE，可通過對散熱元件HDE的材料進行調節來控制半導體元件10a的散熱效率，從而確保封裝結構P1A的可靠性。換句話說，由於散熱元件HDE的存在，可確保封裝結構P1A的整體熱特性(例如散熱、耐熱性)。
另外，對於圖14A中所示的封裝結構P1A，由於圖16的製造方法，散熱元件HDE的側壁(例如，基底層210的側壁及黏著層220的側壁)與位於散熱元件HDE之下的半導體晶粒100的側壁對齊。也就是說，在圖14A中所示的半導體元件10a中，散熱元件HDE的側壁與半導體晶粒100的側壁實質上彼此共面。
另一方面，在替代實施例中，可從散熱元件HDE省略黏著層220，參見圖14B中所繪示的封裝結構P1B。圖14B中所繪示的封裝結構P1B與圖14A中所繪示的封裝結構P1A相似，不同之處在于，封裝結構P1B包括半導體元件10b而不是半導體元件10a，其中半導體元件10b包括具有僅基底層210的散熱元件。也就是說，在圖14B中所示的半導體元件10b中，散熱元件HDE的側壁(例如，基底層210的側壁)與位於散熱元件HDE之下的半導體晶粒100的側壁對齊且實質上共面。
參照圖15，在一些實施例中，根據圖16的步驟S19，通過導電連接件380將封裝結構P1A接合在基底500上以形成(堆疊的)封裝結構P2A。基底500可由例如矽、鍺、金剛石等半導體材料製成。在一些實施例中，也可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些材料的組合等。在一些實施例中，基底500可為SOI基底， 其中SOI基底可包括半導體材料(例如磊晶矽、鍺、矽鍺、SOI、絕緣體上有矽鍺(silicon germanium on insulator，SGOI)或其組合)層。在替代實施例中，基底500可基於絕緣核心(insulating core)，例如玻璃纖維增強樹脂核心(fiberglass reinforced resin core)。一種示例性核心材料(core material)是玻璃纖維樹脂，例如阻燃劑級4(flame retardant class 4，FR4)。核心材料的替代物包括雙馬來醯亞胺三嗪(bismaleimide triazine，BT)樹脂，或者作為另外一種選擇，其他印刷電路板(printed circuit board，PCB)材料或膜。在再一替代實施例中，基底500可為構成膜(build-up film)，例如味之素構成膜(Ajinomoto build-up film，ABF)或其他合適的疊層。
在一個實施例中，基底500可包括可用於產生針對半導體封裝設計的結構及功能要求的主動元件和/或被動元件(未示出)，例如電晶體、電容器、電阻器、其組合等。主動元件和/或被動元件可使用任何合適的方法形成。然而，本公開並非僅限於此；在替代實施例中，基底500可實質上不包含主動元件和/或被動元件。
在一些實施例中，基底500包括彼此內連的多個金屬化層530及多個通孔(未示出)以及連接到金屬化層530及通孔的多個接合墊510、520。金屬化層530與通孔一起形成為基底500提供佈線的功能電路系統。嵌置在基底500中的金屬化層530及通孔可由交替的介電(例如低介電常數介電材料)層與導電材料(例如銅)層和內連導電材料層的通孔形成且可通過任何合適的製程(例如沉積、鑲嵌、雙鑲嵌等)形成。接合墊510、520是用於 為基底500提供與外部元件的電連接。在一些實施例中，接合墊510、520通過金屬化層530及通孔彼此電連接。如圖15中所示，例如，封裝結構P1A的導電連接件380分別連接到基底500的接合墊510。如圖15中所示，在一些實施例中，通過接合墊510及導電連接件380，封裝結構P1A電連接到基底500。
在一些實施例中，可視需要在基底500的底表面上設置多個導電元件560，如圖15中所示。在一些實施例中，可使用導電元件560將基底500實體地連接到及電連接到其他元件、封裝、連接元件等。在本公開中，導電元件560被稱為基底500的導電端子以提供與外部元件的實體連接和/或電連接。如圖15中所示，導電元件560及封裝結構P1A分別位於基底500的兩個相對的側上，其中導電元件560中的一些導電元件560通過接合墊510、520及導電連接件380電連接到封裝結構P1A。
在一些實施例中，可視需要將一個或多個表面元件540、550連接到基底500。表面元件540、550可例如用於向封裝結構P2A提供附加功能或程式化。在實施例中，表面元件540、550可包括期望連接到封裝結構P2A且與封裝結構P2A接合利用的表面安裝元件(surface mount device，SMD)或積體被動元件(integrated passive device，IPD)，所述積體被動元件包括被動元件，例如電阻器、電感器、電容器、跳線器(jumper)、這些元件的組合等。
舉例來說，如圖15中所示，表面元件540被放置在其中設置有封裝結構P1A的基底500的表面上，且表面元件550被放置在其中設置有導電元件560的基底500的表面上。表面元件540的數目及表面元件550的數目並非僅限於所述實施例，且可基於 需要及設計佈局來選擇。本公開並非僅限於此。在一個實施例中，僅表面元件540形成在基底500上，其中表面元件540的數目可為一個或多於一個。在替代實施例中，僅表面元件550形成在基底500上，其中表面元件550的數目可為一個或多於一個。如圖15中所示，表面元件540、550例如通過接合墊510、520、金屬化層530及通孔、以及導電連接件380電連接到封裝結構P1A。
在一些實施例中，在基底500上形成底部填充膠UF2。如圖15中所示，例如，底部填充膠UF2填充封裝結構P1A與基底500之間的間隙，且包繞導電連接件380的側壁。底部填充膠UF2的材料及形成可與圖6中所闡述的底部填充膠UF1的材料及形成相同或相似，且因此為了簡潔性起見本文中不再重複。
至此，封裝結構P2A得以製造完成。另外，基底500被認為是電路結構(例如，嵌置有電路系統結構的有機基底，例如印刷電路板(PCB))。然而，本公開並非僅限於此；在替代實施例中，圖15中所繪示的封裝結構P2A中所包括的封裝結構P1A可用圖14B中所繪示的封裝結構P1B代替。
參照圖17，在一些實施例中，提供散熱蓋600且將散熱蓋600接合到封裝結構P2A的基底500以形成封裝結構P3A。在一些實施例中，在封裝結構P3A中，除了散熱的功能之外，散熱蓋600可向封裝結構P2A中所包括的封裝結構P1A提供實體保護。散熱蓋600可具有高導熱率(例如，大於或處於約200W/m．K到約400W/m．K之間)，且可使用金屬、金屬合金等形成。在一些實施例中，使用例如黏著劑等接合元件620將散熱蓋600貼合到基底500，以使得封裝結構P1A佈置在由散熱蓋600及基底500 限定的內腔中。然而，本公開並非僅限於此；在替代實施例中，圖17所繪示的封裝結構P3A中所包括的封裝結構P1A可用圖14B中所繪示的封裝結構P1B代替。
在一些實施例中，在封裝結構P1A與散熱蓋600之間施加熱介面材料(thermal interface material)610，其中熱介面材料610熱耦合到封裝結構P1A的散熱元件HDE，這進一步有助於將熱量從封裝結構P1A發散到散熱蓋600，從而有助於在封裝結構P3A內保持較低溫度。熱介面材料610可包括任何合適的導熱材料，例如，具有大於或可處於約3W/m．K到約10W/m．K之間約3W/m．K之間的良好導熱率的聚合物。
圖18到圖19是根據本公開一些實施例的封裝結構的製造方法中的各個階段的示意性剖面圖。圖20是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖21A及圖21B是根據本公開一些實施例的封裝結構的示意性剖面圖。圖22是根據本公開一些實施例的封裝結構的示意性剖面圖。圖23是根據本公開一些實施例的封裝結構的示意性剖面圖。在一些實施例中，圖1到圖6中所闡述的製程可用圖18到圖19中所闡述的製程取代。與上述元件相似或實質上相同的元件將使用相同的參考編號，且相同元件的某些細節或說明(例如，形成及材料)及其關係(例如，相對定位配置及電連接)在本文中將不再重複。
參照圖18，在一些實施例中，根據圖20的步驟S20，提供至少一個半導體晶粒100及至少一個半導體元件20且將所述至少一個半導體晶粒100及所述至少一個半導體元件20接合到基底310(其中嵌置有多個穿孔320且在其上方設置有重佈線路結構 340及多個導電連接件360)。如圖18中所示，例如，半導體晶粒100通過實體地連接導通孔140與導電連接件360而接合到基底310，且半導體元件20通過實體地連接導通孔22與導電連接件360而接合到基底310。在一些實施例中，施加底部填充膠UF1來填充重佈線路結構340與半導體晶粒100之間的間隙以及重佈線路結構340與半導體元件20之間的間隙，從而進一步增強重佈線路結構340與半導體晶粒100之間的接合強度以及重佈線路結構340與半導體元件20之間的接合強度。在圖1到圖4中闡述了半導體晶粒100的細節，在圖6中闡述了半導體元件20的細節、基底310的細節及底部填充膠UF1的細節，且因此本文中不再重複。如圖18中所示，例如，當沿著堆疊方向Z測量時，第一半導體晶粒100的厚度小於第二半導體元件20的厚度。
參照圖19，在一些實施例中，根據圖20的步驟S21，提供散熱元件HDE且將散熱元件HDE接合到半導體晶粒100中的相應的一個半導體晶粒100來形成半導體元件10c。如圖19所示，例如，當沿著堆疊方向Z測量時，半導體元件10c的厚度大於第二半導體元件20的厚度。然而，本公開並非僅限於此；在替代實施例中，半導體元件10c的厚度實質上等於第二半導體元件20的厚度。在一些實施例中，對於圖19中所示的每一半導體元件10c，散熱元件HDE連接到位於其之下的半導體晶粒100，且散熱元件HDE與位於其之下的半導體晶粒100彼此熱耦合。如圖19中所示，散熱元件HDE包括基底層210及設置在基底層210上的黏著層220，其中黏著層220夾置在散熱元件HDE的基底層210與半導體晶粒100之間。然後，對圖19中所繪示的結構執行如上方先 前在圖7到圖13中所闡述的製造製程以獲得圖21A中所繪示的封裝結構P1C，先前所闡述的製造製程也在圖20中的製造方法的步驟S22到步驟S27中示出。由於散熱元件HDE，從半導體晶粒100產生的熱量能夠通過散熱元件HDE而容易地發散到外部環境，從而有助於在封裝結構P1C內保持較低溫度。
也就是說，基於封裝結構P1C中所包括的每一半導體元件10c的散熱元件HDE，可通過對散熱元件HDE的材料進行調節來控制半導體元件10c的散熱效率，從而確保封裝結構P1C的可靠性。換句話說，由於散熱元件HDE的存在，可確保封裝結構P1C的整體熱特性(例如，散熱、耐熱性)。
在一些實施例中，由於圖20的製造方法，對於圖21A中繪示的每一半導體元件10c，散熱元件HDE的側壁(例如，基底層210的側壁及黏著層220的側壁)可不與位於散熱元件HDE之下的半導體晶粒100的側壁對齊，而基底層210的側壁也可不與黏著層220的側壁對齊。也就是說，在圖21A中，例如，在散熱元件HDE內，基底層210的側壁與黏著層220的側壁之間存在偏移D1；且在半導體元件10c內，黏著層220的側壁與半導體晶粒100的側壁之間存在偏移D2。在一些實施例中，偏移D1與偏移D2獨立地介於從5微米到5000微米的範圍內。
然而，本公開並非僅限於此。在一個實施例中，散熱元件HDE的側壁(例如，基底層210的側壁及黏著層220的側壁)可不與位於散熱元件HDE之下的半導體晶粒100的側壁對齊，而基底層210的側壁可與黏著層220的側壁對齊。或者，在另一實施例中，散熱元件HDE的側壁可與位於散熱元件HDE之下的半導 體晶粒100的側壁局部地對齊(例如，基底層210的側壁及黏著層220的側壁中的一者可與位於其之下的半導體晶粒100的側壁局部地對齊)，而基底層210的側壁可不與黏著層220的側壁對齊。或者，在再一實施例中，與半導體元件10a相同，散熱元件HDE的側壁(例如，基底層210的側壁及黏著層220的側壁)可與位於散熱元件HDE之下的半導體晶粒100的側壁對齊，而基底層210的側壁可與黏著層220的側壁對齊。
另一方面，在封裝結構P1C的替代實施例中，可從散熱元件HDE省略黏著層220，參見圖21B中所繪示的封裝結構P1D。在一些實施例中，封裝結構P1D包括半導體元件10d而不是半導體元件10c，其中封裝結構P1D中的半導體元件10d包括具有僅基底層210的散熱元件HDE。在一些實施例中，由於圖20的製造方法，對於圖21B中所繪示的每一半導體元件10d，散熱元件HDE的側壁(例如，基底層210的側壁)可不與位於散熱元件HDE之下的半導體晶粒100的側壁對齊。也就是說，在圖21B中，例如，在半導體元件10d內在基底層210的側壁與半導體晶粒100的側壁之間存在偏移D3。在一些實施例中，偏移D3介於從5微米到5000微米的範圍內。或者，在一個實施例中，與半導體元件10b相同，散熱元件HDE的側壁(例如，基底層210的側壁)可與位於散熱元件HDE之下的半導體晶粒100的側壁對齊。
另外，可對圖21A中所繪示的結構執行如上方先前在圖15中所闡述的製造製程以獲得圖22中所繪示的(堆疊的)封裝結構P2C，且可對圖22中所繪示的結構執行如上方先前在圖17中所闡述的製造製程以獲得圖23中所繪示的(堆疊的)封裝結構 P3C。然而，本公開並非僅限於此；在替代實施例中，圖22中所繪示的封裝結構P2C中所包括的封裝結構P1C或圖23中所繪示的封裝結構P3C中所包括的封裝結構P1C可用圖21B中所繪示的封裝結構P1D代替。
圖24到圖33A是根據本公開一些實施例的封裝結構的製造方法中的各個階段的示意性剖面圖。圖33B是根據本公開一些實施例的封裝結構的示意性剖面圖。圖34是根據本公開一些實施例的封裝結構的示意性剖面圖。圖35是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。與上述元件相似或實質上相同的元件將使用相同的參考編號，且相同元件的某些細節或說明(例如，形成及材料)及其關係(例如，相對定位配置及電連接)在本文中將不再重複。
參照圖24，在一些實施例中，在圖18中闡述的製程(根據圖35的步驟S30)之後，在半導體晶粒100中的每一者上依序形成虛設元件DE(根據圖35的步驟S31)。虛設元件DE可包括由玻璃、聚合物或化合物製成的可移除層，且可通過粘合或任何其他合適的技術形成在半導體晶粒100上。本公開並非僅限於此。如圖24中所示，例如，當沿著堆疊方向Z測量時，具有相應的一個虛設元件DE的每一半導體晶粒的厚度大於第二半導體元件20的厚度。然而，本公開並非僅限於此；在替代實施例中，具有相應的一個虛設元件DE的每一半導體晶粒的厚度實質上等於第二半導體元件20的厚度。
參照圖25，在一些實施例中，根據圖35的步驟S32，在基底310之上形成絕緣包封體400m。在圖7的製程中已闡述了絕 緣包封體400m的形成及材料，且因此本文中不再重複。如圖25中所示，例如，上面設置有虛設元件DE的半導體晶粒100、半導體元件20及底部填充膠UF1被絕緣包封體400m環繞及覆蓋。也就是說，上面設置有虛設元件DE的半導體晶粒100、半導體元件20及底部填充膠UF1嵌置在絕緣包封體400m中。換句話說，上面設置有虛設元件DE的半導體晶粒100、半導體元件20及底部填充膠UF1不被絕緣包封體400m以可觸及的方式顯露出且嵌置在絕緣包封體400m中。
參照圖25及圖26，在一些實施例中，根據圖35的步驟S33，將絕緣包封體400m平坦化直到暴露出設置在半導體晶粒100上的虛設元件DE的底表面S1及半導體元件20的底表面20b。在將絕緣包封體400m平坦化之後，形成(經平坦化的)絕緣包封體400，且虛設元件DE的底表面S1及半導體元件20的底表面20b被絕緣包封體400的表面400a暴露出。在圖8的製程中已闡述了絕緣包封體400的形成，且因此本文中不再重複。
參照圖27，在一些實施例中，在形成絕緣包封體400之後，將圖26中所繪示的結構翻轉(沿著堆疊方向Z顛倒)，且將絕緣包封體400放置在載體C1上。在圖9的製程中已闡述了載體C1的材料，且因此本文中不再重複。
參照圖28，在一些實施例中，根據圖35的步驟S34，接著將基底310平坦化直到暴露出嵌置在基底310中的穿孔320的底表面320b。在圖10的製程中已闡述了圖案化製程的細節，且因此本文中不再重複。如圖28中所示，穿孔320的底表面320b與基底310的表面310b實質上齊平且共面。也就是說，穿孔320的 底表面320b被基底310以可觸及的方式暴露出。
參照圖29，在一些實施例中，根據圖35的步驟S35，在基底310上形成多個導電連接件380，其中導電連接件380連接到穿孔320。在圖29的製程中已闡述了導電連接件380的形成及材料，且因此本文中不再重複。在一些實施例中，通過穿孔320、重佈線路結構340及導電連接件360，導電連接件380中的一些導電連接件380電連接到半導體晶粒100。在一些實施例中，通過穿孔320、重佈線路結構340及導電連接件360，導電連接件380中的一些導電連接件380電連接到半導體元件20。在替代實施例中，導電連接件380中的一些導電連接件380可還電連接到嵌置在基底310中或形成在基底310的表面310a上的主動元件及被動元件。
參照圖30，在一些實施例中，將圖29中所繪示的整個結構連同載體C1翻轉(顛倒)且放置到固持元件HD2上，且然後將載體C1從絕緣包封體400、虛設元件DE及半導體元件20剝離。在一些實施例中，載體C1通過剝離製程與絕緣包封體400、虛設元件DE及半導體元件20分離，其中載體C1被移除，且絕緣包封體400、虛設元件DE及半導體元件20被暴露出。如圖30中所示，絕緣包封體400的表面400a、虛設元件DE的底表面S1及半導體元件20的底表面20b被暴露出。在圖12的製程中已闡述了剝離製程的細節及固持元件HD2的材料，且因此本文中不再重複。
參照圖31，在一些實施例中，根據圖35的步驟S36，依序執行切分(或單體化)製程以將圖30中所繪示的整個結構切割 成上面設置有虛設元件DE的單獨且分開的多個結構。在一個實施例中，切分製程是晶圓切分製程，所述晶圓切分製程包括機械刀片鋸切或雷射切割。本公開並非僅限於此。另外，基底310與穿孔320一起被認為是中介體。
參照圖32，在一些實施例中，根據圖35的步驟S37，通過多個導電連接件380將上面設置有虛設元件DE的結構接合在基底500(包括多個接合墊510、520、彼此內連的多個金屬化層530及多個通孔、多個表面元件540、550以及多個導電元件560)上。在圖15的製程中已闡述了接合製程的細節以及基底500(包括接合墊510、520、彼此內連的金屬化層530及通孔、表面元件540、550以及導電元件560)的形成及材料，且因此本文中不再重複。在一些實施例中，在基底500上形成底部填充膠UF2。如圖32中所示，例如，底部填充膠UF2填充上面設置有虛設元件DE的結構與基底500之間的間隙，且包繞導電連接件380的側壁。底部填充膠UF2的材料及形成可與圖6中所闡述的底部填充膠UF1的材料及形成相同或相似，且因此為了簡潔性起見本文中不再重複。另外，基底500被認為是電路結構(例如，嵌置有電路系統結構的有機基底，例如印刷電路板(PCB))。
參照圖33A，在一些實施例中，根據圖35的步驟S38，移除虛設元件DE，且然後在半導體晶粒100上設置散熱元件HDE以形成具有封裝結構P1E的(堆疊的)封裝結構P2E，封裝結構P1E包括設置在基底500上的半導體元件10e。舉例來說，虛設元件DE的移除可通過蝕刻、紫外去黏著(UV de-adhesion)或熱去黏著來執行，本公開並非僅限於此。在一些實施例中，從圖32中 所繪示的結構移除虛設元件DE以在半導體晶粒100上方形成凹槽R，且接著在凹槽R中設置散熱元件HDE以與半導體晶粒100及絕緣包封體400實體地接觸。換句話說，凹槽R由半導體晶粒100及絕緣包封體400限定。在一些實施例中，半導體元件10e包括散熱元件HDE及位於散熱元件HDE之下的半導體晶粒100，其中散熱元件HDE與半導體晶粒100熱耦合。舉例來說，如圖33A中所示，散熱元件HDE包括基底層210及設置在基底層210上的黏著層220，其中黏著層220夾置在半導體元件10e的半導體晶粒100與基底層210之間。在圖1中已闡述了散熱元件HDE中所包括的基底層210的材料及黏著層220的材料，且在圖1到圖5中已闡述了半導體晶粒100的細節，且因此本文中不再重複。如圖33A中所示，在被包封在絕緣包封體400中的每一半導體元件10e中，從半導體晶粒100產生的熱量能夠通過散熱元件HDE而容易地發散到外部環境，從而有助於在封裝結構P1E內保持較低溫度。也就是說，基於封裝結構P1E中所包括的每一半導體元件10e的散熱元件HDE，可通過對散熱元件HDE的材料進行調節來控制半導體元件10e的散熱效率，從而確保封裝結構P1E的可靠性。換句話說，由於散熱元件HDE的存在，可確保封裝結構P1E的整體熱特性(例如，散熱、耐熱性)。
由於圖35的製造方法，在剖面圖中，封裝結構P2E中的封裝結構P1E所包括的半導體元件10e的輪廓可與圖14A中所繪示的半導體元件10a或圖21A中所繪示的半導體元件10c的輪廓相同。舉例來說，如圖33A中所示，與半導體元件10a相同，基底層210的側壁及黏著層220的側壁與半導體晶粒100的側壁對 齊且實質上共面。然而，本公開並非僅限於此。在一些實施例中，與半導體元件10c相同，散熱元件HDE的側壁(例如，基底層210的側壁及黏著層220的側壁)可不與位於散熱元件HDE之下的半導體晶粒100的側壁對齊，而基底層210的側壁也可不與黏著層220的側壁對齊。也就是說，例如，在散熱元件HDE內，基底層210的側壁與黏著層220的側壁之間可存在介於從5微米到5000微米的範圍內的偏移；且在半導體元件10e內，黏著層220的側壁與半導體晶粒100的側壁之間可存在介於從5微米到5000微米的範圍內的另一偏移。在一些實施例中，散熱元件HDE的側壁(例如，基底層210的側壁及黏著層220的側壁)可不與位於散熱元件HDE之下的半導體晶粒100的側壁對齊，而基底層210的側壁可與黏著層220的側壁對齊。或者，在另一實施例中，散熱元件HDE的側壁可與位於散熱元件HDE之下的半導體晶粒100的側壁局部地對齊(例如，基底層210的側壁及黏著層220的側壁中的一者可與半導體晶粒100的側壁對齊)，而基底層210的側壁可不與黏著層220的側壁對齊。
另一方面，在封裝結構P1E的替代實施例中，可從散熱元件HDE省略黏著層220，參見圖33B中所繪示的(堆疊的)封裝結構P2F中所包括的封裝結構P1F。在一些實施例中，封裝結構P1F包括半導體元件10f而不是半導體元件10e，其中封裝結構P1F的半導體元件10f包括具有僅基底層210的散熱元件HDE。在一些實施例中，由於圖35的製造方法，對於圖33B中所繪示的每一半導體元件10f，在剖面圖中，封裝結構P2F的封裝結構P1F中包括的半導體元件10f的輪廓可與圖14B中所繪示的半導體元 件10b或圖21B中所繪示的半導體元件10d的輪廓相同。舉例來說，如圖33B所示，與半導體元件10b相同，基底層210的側壁可與位於基底層210之下的半導體晶粒100的側壁對齊。然而，本公開並非僅限於此。在一些實施例中，與半導體元件10d相同，基底層210的側壁可不與位於基底層210之下的半導體晶粒100的側壁對齊。也就是說，例如，在半導體元件10f內在基底層210的側壁與半導體晶粒100的側壁之間可存在介於從5微米到5000微米的範圍內的偏移。
參照圖34，在一些實施例中，提供散熱蓋600以及熱介面材料610且將散熱蓋600以及熱介面材料610接合到封裝結構P2E的基底500以形成封裝結構P3E。在圖17中已闡述了散熱蓋600及熱介面材料610的材料及形成，且因此為了簡潔性起見本文中不再重複。在一些實施例中，熱介面材料610位於封裝結構P1E與散熱蓋600之間，其中熱介面材料610熱耦合到封裝結構P1E的半導體元件10e中所包括的散熱元件HDE，這進一步有助於將熱量從封裝結構P1E發散到散熱蓋600，從而有助於在封裝結構P3E內保持較低溫度。然而，本公開並非僅限於此；在替代實施例中，圖34中所繪示的封裝結構P3E中所包括的封裝結構P2E可用圖33B中所繪示的封裝結構P2F代替。
圖36是根據本公開一些實施例的封裝結構的示意性剖面圖。圖37是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖38是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖39是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖40是根據本公開一些實施例的封裝結構的示 意性剖面圖。與上述元件相似或實質上相同的元件將使用相同的參考編號，且相同元件的某些細節或說明(例如，形成及材料)及其關係(例如，相對定位配置及電連接)在本文中將不再重複。
參照圖36，在一些實施例中，封裝結構P4A包括半導體元件10a、半導體元件30、絕緣包封體700、重佈線路結構800及多個導電端子900。在一些實施例中，半導體元件10a及半導體元件30被包封在絕緣包封體700中，其中半導體元件10a的表面S2及半導體元件30的表面S3被絕緣包封體700的表面700b暴露出。在一些實施例中，重佈線路結構800位於絕緣包封體700的表面700a上，其中表面700a沿重佈線路結構800與絕緣包封體700的堆疊方向Z與表面700b相對。如圖36中所示，例如，重佈線路結構800電連接到半導體元件10a及半導體元件30。在本公開中，重佈線路結構800向半導體元件10a、30提供佈線功能。在一些實施例中，導電端子900位於重佈線路結構800上且連接到重佈線路結構800，其中重佈線路結構800位於絕緣包封體700與導電端子900之間。如圖36中所示，導電端子900中的一些導電端子900電連接到半導體元件10a，導電端子900中的一些導電端子900電連接到半導體元件30。
在圖1到圖5中已闡述了半導體元件10a的形成及材料，且因此本文中不再重複。如圖36中所示，半導體元件10a包括第一半導體晶粒100及設置在第一半導體晶粒100上的散熱元件HDE，其中散熱元件HDE熱耦合到第一半導體晶粒100。由於散熱元件HDE，從半導體晶粒100產生的熱量能夠通過散熱元件HDE而容易地發散到外部環境，從而有助於在封裝結構P4A內保 持較低溫度。也就是說，基於封裝結構P4A中所包括的半導體元件10a的散熱元件HDE，可通過對散熱元件HDE的材料進行調節來控制半導體元件10a的散熱效率，從而確保封裝結構P4A的可靠性。換句話說，由於散熱元件HDE的存在，可確保封裝結構P4A的整體熱特性(例如散熱、耐熱性)。然而，本公開並非僅限於此；在替代實施例中，半導體元件10a可用圖21A所繪示的半導體元件10c或圖33A中所繪示的半導體元件10e來代替；或者，半導體元件10a可由圖14B中所繪示的半導體元件10b(參見圖40中所示的封裝P4B)、圖21B中所繪示的半導體元件10d或圖33B中所繪示的半導體元件10f代替。
在一些實施例中，半導體元件30包括具有主動表面31a的半導體基底31、形成在主動表面31a上的內連結構32以及電連接到內連結構32的多個導通孔33。在一些實施例中，半導體基底31可為矽基底，所述矽基底包括形成在其中的主動元件(例如電晶體等)和/或被動元件(例如電阻器、電容器、電感器等)。本公開並非僅限於此。在一個實施例中，半導體基底31的形成及材料可與半導體基底110的形成及材料相同；然而，本公開並非僅限於此。
在一些實施例中，內連結構32包括交替地堆疊的一個或多個層間介電層32a與一個或多個圖案化導電層32b。在某些實施例中，圖案化導電層32b夾置在層間介電層32a之間，其中圖案化導電層32b的最頂層的頂表面的部分被層間介電層32a的最頂層暴露出且實體地連接到導通孔33，且圖案化導電層32b的最底層的一些部分被層間介電層32a的最底層暴露出且電連接到半導 體基底31中所形成的主動元件和/或被動組件(未示出)。如圖36中所示，層間介電層32a的最底層位於半導體基底31的主動表面31a上，且層間介電層32a的最頂層至少局部地與導通孔33接觸。層間介電層32a的數目及圖案化導電層32b的數目可基於需要來選擇，且在本公開中不受限制。層間介電層32a的數目及圖案化導電層32b的數目可小於或大於圖36中所繪示的數目，且可基於需要和/或設計佈局來指定；本公開並非僅限於此。在一個實施例中，層間介電層32a的形成及材料可與圖1中所闡述的層間介電層122的形成及材料相同或相似，且圖案化導電層32b的形成及材料可與圖1中所闡述的圖案化導電層124的形成及材料相同或相似，且因此本文中不再重複。在本公開中，導通孔33用作半導體元件30的導電端子以電連接到外部元件。在一些實施例中，儘管出於例示目的，圖36中呈現出僅四個導通孔33，但應理解，導通孔33的數目可基於需要及設計佈局來選擇或指定；本公開並非僅限於此。在一個實施例中，導通孔33的形成及材料可與圖1中所闡述的導通孔140的形成及材料相同，且因此本文中不再重複。如圖36中所示，導通孔33實體地連接到及電連接到內連電路結構32。在一些實施例中，半導體元件10a的導通孔140的表面及半導體元件30的導通孔33的表面與絕緣包封體700的表面700a實質上齊平且實質上共面，其中半導體元件10a的導通孔140的表面及半導體元件30的導通孔33的表面被絕緣包封體700暴露出且與重佈線路結構800接觸。
在一些實施例中，本文中所闡述的半導體元件30可被稱為半導體晶片或積體電路(IC)。在一個實施例中，半導體元件30 可與半導體晶粒100相同或相似。在替代實施例中，半導體元件30可與半導體晶粒100不同。在再一個實施例中，半導體元件30可與半導體元件20相同或相似。在再一替代實施例中，半導體元件30可與半導體元件20不同。
在一些實施例中，如圖36中所示，重佈線路結構800包括交替地堆疊的多個介電層802與多個金屬化層804，金屬化層804夾置在介電層802之間，其中金屬化層804的最頂層的頂表面至少局部地被形成在介電層802的最頂層中的多個開口(未標記)暴露出以連接到稍後形成的元件以進行電連接，且金屬化層804的最低層的底表面至少局部地被形成在介電層802的最低層中的多個開口(未標記)暴露出且通過導通孔140電連接到半導體元件10a，且通過導通孔33電連接到半導體元件30。金屬化層804的數目及介電層802的數目在本公開中不受限制，且可基於需要和/或設計佈局來指定。也就是說，被絕緣包封體700暴露出的半導體元件10a的導通孔140的表面及半導體元件30的導通孔33的表面與被介電層802的最底層暴露出的金屬化層804的最底層實體地接觸。在一些實施例中，被絕緣包封體700暴露出的半導體元件10a的導通孔140的表面及半導體元件30的導通孔33的表面被介電層802的最底層局部地覆蓋。
繼續圖36，在一些實施例中，封裝結構P4A可還包括多個球下金屬(under-ball metallurgy，UBM)圖案u1，其中UBM圖案u1可設置在金屬化層804的最頂層的被暴露的頂表面上以與多個導電元件(例如，導電球或導電凸塊，例如導電端子900)電連接。如圖36中所示，例如，UBM圖案u1形成在重佈線路結構800 上且電連接到重佈線路結構800。舉例來說，UBM圖案u1的材料可包括銅、鎳、鈦、鎢或其合金等，且可通過電鍍製程形成。UBM圖案u1的數目在本公開中不受限制，且與金屬化層804的最頂層的頂表面的被介電層802的最頂層暴露出的部分的數目對應。在一些實施例中，導電端子900通過UBM圖案u1電連接到重佈線路結構800。在一些實施例中，導電端子900可通過植球製程(ball placement process)或回焊製程(reflow process)設置在UBM圖案u1上。在一些實施例中，導電端子900是例如焊料球或球柵陣列(ball grid array，BGA)球。導電端子900的數目並不僅限於本公開，且可基於UBM圖案u1的數目來指定及選擇。
在一個實施例中，可通過圖37的方法來製造封裝結構P4A。應理解，在圖37的方法的所示動作之前、期間及之後可發生附加處理(additional treatment)以完成封裝結構P4A的形成。圖37的方法包括至少步驟S40到步驟S46。舉例來說，圖37中所示的方法從步驟S40開始，步驟S40提供包括多個第一半導體晶粒的晶圓；步驟S41，將包括所述多個第一半導體晶粒的晶圓接合到包括多個散熱元件的晶圓；步驟S42，對接合結構進行切分以形成各自具有一個第一半導體晶粒及設置在所述一個第一半導體晶粒上的一個相應的散熱元件的多個單獨且分開的第一半導體元件，其中第一半導體晶粒熱耦合到相應的一個散熱元件；步驟S43，將所述多個第一半導體元件中的至少一者以及至少一個第二半導體元件包封在絕緣包封體中；步驟S44，將絕緣包封體平坦化，以使絕緣包封體的第一表面暴露出第一半導體元件中所包括的散熱元件；步驟S45，在絕緣包封體的第二表面上形成電連接到第一半 導體元件及第二半導體元件的重佈線路結構，其中第一表面與第二表面相對；以及步驟S46，在重佈線路結構上設置多個導電端子，導電端子通過重佈線路結構電連接到第一半導體元件及第二半導體元件，其中重佈線路結構夾置在導電端子與絕緣包封體之間。然而，本公開並非僅限於此。
在替代實施例中，可通過圖38的方法來製造封裝結構P4A。應理解，在圖38的方法的所示動作之前、期間及之後可發生附加處理以完成封裝結構P4A的形成。圖38的方法包括至少步驟S50到步驟S55。舉例來說，圖38中所示的方法從步驟S50開始，步驟S50提供至少一個第一半導體晶粒及至少一個第二半導體元件，其中第一半導體晶粒的厚度小於第二半導體元件的厚度；步驟S51，在第一半導體晶粒上設置散熱元件以形成第一半導體元件，其中散熱元件實體地連接到第一半導體晶粒，且散熱元件熱耦合到第一半導體晶粒；步驟S52，將第一半導體元件及第二半導體元件包封在絕緣包封體中；步驟S53，將絕緣包封體平坦化，以使絕緣包封體的第一表面暴露出第一半導體元件中所包括的散熱元件；步驟S54，在絕緣包封體的第二表面上形成電連接到第一半導體元件及第二半導體元件的重佈線路結構，其中第一表面與第二表面相對；以及步驟S55，在重佈線路結構上設置多個導電端子，導電端子通過重佈線路結構電連接到第一半導體元件及第二半導體元件，其中重佈線路結構夾置在導電端子與絕緣包封體之間。然而，本公開並非僅限於此。
在一些替代實施例中，可通過圖39的方法來製造封裝結構P4A。應理解，在圖39的方法的所示動作之前、期間及之後可 發生附加處理以完成封裝結構P4A的形成。圖39的方法包括至少步驟S60到步驟S66。舉例來說，圖39中所示的方法從步驟S60開始，步驟S60提供至少一個第一半導體晶粒及至少一個第二半導體元件，其中第一半導體晶粒的厚度小於第二半導體元件的厚度；步驟S61，在第一半導體晶粒上設置虛設元件；步驟S62，將上面設置有虛設元件的第一半導體晶粒及第二半導體元件包封在絕緣包封體中；步驟S63，將絕緣包封體平坦化，以使絕緣包封體的第一表面暴露出虛設元件；步驟S64，在絕緣包封體的第二表面上形成電連接到第一半導體晶粒及第二半導體元件的重佈線路結構，其中第一表面與第二表面相對；步驟S65，在重佈線路結構上設置多個導電端子，導電端子通過重佈線路結構電連接到第一半導體晶粒及第二半導體元件，其中重佈線路結構夾置在導電端子與絕緣包封體之間；以及步驟S66，從第一半導體晶粒移除虛設元件且在第一半導體晶粒上直接設置散熱元件以形成第一半導體元件，其中散熱元件實體地連接到第一半導體晶粒，且散熱元件熱耦合到第一半導體晶粒。
在一些實施例中，圖36中所示的半導體元件10a的數目及半導體元件30的數目和/或圖40中所示的半導體元件10b的數目及半導體元件30的數目並非僅限於此，且可為一個或多於一個。另外，以上半導體元件30也可用圖6中所闡述的半導體元件20代替。圖41是根據本公開一些實施例的封裝結構的示意性剖面圖。圖42是根據本公開一些實施例的封裝結構的示意性剖面圖。圖43是根據本公開一些實施例的封裝結構的示意性剖面圖。圖44是根據本公開一些實施例的封裝結構的示意性剖面圖。與上述元件相 似或實質上相同的元件將使用相同的參考編號，且相同元件的某些細節或說明(例如，形成及材料)及其關係(例如，相對定位配置及電連接)在本文中將不再重複。
一起參照圖36與圖41，圖36中所繪示的封裝結構P4A與圖41中所繪示的封裝結構P5A相似；不同之處在於，對於圖41中所繪示的半導體封裝P5A，以兩個半導體元件20代替一個半導體元件30。一起參照圖40與圖42，圖40中所繪示的封裝結構P4B與圖42中所繪示的封裝結構P5B相似；不同之處在於，對於圖42中所繪示的半導體封裝P5B，以兩個半導體元件20代替一個半導體元件30。
一起參照圖36與圖43，圖36中所繪示的封裝結構P4A與圖43中所繪示的封裝結構P6A相似；不同之處在於，對於圖43中所繪示的半導體封裝P6A，以兩個半導體元件10a代替一個半導體元件10a，且以一個半導體元件20代替一個半導體元件30。一起參照圖40與圖44，圖40中所繪示的封裝結構P4B與圖44中所繪示的封裝結構P6B相似；不同之處在於，對於圖44中所繪示的半導體封裝P6B，以兩個半導體元件10b代替一個半導體元件10b，且以一個半導體元件20代替一個半導體元件30。
然而，本公開並非僅限於此。在替代實施例中，可以圖21A中所繪示的半導體元件10c或圖33A中所繪示的半導體元件10e獨立地代替圖41及圖43中所繪示的半導體元件10a，且圖42及圖44中所繪示的半導體元件10b可獨立地被圖21B中所繪示的半導體元件10d或圖33B中所繪示的半導體元件10f代替。
圖45是根據本公開一些實施例的封裝結構的示意性剖面 圖。圖46是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖47是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖48是示出根據本公開一些實施例的製造封裝結構的方法的流程圖。圖49是根據本公開一些實施例的封裝結構的示意性剖面圖。一起參照圖36與圖45，圖36中所繪示的封裝結構P4A與圖45中所繪示的封裝結構P7A相似；以使得與上述元件相似或實質上相同的元件將使用相同的參考編號，且相同元件的某些細節或說明(例如，形成及材料)及其關係(例如，相對定位配置及電連接)在本文中將不再重複。
一起參照圖36與圖45，不同之處在於，對於圖45中所繪示的封裝結構P7A，還包括附加元件(例如，介電層PM1、多個導通孔CP1、多個導通孔CP2、絕緣包封體702及橋接元件(bridge element)BE)，其中橋接元件BE被包封在絕緣包封體702中且設置在重佈線路結構800與絕緣包封體700之間，且橋接元件BE通過導通孔CP2電連接到半導體元件10a及半導體元件30。也就是說，例如，半導體元件10a與半導體元件30通過橋接元件BE電連通。
在一些實施例中，如圖45中所示，介電層PM1形成在絕緣包封體700上且實體地接觸絕緣包封體700，其中介電層PM1具有多個開口(未標記)，所述多個開口暴露出半導體元件30的導通孔33的表面及半導體元件10a的導通孔140的表面。介電層PM1的材料可包括可使用顯影和/或蝕刻製程圖案化的聚醯亞胺、PBO、苯並環丁烯(benzocyclobutene，BCB)、氮化物(例如氮化矽)、氧化物(例如氧化矽)、磷矽酸鹽玻璃(phosphosilicate glass， PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、其組合等。在一些實施例中，導通孔CP1及導通孔CP2形成在介電層PM1上且通過介電層PM1的開口連接到導通孔33及導通孔140。導通孔CP1及導通孔CP2的材料及形成與圖4中所闡述的導通孔140的材料及形成相同或相似，因此本文中可不再重複。
在一些實施例中，橋接元件BE設置在導通孔CP2上且被導通孔CP1環繞。在一些實施例中，當在堆疊方向Z上測量時，橋接元件BE的高度小於導通孔CP1的高度。如圖45中所示，橋接元件BE在重佈線路結構800與絕緣包封體700的堆疊方向Z上與半導體元件10a及半導體元件30交疊，且在重佈線路結構800上的垂直投影中從半導體元件10a延伸到半導體元件30(或者說，從半導體元件30延伸到半導體元件10a)。由於所述配置，半導體元件10a與半導體元件30之間的短的電性路徑(short electrical path)得以實現，從而降低了其訊號損耗。
在一些實施例中，導通孔CP1、導通孔CP2及橋接元件BE被包封在絕緣包封體702中，且被導通孔CP1及導通孔CP2暴露出的介電層PM1被絕緣包封體702覆蓋。如圖45中所示，橋接元件BE的表面、導通孔CP1的表面及絕緣包封體142的表面702a實質上彼此齊平且實質上彼此共面。在一些實施例中，重佈線路結構800位於橋接元件BE、導通孔CP1及絕緣包封體702(在表面702a處)上，且實體地連接到以及電連接到導通孔CP1。絕緣包封體702的材料及形成與圖36中所闡述的絕緣包封體700的材料及形成相同或相似，因此本文中可不再重複。也就是說，例 如，重佈線路結構800通過導通孔CP1、導通孔33及導通孔140電連接到半導體元件10a及半導體元件30。
在一些實施例中，橋接元件BE包括基底41、設置在基底41上的重佈線路結構42(其中佈置有介電結構42a及一個或多個金屬化層42b)以及嵌置到基底41且電連接到重佈線路結構42的多個穿孔43。基底41的形成及材料與基底310的形成及材料相同或相似，重佈線路結構42的形成及材料與重佈線路結構340的形成及材料相同或相似，且穿孔43的形成及材料與穿孔320的形成及材料相同或相似，且因此為了簡潔性起見本文中不再重複。
如圖45中所示，橋接元件BE通過導通孔33、140、CP2及重佈線路結構42電連接到半導體元件10a及半導體元件30。換句話說，半導體元件10a與半導體元件30通過橋接元件BE彼此電連通。在一些實施例中，如圖45中所示，橋接元件BE的穿孔43實體地連接到以及電連接到重佈線路結構800的金屬化層804的最底層。也就是說，例如，重佈線路結構800可還通過橋接元件BE、導通孔CP2、導通孔33及導通孔140電連接到半導體元件10a及半導體元件30。在一些實施例中，導電元件900中的一些導電元件900通過UBM圖案u1中的一些UBM圖案u1、重佈線路結構800及導通孔CP1中的一些導通孔CP1或者通過UBM圖案u1中的一些UBM圖案u1、重佈線路結構800、橋接元件BE及導通孔CP2中的一些導通孔CP2電連接到半導體元件10a，且導電元件900中的一些導電元件900通過UBM圖案u1中的一些UBM圖案u1、重佈線路結構800及導通孔CP1中的一些導通孔CP1或者通過UBM圖案u1中的一些UBM圖案u1、重佈線路結 構800、橋接元件BE及導通孔CP2中的一些導通孔CP2電連接到半導體元件30。
在一個實施例中，可通過圖46的方法來製造封裝結構P7A。應理解，在圖46的方法的所示動作之前、期間及之後可發生附加處理以完成封裝結構P7A的形成。圖46的方法包括至少步驟S70到步驟S79。舉例來說，圖46中所示的方法從步驟S70開始，步驟S70提供包括多個第一半導體晶粒的晶圓；步驟S71，將包括所述多個第一半導體晶粒的晶圓接合到包括多個散熱元件的晶圓；步驟S72，對接合結構進行切分以形成各自具有一個第一半導體晶粒及設置在所述一個第一半導體晶粒上的一個相應的散熱元件的多個單獨且分開的第一半導體元件，其中第一半導體晶粒熱耦合到相應的一個散熱元件；步驟S73，將所述多個第一半導體元件中的至少一者及至少一個第二半導體元件包封在絕緣包封體的第一部分中；步驟S74，將絕緣包封體的第一部分平坦化，以使絕緣包封體的第一部分的第一表面暴露出第一半導體元件中所包括的散熱元件；步驟S75，在第一半導體元件及第二半導體元件上設置多個第一導通孔及多個第二導通孔；步驟S76，在第一半導體元件及第二半導體元件之上且在第二導通孔上方設置連接元件(例如圖45中所繪示的橋接元件BE)以電連接第一半導體元件與第二半導體元件，其中連接元件實體地連接到以及電連接到與第一半導體元件及第二半導體元件連接的第二導通孔，以使得第一半導體元件與第二半導體元件通過連接元件及第二導通孔彼此電連通；步驟S77，將第一導通孔、第二導通孔及連接元件包封在絕緣包封體的第二部分中，其中第一導通孔的表面及連接元件的表 面與絕緣包封體的第二部分的第二表面實質上齊平且實質上共面；步驟S78，在絕緣包封體的第二部分的第二表面上形成重佈線路結構，以通過第一導通孔和/或連接到第二導通孔的連接元件電連接到第一半導體元件及第二半導體元件，其中絕緣包封體的第二部分夾置在重佈線路結構與絕緣包封體的第一部分之間；以及步驟S79，在重佈線路結構上設置多個導電端子，導電端子通過重佈線路結構電連接到第一半導體元件及第二半導體元件，其中重佈線路結構夾置在導電端子與絕緣包封體的第二部分之間。然而，本公開並非僅限於此。
在替代實施例中，可通過圖47的方法來製造封裝結構P7A。應理解，在圖47的方法的所示動作之前、期間及之後可發生附加處理以完成封裝結構P7A的形成。圖47的方法包括至少步驟S80到步驟S88。舉例來說，圖47中所示的方法從步驟S80開始，步驟S80提供至少一個第一半導體晶粒及至少一個第二半導體元件，其中第一半導體晶粒的厚度小於第二半導體元件的厚度；步驟S81，在第一半導體晶粒上設置散熱元件以形成第一半導體元件，其中散熱元件實體地連接到第一半導體晶粒，且散熱元件熱耦合到第一半導體晶粒；步驟S82，將第一半導體元件及第二半導體元件包封在絕緣包封體的第一部分中；步驟S83，將絕緣包封體的第一部分平坦化，以使絕緣包封體的第一部分的第一表面暴露出第一半導體元件中所包括的散熱元件；步驟S84，在第一半導體元件及第二半導體元件上設置多個第一導通孔及多個第二導通孔；步驟S85，在第一半導體元件及第二半導體元件之上且在第二導通孔上方設置連接元件(例如圖45中所繪示的橋接元件BE)以電 連接第一半導體元件與第二半導體元件，其中連接元件實體地連接到以及電連接到與第一半導體元件及第二半導體元件連接的第二導通孔，以使得第一半導體元件與第二半導體元件通過連接元件及第二導通孔彼此電連通；步驟S86，將第一導通孔、第二導通孔及連接元件包封在絕緣包封體的第二部分中，其中第一導通孔的表面及連接元件的表面與絕緣包封體的第二部分的第二表面實質上齊平且實質上共面；步驟S87，在絕緣包封體的第二部分的第二表面上形成重佈線路結構，以通過第一導通孔和/或連接到第二導通孔的連接元件電連接到第一半導體元件及第二半導體元件，其中絕緣包封體的第二部分夾置在重佈線路結構與絕緣包封體的第一部分之間；以及步驟S88，在重佈線路結構上設置多個導電端子，導電端子通過重佈線路結構電連接到第一半導體元件及第二半導體元件，其中重佈線路結構夾置在導電端子與絕緣包封體的第二部分之間。然而，本公開並非僅限於此。
在一些替代實施例中，可通過圖48的方法來製造封裝結構P7A。應理解，在圖48的方法的所示動作之前、期間及之後可發生附加處理以完成封裝結構P7A的形成。圖48的方法包括至少步驟S90到步驟S99。舉例來說，圖48所示的方法從步驟S90開始，步驟S90提供至少一個第一半導體晶粒及至少一個第二半導體元件，其中第一半導體晶粒的厚度小於第二半導體元件的厚度；步驟S91，在第一半導體晶粒上設置虛設元件；步驟S92，將上面設置有虛設元件的第一半導體晶粒及第二半導體元件包封在絕緣包封體的第一部分中；步驟S93，將絕緣包封體的第一部分平坦化，以使絕緣包封體的第一部分的第一表面暴露出設置在第一半 導體晶粒上的虛設元件；步驟S94，在第一半導體晶粒及第二半導體元件上設置多個第一導通孔及多個第二導通孔；步驟S95，在第一半導體晶粒及第二半導體元件之上且在第二導通孔上方設置連接元件(例如圖45中所繪示的橋接元件BE)以電連接第一半導體晶粒與第二半導體元件，其中連接元件實體地連接到以及電連接到與第一半導體晶粒及第二半導體元件連接的第二導通孔，以使得第一半導體晶粒與第二半導體元件通過連接元件及第二導通孔彼此電連通；步驟S96，通過絕緣包封體的第二部分包封第一導通孔、第二導通孔及連接元件，其中第一導通孔的表面及連接元件的表面與絕緣包封體的第二部分的第二表面實質上齊平且實質上共面；步驟S97，在絕緣包封體的第二部分的第二表面上形成重佈線路結構，以通過第一導通孔和/或連接到第二導通孔的連接元件電連接到第一半導體晶粒及第二半導體元件，其中絕緣包封體的第二部分夾置在重佈線路結構與絕緣包封體的第一部分之間；步驟S98，在重佈線路結構上設置多個導電端子，導電端子通過重佈線路結構電連接到第一半導體晶粒及第二半導體元件，其中重佈線路結構夾置在導電端子與絕緣包封體的第二部分之間；以及步驟S99，從第一半導體晶粒移除虛設元件且在第一半導體晶粒上直接設置散熱元件以形成第一半導體元件，其中散熱元件實體地連接到第一半導體晶粒，且散熱元件熱耦合到第一半導體晶粒。
然而，本公開並非僅限於此；在一些替代實施例中，可用圖21A中所繪示的半導體元件10c或圖33A中所繪示的半導體元件10e代替封裝結構P7A的半導體元件10a；或者，封裝結構P7A的半導體元件10a可被圖14B中所繪示的半導體元件10b(參見 圖49中所示的封裝結構P7B)、圖21B中所繪示的半導體元件10d或圖33B中所繪示的半導體元件10f代替。
在一些替代實施例中，除了圖36、圖40到圖45、及圖49中的導電端子900之外，可通過替代UBM圖案u1的接合墊(未示出)在重佈線路結構800上設置附加半導體元件(未示出)。附加半導體元件可包括被動元件或主動元件。附加半導體元件的數目在本公開中不受限制，且可基於需要及設計佈局來指定。在一些實施例中，封裝結構P4A到封裝結構P7B可進一步安裝有附加封裝、晶片/晶粒、其他電子元件或合適的基底(例如有機基底)，以形成堆疊的封裝結構，本公開並非僅限於此。
根據一些實施例，一種封裝結構包括電路元件、第一半導體晶粒、第二半導體晶粒、散熱元件以及絕緣包封體。所述第一半導體晶粒及所述第二半導體晶粒位於所述電路元件上。所述散熱元件連接到所述第一半導體晶粒，且所述第一半導體晶粒位於所述電路元件與所述散熱元件之間，其中所述第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述第二半導體晶粒的第二厚度。所述絕緣包封體包封所述第一半導體晶粒、所述第二半導體晶粒及所述散熱元件，其中所述散熱元件的表面與所述絕緣包封體的表面實質上齊平。
在一些實施例中，在所述封裝結構中，其中在剖面圖中，所述散熱元件的側壁與所述第一半導體晶粒的側壁實質上對齊。在一些實施例中，在所述封裝結構中，其中所述散熱元件包括黏著基底層，且所述黏著基底層的導熱係數大於所述絕緣包封體的導熱係數。在一些實施例中，在所述封裝結構中，其中在剖面圖中， 在所述散熱元件的側壁與所述第一半導體晶粒的側壁之間存在偏移，且所述偏移介於從5微米到5000微米的範圍內。在一些實施例中，在所述封裝結構中，其中所述散熱元件包括基底層及位於所述基底層與所述第一半導體晶粒之間的黏著層，其中所述基底層的導熱係數大於所述絕緣包封體的導熱係數，且所述黏著層的導熱係數大於所述絕緣包封體的所述導熱係數。在一些實施例中，在所述封裝結構中，其中在剖面圖中，在所述基底層的側壁與所述黏著層的側壁之間存在第一偏移，且在所述黏著層的所述側壁與所述第一半導體晶粒的側壁之間存在第二偏移，且所述第一偏移與所述第二偏移獨立地介於從5微米到5000微米的範圍內。在一些實施例中，在所述封裝結構中，其中所述電路元件是不與所述絕緣包封體相接觸的電路基底，且所述封裝結構還包括：中介體結構，位於所述第一半導體晶粒與所述電路元件之間且連接到所述第一半導體晶粒及所述電路元件；以及多個導電端子，位於所述電路元件上，所述電路元件位於所述中介體結構與所述多個導電端子之間。在一些實施例中，在所述封裝結構中，其中所述電路元件是重佈線路結構，所述重佈線路結構的被所述第一半導體晶粒及所述第二半導體晶粒暴露出的部分被所述絕緣包封體覆蓋，且所述封裝結構還包括：多個導電端子，位於所述電路元件上，所述電路元件位於所述絕緣包封體與所述多個導電端子之間。在一些實施例中，在所述封裝結構中，其中所述電路元件是重佈線路結構，所述重佈線路結構的被所述第一半導體晶粒及所述第二半導體晶粒暴露出的部分被所述絕緣包封體覆蓋，且所述封裝結構還包括：連接元件，具有半導體基底及穿透所述半導體基底的多個穿孔，所述連 接元件位於所述第一半導體晶粒及所述第二半導體晶粒上，所述第一半導體晶粒與所述第二半導體晶粒通過所述連接元件電連通；多個導電柱，位於所述第一半導體晶粒及所述第二半導體晶粒上且連接到所述第一半導體晶粒及所述第二半導體晶粒，並位於所述連接元件旁邊；以及多個導電端子，位於所述電路元件上，所述電路元件位於所述絕緣包封體與所述多個導電端子之間，其中所述絕緣包封體包括包封所述第一半導體晶粒及所述第二半導體晶粒的第一部分以及包封所述連接元件及所述多個導電柱的第二部分，所述第二部分位於所述第一部分與所述電路元件之間。
根據一些實施例，一種製造封裝結構的方法包括以下步驟，提供連接有散熱元件的第一半導體晶粒；提供第二半導體晶粒；將所述第一半導體晶粒、所述第二半導體晶粒及所述散熱元件包封在絕緣包封體中；以及將所述絕緣包封體平坦化，以使所述絕緣包封體暴露出所述散熱元件，其中所述第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述第二半導體晶粒的第二厚度。
在一些實施例中，在所述製造封裝結構的方法中，其中提供連接有所述散熱元件的所述第一半導體晶粒包括：提供具有電路系統的第一晶圓及包括所述散熱元件的第二晶圓；將所述第一晶圓接合到所述第二晶圓，以形成堆疊結構；以及對所述堆疊結構進行切分，以形成連接有所述散熱元件的所述第一半導體晶粒。在一些實施例中，在所述製造封裝結構的方法中，其中提供連接有所述散熱元件的所述第一半導體晶粒包括：提供所述第一半導體晶粒；將所述第一半導體晶粒設置在電路元件上；以及將所述散熱元 件設置在所述第一半導體晶粒上。在一些實施例中，所述製造封裝結構的方法還包括：在所述絕緣包封體上形成電連接到所述第一半導體晶粒及所述第二半導體晶粒的重佈線路結構；以及在所述重佈線路結構上設置多個導電端子，其中所述重佈線路結構夾置在所述多個導電端子與所述絕緣包封體之間。在一些實施例中，在所述製造封裝結構的方法中，其中所述絕緣包封體包括包封所述第一半導體晶粒及所述第二半導體晶粒的第一部分及堆疊在所述第一部分上的第二部分，在形成所述重佈線路結構之前，所述方法還包括：在被包封在所述第一部分中的所述第一半導體晶粒及所述第二半導體晶粒上設置連接元件，以電連通所述第一半導體晶粒與所述第二半導體晶粒；在所述第一半導體晶粒及所述第二半導體晶粒上形成多個導電柱；以及將所述連接元件及所述多個導電柱包封在所述絕緣包封體的所述第二部分中，所述第二部分位於所述第一部分與所述重佈線路結構之間。在一些實施例中，所述製造封裝結構的方法還包括：提供其中具有多個穿孔的中介體；在將所述第一半導體晶粒及所述第二半導體晶粒包封在所述絕緣包封體中之前，通過倒裝晶片接合將所述第一半導體晶粒及所述第二半導體晶粒設置在所述中介體上；在將所述絕緣包封體平坦化之後，將所述中介體圖案化以顯露出所述多個穿孔；在被顯露出的所述多個穿孔上形成多個連接件，所述中介體夾置在所述絕緣包封體與所述多個連接件之間；以及通過所述中介體的所述多個連接件，將所述第一半導體晶粒與所述第二半導體晶粒接合在具有多個導電端子的電路結構上，所述電路基底夾置在所述多個導電端子與所述多個連接件之間。在一些實施例中，所述製造封裝結構 的方法還包括：提供蓋；將所述蓋設置在所述電路基底上，所述第一半導體晶粒、所述第二半導體晶粒及所述中介體位於由所述蓋及所述電路結構包圍的空間中；以及在所述蓋和與所述絕緣包封體的表面實質上齊平的所述散熱元件的表面之間設置熱黏著層。
根據一些實施例，一種製造封裝結構的方法包括以下步驟，提供至少一個第一半導體晶粒及至少一個第二半導體晶粒；在所述至少一個第一半導體晶粒的表面上設置虛設元件，所述至少一個第一半導體晶粒位於所述虛設元件之上；將所述至少一個第一半導體晶粒、所述至少一個第二半導體晶粒及所述虛設元件包封在絕緣包封體中；將所述絕緣包封體平坦化，以使所述絕緣包封體的表面暴露出所述虛設元件；移除所述虛設元件，以在所述絕緣包封體中形成凹槽；以及在所述至少一個第一半導體晶粒上及在所述凹槽中設置散熱元件，其中所述至少一個第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述至少一個第二半導體晶粒的第二厚度。
在一些實施例中，在所述製造封裝結構的方法中，在移除所述虛設元件之前，還包括：在所述絕緣包封體上形成電連接到所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒的重佈線路結構；以及在所述重佈線路結構上設置多個導電端子，其中所述重佈線路結構夾置在所述多個導電端子與所述絕緣包封體之間。在一些實施例中，在所述製造封裝結構的方法中，其中所述絕緣包封體包括包封所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒的第一部分及堆疊在所述第一部分上的第二部分，在形成所述重佈線路結構之前，所述方法還包括：在被包封在 所述第一部分中的所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒上設置連接元件，以電連通所述至少一個第一半導體晶粒與所述至少一個第二半導體晶粒；在所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒上形成多個導電柱；以及將所述連接元件及所述多個導電柱包封在所述絕緣包封體的所述第二部分中，所述第二部分位於所述第一部分與所述重佈線路結構之間。在一些實施例中，所述製造封裝結構的方法還包括：提供其中具有多個穿孔的中介體；在所述至少一個第一半導體晶粒上設置所述虛設元件之前，通過倒裝晶片接合將所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒設置在所述中介體上；在將所述絕緣包封體平坦化之後，將所述中介體圖案化以顯露出所述多個穿孔；在被顯露出的所述多個穿孔上形成多個連接件，所述中介體夾置在所述絕緣包封體與所述多個連接件之間；以及通過所述中介體的所述多個連接件，將所述第一半導體晶粒與所述第二半導體晶粒接合在具有多個導電端子的電路結構上，所述電路基底夾置在所述多個導電端子與所述多個連接件之間。
前文概述若干實施例的特徵以使得本領域的技術人員可更佳地理解本發明的態樣。本領域的技術人員應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。本領域的技術人員亦應認識到，這些等效構造並不脫離本發明的精神及範疇，且本領域的技術人員可在不脫離本發明的精神及範疇之情況下在本文中作出各種改變、替代及更改。
10a：半導體元件 20：第二半導體元件/半導體元件 22、140：導通孔 310：基底 340：重佈線路結構 342：介電結構 344：金屬化層 320：穿孔 100：第一半導體晶粒/半導體晶粒 210：基底層 220：黏著層 360、380：導電連接件 400：絕緣包封體 HDE：散熱元件 P1A：封裝結構 Z：堆疊方向

Claims (10)

  1. 一種封裝結構，包括：電路元件；第一半導體晶粒及第二半導體晶粒，位於所述電路元件上，其中所述第一半導體晶粒包括基板與設置在所述基板上的多個第一導通孔，且所述多個第一導通孔凸出於所述基板；散熱元件，連接到所述第一半導體晶粒，所述第一半導體晶粒位於所述電路元件與所述散熱元件之間且所述基板位於所述多個第一導通孔與所述散熱元件之間，其中所述第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述第二半導體晶粒的第二厚度；以及絕緣包封體，包封所述第一半導體晶粒、所述第二半導體晶粒及所述散熱元件，其中所述散熱元件的表面與所述絕緣包封體的表面實質上齊平，且所述散熱元件的側壁與所述絕緣包封體接觸。
  2. 如申請專利範圍第1項所述的封裝結構，其中在剖面圖中，所述散熱元件的所述側壁與所述第一半導體晶粒的側壁實質上對齊。
  3. 如申請專利範圍第1項所述的封裝結構，其中所述散熱元件包括基底層及位於所述基底層與所述第一半導體晶粒之間的黏著層，其中所述基底層的導熱係數大於所述絕緣包封體的導熱係數，且所述黏著層的導熱係數大於所述絕緣包封體的所述導熱係數。
  4. 如申請專利範圍第3項所述的封裝結構，其中在剖面圖 中，在所述基底層的側壁與所述黏著層的側壁之間存在第一偏移，且在所述黏著層的所述側壁與所述第一半導體晶粒的側壁之間存在第二偏移，且所述第一偏移與所述第二偏移獨立地介於從5微米到5000微米的範圍內。
  5. 一種製造封裝結構的方法，包括：提供連接有散熱元件的第一半導體晶粒，所述第一半導體晶粒包括基板與設置在所述基板上的多個第一導通孔，且所述多個第一導通孔凸出於所述基板，其中所述基板位於所述多個第一導通孔與所述散熱元件之間；提供第二半導體晶粒；將所述第一半導體晶粒、所述第二半導體晶粒及所述散熱元件包封在絕緣包封體中；以及將所述絕緣包封體平坦化，以使所述絕緣包封體暴露出所述散熱元件並接觸所述散熱元件的側壁，其中所述第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述第二半導體晶粒的第二厚度。
  6. 如申請專利範圍第5項所述的方法，其中提供連接有所述散熱元件的所述第一半導體晶粒包括：提供具有電路系統的第一晶圓及包括所述散熱元件的第二晶圓；將所述第一晶圓接合到所述第二晶圓，以形成堆疊結構；以及對所述堆疊結構進行切分，以形成連接有所述散熱元件的所述第一半導體晶粒。
  7. 如申請專利範圍第5項所述的方法，其中提供連接有所述散熱元件的所述第一半導體晶粒包括：提供所述第一半導體晶粒；將所述第一半導體晶粒設置在電路元件上；以及將所述散熱元件設置在所述第一半導體晶粒上。
  8. 一種製造封裝結構的方法，包括：提供至少一個第一半導體晶粒及至少一個第二半導體晶粒；在所述至少一個第一半導體晶粒的表面上設置虛設元件，所述至少一個第一半導體晶粒位於所述虛設元件之上；將所述至少一個第一半導體晶粒、所述至少一個第二半導體晶粒及所述虛設元件包封在絕緣包封體中；將所述絕緣包封體平坦化，以使所述絕緣包封體的表面暴露出所述虛設元件；移除所述虛設元件，以在所述絕緣包封體中形成凹槽；以及在所述至少一個第一半導體晶粒上及在所述凹槽中設置散熱元件，其中所述至少一個第一半導體晶粒的第一厚度與所述散熱元件的第三厚度之和實質上等於所述至少一個第二半導體晶粒的第二厚度。
  9. 如申請專利範圍第8項所述的方法，在移除所述虛設元件之前，更包括：在所述絕緣包封體上形成電連接到所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒的重佈線路結構；以及在所述重佈線路結構上設置多個導電端子，其中所述重佈線路結構夾置在所述多個導電端子與所述絕緣包封體之間。
  10. 如申請專利範圍第9項所述的方法，其中所述絕緣包封體包括包封所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒的第一部分及堆疊在所述第一部分上的第二部分，在形成所述重佈線路結構之前，所述方法更包括：在被包封在所述第一部分中的所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒上設置連接元件，以電連通所述至少一個第一半導體晶粒與所述至少一個第二半導體晶粒；在所述至少一個第一半導體晶粒及所述至少一個第二半導體晶粒上形成多個導電柱；以及將所述連接元件及所述多個導電柱包封在所述絕緣包封體的所述第二部分中，所述第二部分位於所述第一部分與所述重佈線路結構之間。
TW108143536A 2019-09-17 2019-11-29 封裝結構及其製造方法 TWI727523B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/572,619 2019-09-17
US16/572,619 US11164855B2 (en) 2019-09-17 2019-09-17 Package structure with a heat dissipating element and method of manufacturing the same

Publications (2)

Publication Number Publication Date
TW202113995A TW202113995A (zh) 2021-04-01
TWI727523B true TWI727523B (zh) 2021-05-11

Family

ID=74869057

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108143536A TWI727523B (zh) 2019-09-17 2019-11-29 封裝結構及其製造方法

Country Status (3)

Country Link
US (1) US11164855B2 (zh)
CN (1) CN112530913A (zh)
TW (1) TWI727523B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11728238B2 (en) * 2019-07-29 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with heat dissipation films and manufacturing method thereof
US11404379B2 (en) * 2020-11-17 2022-08-02 International Business Machines Corporation Structure and method for bridge chip assembly with capillary underfill
US11848246B2 (en) * 2021-03-24 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11862590B2 (en) 2021-04-14 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of forming thereof
US20230014913A1 (en) * 2021-07-15 2023-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. Heat Dissipation Structures for Integrated Circuit Packages and Methods of Forming the Same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201639106A (zh) * 2015-04-30 2016-11-01 台灣積體電路製造股份有限公司 具有虛設晶粒之扇出堆疊系統級封裝（ｓｉｐ）及其製造方法
TW201919184A (zh) * 2017-11-03 2019-05-16 南韓商三星電機股份有限公司 扇出型半導體封裝

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201639106A (zh) * 2015-04-30 2016-11-01 台灣積體電路製造股份有限公司 具有虛設晶粒之扇出堆疊系統級封裝（ｓｉｐ）及其製造方法
TW201919184A (zh) * 2017-11-03 2019-05-16 南韓商三星電機股份有限公司 扇出型半導體封裝

Also Published As

Publication number Publication date
TW202113995A (zh) 2021-04-01
US11164855B2 (en) 2021-11-02
CN112530913A (zh) 2021-03-19
US20210082894A1 (en) 2021-03-18

Similar Documents

Publication Publication Date Title
US11189603B2 (en) Semiconductor packages and methods of forming same
TWI681466B (zh) 半導體結構及積體電路封裝的形成方法
TWI746306B (zh) 封裝結構及其形成方法
TWI727523B (zh) 封裝結構及其製造方法
TWI730879B (zh) 封裝結構及其製作方法
TW202105663A (zh) 積體電路封裝
US11869819B2 (en) Integrated circuit component and package structure having the same
TWI719678B (zh) 半導體結構及其形成方法
US11211371B2 (en) Integrated circuit package and method
TW202209509A (zh) 積體電路封裝及其形成方法
US20230170304A1 (en) Semiconductor package
CN115295507A (zh) 集成电路器件和其形成方法
TWI756907B (zh) 封裝結構及其製作方法
KR20240005646A (ko) 집적 회로 패키지 및 방법
US20230378019A1 (en) Package structure and method of fabricating the same
TWI776646B (zh) 積體電路封裝體及其形成方法
TWI735353B (zh) 積體電路封裝及其製作方法
TWI765601B (zh) 半導體裝置及製造方法
KR102524244B1 (ko) 반도체 패키지들에서의 방열 및 그 형성 방법
US20230317585A1 (en) Package structure and manufacturing method thereof
TW202401695A (zh) 半導體封裝及方法
TW202329377A (zh) 半導體封裝及其製造方法