TW202209509A - 積體電路封裝及其形成方法 - Google Patents

積體電路封裝及其形成方法 Download PDF

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TW202209509A
TW202209509A TW110107233A TW110107233A TW202209509A TW 202209509 A TW202209509 A TW 202209509A TW 110107233 A TW110107233 A TW 110107233A TW 110107233 A TW110107233 A TW 110107233A TW 202209509 A TW202209509 A TW 202209509A
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Taiwan
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integrated circuit
circuit element
stress reducing
package
buffer layer
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TW110107233A
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TWI796640B (zh
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邱文智
林士庭
余振華
盧思維
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台灣積體電路製造股份有限公司
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Abstract

一種積體電路封裝，包括：中介板；第一積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至中介板；第二積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至中介板；緩衝層，圍繞第一積體電路元件及第二積體電路元件，緩衝層包含具有第一楊氏模數的應力減小材料；以及包封體，圍繞緩衝層、第一積體電路元件以及第二積體電路元件，包封體包含具有第二楊氏模數的模製材料，且第一楊氏模數小於第二楊氏模數。

Description

積體電路封裝及其形成方法
自積體電路（integrated circuit；IC）的發展以來，半導體行業因各種電子組件（亦即，電晶體、二極體、電阻器、電容器等）的積體密度的持續改良而已經歷持續快速增長。在很大程度上，積體密度的此等改良來自最小特徵大小的重複減小，此允許將更多組件整合至給定區域中。
此等積體改良基本上在本質上為二維（two-dimensional；2D）的，此是由於由積體組件佔據的區域基本上在半導體晶圓的表面上。積體電路的增加的密度及面積的對應減小總體上已超過將積體電路晶片直接接合至基板上的能力。中介板已用於將球接觸區域自晶片的球接觸區域重佈至中介板的較大區域。此外，中介板已允許包含多個晶片的三維封裝。亦已研發其他封裝以併入三維態樣。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露內容。當然，此等僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清晰的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，為易於描述，本文中可使用諸如「在.…..之下」、「在.…..下方」、「下部」、「在.…..上方」、「上部」以及類似者的空間相對術語，以描述如諸圖中所示出的一個部件或特徵相對於另一部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
根據各種實施例，藉由將積體電路元件直接接合至含有另一元件（諸如中介板）的晶圓來形成積體電路封裝。在包封積體電路元件之前，圍繞積體電路元件形成應力緩衝層。應力緩衝層由有助於包封體在高溫下膨脹期間保護積體電路元件的材料形成。因此可提高積體電路封裝的良率及可靠性。
圖1為積體電路元件50的剖面圖。多個積體電路元件50將在後續處理中經封裝以形成積體電路封裝。每一積體電路元件50可為邏輯元件（例如中央處理單元（central processing unit；CPU）、圖形處理單元（graphics processing unit；GPU）、微控制器等）、記憶體元件（例如動態隨機存取記憶體（dynamic random access memory；DRAM）晶粒、靜態隨機存取記憶體（static random access memory；SRAM）晶粒等）、功率管理元件（例如功率管理積體電路（power management integrated circuit；PMIC）晶粒）、射頻（radio frequency；RF）元件、感測器元件、微機電系統（MEMS；micro-electro-mechanical-system）元件、訊號處理元件（例如數位信號處理（digital signal processing；DSP）晶粒）、前端元件（例如類比前端（analog front-end；AFE）晶粒）、類似者或其組合（例如系統單晶片（system-on-a-chip；SoC）晶粒）。積體電路元件50可形成於晶圓中，所述晶圓可包含在後續步驟中經單體化以形成多個積體電路元件50的不同元件區。積體電路元件50包括半導體基板52、內連線結構54、晶粒連接件56以及介電層58。
半導體基板52可為經摻雜的或未經摻雜的矽基板，或絕緣層上半導體（semiconductor-on-insulator；SOI）基板的主動層。半導體基板52可包含其他半導體材料，諸如：鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含矽-鍺、砷化鎵磷化物、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵及/或砷化銦鎵磷化物；或其組合。亦可使用其他基板，諸如多層基板或梯度基板（gradient substrate）。半導體基板52具有主動表面（例如面朝上的表面）及非主動表面（例如面朝下的表面）。元件位於半導體基板52的主動表面處。元件可為主動元件（例如，電晶體、二極體等）、電容器、電阻器等。非主動表面可不含元件。
內連線結構54位於半導體基板52的主動表面上，且用於電性連接半導體基板52的元件以形成積體電路。內連線結構54可包括一或多個介電層及介電層中的各別金屬化圖案。用於介電層的可接受的介電材料包括：氧化物（諸如氧化矽或氧化鋁）；氮化物（諸如氮化矽）；碳化物（諸如碳化矽）；類似者；或其組合（諸如氮氧化矽、碳氧化矽、碳氮化矽、氧碳氮化矽或類似者）。亦可使用其他介電材料，諸如聚合物（諸如聚苯并噁唑（PBO））、聚醯亞胺、苯環丁烷（BCB）類聚合物或類似者。金屬化圖案可包括導通孔及/或導電線以內連半導體基板52的元件。金屬化圖案可由諸如金屬（諸如銅、鈷、鋁、金、其組合或類似者）的導電材料形成。內連線結構54可藉由金屬鑲嵌製程（諸如單金屬鑲嵌製程、雙金屬鑲嵌製程或類似者）形成。
晶粒連接件56位於積體電路元件50的前側50F處。晶粒連接件56可為與其形成外部連接的導電柱、墊或類似者。晶粒連接件56位於內連線結構54中及/或內連線結構54上。舉例而言，晶粒連接件56可為內連線結構54的上部金屬化圖案的一部分。晶粒連接件56可由諸如銅、鋁或類似者的金屬形成，且可藉由例如鍍覆或類似者形成。
可選地，在形成積體電路元件50期間，焊料區（例如焊料球或焊料凸塊）可配置於晶粒連接件56上。焊料球可用於對積體電路元件50執行晶片探針（chip probe；CP）測試。可對積體電路元件50執行CP測試以確定積體電路元件50是否為良裸晶粒（known good die；KGD）。因此，僅封裝經受後續處理的為KGD的積體電路元件50，且不封裝未通過CP測試的元件。在測試之後，可在後續處理步驟中移除焊料區。
介電層58位於積體電路元件50的前側50F處。介電層58位於內連線結構54中及/或內連線結構54上。舉例而言，介電層58可為內連線結構54的上部介電層。介電層58側向地包封晶粒連接件56。介電層58可為氧化物、氮化物、碳化物、聚合物、類似者或其組合。介電層58可例如藉由旋轉塗佈、疊層、化學氣相沈積（chemical vapor deposition；CVD）或類似者形成。最初，介電層58可埋住晶粒連接件56，使得介電層58的頂表面在晶粒連接件56的頂表面上方。在形成積體電路元件50期間，晶粒連接件56經由介電層58暴露出。暴露晶粒連接件56可移除可能存在於晶粒連接件56上的任何焊料區。移除製程可應用於各種層以移除晶粒連接件56上的多餘材料。移除製程可為平坦化製程，諸如化學機械研磨（chemical mechanical polish；CMP）、回蝕（etch-back）、其組合或類似者。在平坦化之後，晶粒連接件56及介電層58的頂表面為共面的（在製程變化內）且在積體電路元件50的前側50F處暴露出。如下文將更詳細地描述，積體電路元件50的平坦化前側50F將接合至另一元件，諸如中介板。
在一些實施例中，積體電路元件50為包括多個半導體基板52的堆疊元件。舉例而言，積體電路元件50可為包括多個記憶體晶粒的記憶體元件，諸如混合記憶體立方體（hybrid memory cube；HMC）元件、高頻寬記憶體（high bandwidth memory；HBM）元件或類似者。在此類實施例中，積體電路元件50包括藉由基板穿孔或矽穿孔（through-silicon via；TSV）內連的多個半導體基板52。半導體基板52中的每一者可（或可不）具有單獨的內連線結構54。
圖2至圖9為根據一些實施例的在用於形成積體電路封裝的製程期間的中間步驟的剖面圖。在圖2至圖8中，藉由將積體電路元件50接合至晶圓70來形成積體電路封裝100。在實施例中，積體電路封裝100為晶圓上晶片（chip-on-wafer；CoW）封裝，但應瞭解，實施例可應用於其他三維積體電路（three-dimensional integrated circuit；3DIC）封裝。晶圓70具有封裝區100A、封裝區100B，所述封裝區100A、封裝區100B各自包含形成於其中的元件，諸如中介板。在圖9中，封裝區100A、封裝區100B經單體化以形成積體電路封裝100，每一積體電路封裝100包括晶圓70的單體化部分（例如中介板140，參看圖9）及接合至晶圓70的單體化部分的積體電路元件50。隨後將積體電路封裝100安裝至封裝基板200。在實施例中，所得元件為基板上晶圓上晶片（chip-on-wafer-on-substrate；CoWoS）封裝，但應瞭解，實施例可應用於其他3DIC封裝。
在圖2中，獲得晶圓70。晶圓70包括位於封裝區100A以及封裝區100B中的元件，所述元件將在後續處理中經單體化以包含於積體電路封裝100中。形成於晶圓70中的元件可為中介板、積體電路晶粒或類似者。晶圓70包括基板72、內連線結構74、晶粒連接件76、介電層78以及導通孔80。
基板72可為塊狀半導體基板、絕緣層上半導體（SOI）基板、多層半導體基板或類似者。基板72可包含半導體材料，諸如：矽；鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含矽-鍺、砷化鎵磷化物、砷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵及/或砷化銦鎵磷化物；或其組合。亦可使用其他基板，諸如多層基板或梯度基板。基板72可經摻雜或未經摻雜。在中介板形成於晶圓70中的實施例中，儘管中介板可包含形成於基板72的前表面（例如，面朝上的表面）中及/或基板72的前表面上的被動元件，但基板72一般並不在其中包含主動元件。在積體電路元件形成於晶圓70中的實施例中，主動元件（諸如電晶體、電容器、電阻器、二極體以及類似者）可形成於基板72的前表面中及/或基板72的前表面上。
內連線結構74位於基板72的前表面上，且用於電性連接基板72的元件（若存在）。內連線結構74可包括一或多個介電層及介電層中的各別金屬化圖案。用於介電層的可接受的介電材料包括：氧化物（諸如氧化矽或氧化鋁）；氮化物（諸如氮化矽）；碳化物（諸如碳化矽）；類似者；或其組合（諸如氮氧化矽、碳氧化矽、碳氮化矽、氧碳氮化矽（silicon oxycarbonitride）或類似者）。亦可使用其他介電材料，諸如聚合物（諸如聚苯并噁唑（PBO））、聚醯亞胺、苯環丁烷（BCB）類聚合物或類似者。金屬化圖案可包括導通孔及/或導電線以將任何元件內連在一起及/或連接至外部元件。金屬化圖案可由諸如金屬（諸如銅、鈷、鋁、金、其組合或類似者）的導電材料形成。內連線結構74可藉由金屬鑲嵌製程（諸如單金屬鑲嵌製程、雙金屬鑲嵌製程或類似者）形成。
晶粒連接件76位於晶圓70的前側70F處。晶粒連接件76可為與其形成外部連接的導電柱、墊或類似者。晶粒連接件76位於內連線結構74中及/或內連線結構74上。舉例而言，晶粒連接件76可為內連線結構74的上部金屬化圖案的一部分。晶粒連接件76可由諸如銅、鋁或類似者的金屬形成，且可藉由例如鍍覆或類似者形成。
介電層78位於晶圓70的前側70F處。介電層78位於內連線結構74中及/或內連線結構74上。舉例而言，介電層78可為內連線結構74的上部介電層。介電層78側向地包封晶粒連接件76。介電層78可為氧化物、氮化物、碳化物、聚合物、類似者或其組合。介電層78可例如藉由旋轉塗佈、疊層、化學氣相沈積（CVD）或類似者形成。最初，介電層78可埋住晶粒連接件76，使得介電層78的頂表面在晶粒連接件76的頂表面上方。在形成晶圓70期間，晶粒連接件76經由介電層78暴露出。移除製程可應用於各種層以移除晶粒連接件76上的多餘材料。移除製程可為平坦化製程，諸如化學機械研磨（CMP）、回蝕、其組合或類似者。在平坦化之後，晶粒連接件76及介電層78的頂表面為共面的（在製程變化內）且在晶圓70的前側70F處暴露出。如下文將更詳細地描述，晶圓70的平坦化前側70F將接合至其他元件，諸如積體電路元件50A、50B。
導通孔80延伸至內連線結構74及/或基板72中。導通孔80電性耦接至內連線結構74的金屬化圖案。導通孔80有時亦被稱作TSV。作為用於形成導通孔80的實例，可藉由例如蝕刻、銑削（milling）、雷射技術、其組合及/或類似者在內連線結構74及/或基板72中形成凹部。可諸如藉由使用氧化技術在凹部中形成薄介電材料。薄阻障層（barrier）可藉由諸如CVD、原子層沈積（atomic layer deposition；ALD）、物理氣相沈積（physical vapor deposition；PVD）、熱氧化、其組合及/或類似者而共形地（conformally）沈積於開口中。阻障層可由氧化物、氮化物、碳化物、其組合或類似者形成。導電材料可沈積於阻障層上及開口中。導電材料可藉由電化學鍍覆製程、CVD、ALD、PVD、其組合及/或類似者形成。導電材料的實例為銅、鎢、鋁、銀、金、其組合及/或類似者。藉由例如CMP自內連線結構74或基板72的表面移除多餘的導電材料及阻障層。阻障層及導電材料的剩餘部分形成導通孔80。
積體電路元件50接合至晶圓70。在此實施例中，積體電路元件50包括置放於封裝區100A、封裝區100B中的每一者中的多個積體電路元件50A、積體電路元件50B。積體電路元件50A、積體電路元件50B可各自具有單一功能（例如邏輯元件、記憶體元件等）或可具有多個功能（例如SoC）。在實施例中，積體電路元件50A為邏輯元件，而積體電路元件50B為記憶體元件。在此實施例中，積體電路元件50A（例如邏輯元件）及積體電路元件50B（例如記憶體元件）接合於封裝區100A、封裝區100B中的每一者中。在另一實施例中，單一積體電路元件50接合於封裝區100A、封裝區100B中的每一者中。
積體電路元件50及晶圓70藉由混合接合（hybrid bonding）以面對面方式直接接合，使得積體電路元件50的前側50F接合至晶圓70的前側70F。具體而言，積體電路元件50的介電層58經由介電質對介電質接合而不使用任何黏著材料（例如晶粒貼合膜）來接合至晶圓70的介電層78，且積體電路元件50的晶粒連接件56經由金屬對金屬接合而不使用任何共熔材料（例如焊料）來接合至晶圓70的晶粒連接件76。接合可包括預接合及退火。在預接合期間，施加較小按壓力以將積體電路元件50壓靠於晶圓70上。預接合在諸如室溫的低溫（諸如約15℃至約30℃範圍內的溫度）下執行，且在預接合之後，介電層58、介電層78彼此接合。隨後在後續退火步驟中提高接合強度，其中介電層58、介電層78在高溫（諸如約100℃至約450℃範圍內的溫度）下退火。在退火之後，形成接合（諸如熔合接合（fusion bonding））從而接合介電層58、介電層78。舉例而言，接合可為介電層58的材料與介電層78的材料之間的共價接合（covalent bond）。晶粒連接件56、晶粒連接件76以一對一的對應關係彼此連接。晶粒連接件56、晶粒連接件76可在預接合之後實體接觸，或可擴展為在退火期間進行實體接觸。此外，在退火期間，晶粒連接件56、晶粒連接件76的材料（例如，銅）混合，使得亦形成金屬對金屬接合。因此，積體電路元件50與晶圓70之間的所得接合為包括介電質對介電質接合及金屬對金屬接合兩者的混合接合。
每一積體電路元件50的寬度小於晶圓70的寬度，使得多個積體電路元件50可接合至晶圓70。如下文將更詳細地描述，積體電路元件50A亦可具有與積體電路元件50B不同的寬度。當藉由混合接合來接合積體電路元件50及晶圓70時，積體電路元件50的外邊緣50E及內邊緣50N與介電層78的平坦化表面介接。積體電路元件50的外邊緣50E為每一各別封裝區100A、封裝區100B中的積體電路元件50的背離各別封裝區100A、封裝區100B中的其他積體電路元件50的彼等邊緣。積體電路元件50的內邊緣50N為每一各別封裝區100A、封裝區100B中的積體電路元件50的面朝各別封裝區100A、封裝區100B中的其他積體電路元件50的彼等邊緣。外邊緣50E經受大量應力，諸如比內邊緣50N更大的應力，此可能在後續處理中使用具有較大楊氏模數及/或較大熱膨脹係數（coefficient of thermal expansion；CTE）的材料包封積體電路元件50時加劇。外邊緣50E處的過度應力可能損壞積體電路元件50（例如內連線結構54及/或介電層58）、晶圓70（例如內連線結構74及/或介電層78）或兩者。舉例而言，介電層58、介電層78可能出現分層（delamination）。如下文將更詳細地描述，膜層將圍繞外邊緣50E形成以緩衝外邊緣50E處的應力。因此，可提高積體電路封裝100的良率及可靠性，尤其在後續包封積體電路元件50時。
在圖3中，將緩衝層108分配（dispense）於晶圓70的前側70F上且圍繞積體電路元件50。具體而言，緩衝層108圍繞封裝區100A、封裝區100B中的每一者中的積體電路元件50而分配。緩衝層108形成於經歷高應力的位置中（例如積體電路元件50的外邊緣50E）。緩衝層108由有助於緩衝外邊緣50E處（參看圖2）的應力的應力減小材料形成。應力減小材料包含聚合物材料且視情況包含填料及/或界面活性劑。聚合物材料可為環氧樹脂、聚醯亞胺類材料、BCB類材料、矽酮材料、丙烯酸材料或類似者。填料由為緩衝層108提供機械強度及熱分散的材料形成，諸如矽石（SiO2 ）顆粒。界面活性劑可為聚乙烯醇或類似者。應力減小材料（包含聚合物材料、填料及/或界面活性劑）可藉由印刷（例如噴墨印刷）、分配（例如標準分配（standard dispensing）、傾斜分配（tilt dispensing）等）、旋轉塗佈、疊層、沈積或類似者形成。
在此實施例中，緩衝層108具有嵌條部分（fillet portion）108F及間隙部分108G。間隙部分108G配置於積體電路元件50之間的間隙中。嵌條部分108F經配置為沿積體電路元件50的外邊緣50E延伸。在其他實施例中，省略間隙部分108G且緩衝層108僅具有嵌條部分108F。
在此實施例中，嵌條部分108F及間隙部分108G具有直的頂表面。在其他實施例中，嵌條部分108F及/或間隙部分108G具有凹形頂表面。頂表面的類型可藉由所分配的應力減小材料的量（例如體積）及界面活性劑是否包含於應力減小材料中來決定。如下文將更詳細地描述，分配較少的應力減小材料及/或包含界面活性劑可形成凹形頂表面。
在此實施例中，緩衝層108在積體電路元件50的側壁完全向上地延伸，使得積體電路元件50的側壁的任何部分均不暴露於後續形成的包封體（例如不與所述包封體接觸）。在其他實施例中，緩衝層108可在積體電路元件50的側壁部分地向上延伸，使得積體電路元件50的側壁的部分暴露於後續形成的包封體。如下文將更詳細地描述，分配較少的應力減小材料可形成緩衝層108以在積體電路元件50的較少側壁向上延伸。
在圖4中，包封體110形成於各種組件上。包封體110由模製材料或化合物形成。模製材料包含聚合物材料且可選地包含填料。聚合物材料可為環氧樹脂或類似者。填料由為包封體110提供機械強度及熱分散的材料形成，諸如矽石（SiO2 ）顆粒。模製材料（包含聚合物材料及/或填料）可藉由壓縮模製、轉移模製或類似者形成。包封體110的聚合物材料與緩衝層108的聚合物材料不同，且藉由與緩衝層108的應力減小材料不同的方法形成。包封體110可形成於晶圓70的前側70F上，以掩埋或覆蓋積體電路元件50及緩衝層108。隨後固化包封體110。可執行平坦化製程以使包封體110的頂表面平坦化。平坦化製程可為化學機械研磨（CMP）、回蝕、其組合或類似者。在所示出的實施例中，在使包封體110平坦化之後保持覆蓋積體電路元件50。在另一實施例中，積體電路元件50藉由包封體110的平坦化而暴露出。
包封體110包圍及保護積體電路元件50。然而，包封體110的模製材料具有比介電層58、介電層78的介電材料更大的楊氏模數及更大的CTE。包封體110在高溫下的膨脹可在積體電路元件50上（尤其在外邊緣50E處）施加應力，而所述應力會損壞積體電路元件50及/或晶圓70。緩衝層108由在高溫下比包封體110更軟的應力減小材料形成，且因此有助於緩衝在膨脹期間由包封體110在外邊緣50E（參看圖2）處施加的應力。緩衝層108的應力減小材料具有允許其在高溫下有效地緩衝來自包封體110的模製材料的應力的若干物性。具體而言，緩衝層108的應力減小材料具有與包封體110的模製材料不同的楊氏模數、不同的CTE、不同的填料負載（例如填料數量）、不同的平均填料粒徑以及不同的伸長率（elongation）。
緩衝層108的應力減小材料具有比包封體110的模製材料更小的楊氏模數。在一些實施例中，應力減小材料的楊氏模數為模製材料的楊氏模數的約5%至約90%。舉例而言，應力減小材料可具有在約0.001 GPa至約0.9 GPa範圍內的楊氏模數，且模製材料可具有在約1 GPa至約2.5 GPa範圍內的楊氏模數。
緩衝層108的應力減小材料具有比包封體110的模製材料類似或更大的CTE。在一些實施例中，應力減小材料的CTE為模製材料的CTE的約150%至約500%。舉例而言，應力減小材料可具有在低於其玻璃轉化溫度（Tg ）約15 ppm/℃至約70 ppm/℃範圍內的CTE及在高於其Tg 約50 ppm/℃至約300 ppm/℃範圍內的CTE，且模製材料可具有在低於其Tg 約5 ppm/℃至約22 ppm/℃範圍內的CTE及在高於其Tg 約22 ppm/℃至約60 ppm/℃範圍內的CTE。
緩衝層108的應力減小材料具有比包封體110的模製材料更小的填料負載（當應力減小材料及模製材料均包含填料時）。在一些實施例中，應力減小材料的填料負載為模製材料的填料負載的約0%至約90%。舉例而言，應力減小材料可具有在約0%至約78%範圍內的填料負載，且模製材料可具有在約75%至約92%範圍內的填料負載。
緩衝層108的應力減小材料具有比包封體110的模製材料更小的平均填料粒徑（當應力減小材料及模製材料均包含填料時）。在一些實施例中，應力減小材料的平均填料粒徑為模製材料的平均值填料粒徑的約0.2%至約60%。舉例而言，應力減小材料可具有在約0.01微米至約10微米範圍內的平均填料粒徑，且模製材料可具有在約5微米至約50微米範圍內的平均填料粒徑。
緩衝層108的應力減小材料具有比包封體110的模製材料更大的伸長率。在一些實施例中，應力減小材料的伸長率為模製材料的伸長率的約120%至約5000%。舉例而言，應力減小材料可具有在約2%δ至約100%δ範圍內的伸長率，且模製材料可具有在約1.2%δ至約5%δ範圍內的伸長率。
以上文所論述的範圍內的楊氏模數、CTE、填料負載、平均填料粒徑以及伸長率形成緩衝層108的應力減小材料及包封體110的模製材料允許緩衝層108足夠緩衝來自包封體110的應力，以避免在外邊緣50E處損壞積體電路元件50及/或晶圓70。以上文所論述的範圍之外的楊氏模數、CTE、填料負載、平均填料粒徑或伸長率形成緩衝層108的應力減小材料及包封體110的模製材料可能不允許緩衝層108足夠緩衝來自包封體110的應力以避免在外邊緣50E處損壞積體電路元件50及/或晶圓70。
除上文所論述的不同物性以外，緩衝層108及包封體110均具有與介電層58、介電層78不同的物性。具體而言，介電層58、介電層78的介電材料具有比緩衝層108的應力減小材料及包封體110的模製材料兩者更大的楊氏模數及更小的CTE。在一些實施例中，模製材料的楊氏模數為介電材料的楊氏模數的約3%至約50%，且應力減小材料的楊氏模數為介電材料的楊氏模數的約6%至約30%。在一些實施例中，模製材料的CTE為介電材料的CTE的約500%至約2500%，且應力減小材料的CTE為介電材料的CTE的約3000%至約30000%。繼續上述實例，介電材料可具有在約30 GPa至約300 GPa範圍內的楊氏模數，且可具有在約0.3 ppm/℃至約5 ppm/℃範圍內的CTE。
在圖5中，中間結構經翻轉（未示出）以準備處理基板72的背側70B。中間結構可置放於載板112上或其他適合的支撐結構上以用於後續處理。舉例而言，載板112可貼合至包封體110。載板112可藉由釋放層貼合至包封體110。釋放層可由聚合物類材料形成，所述釋放層可在處理之後與載板112一起自結構移除。在一些實施例中，載板112為諸如塊狀半導體（bulk semiconductor）或玻璃基板的基板。在一些實施例中，釋放層為在加熱時損失其黏著性的環氧類熱釋放材料，諸如光-熱轉換（light-to-heat-conversion；LTHC）釋放塗層。
在圖6中，薄化基板72以暴露出導通孔80。導通孔80的暴露可藉由薄化製程（諸如研磨製程、化學機械研磨（CMP）、回蝕、其組合或類似者）完成。在所示出的實施例中，執行凹入製程以使基板72的背表面凹入，而使得導通孔80在晶圓70的背側70B處突出。凹入製程可為例如合適的回蝕製程、化學機械研磨（CMP）或類似者。在一些實施例中，用於暴露導通孔80的薄化製程包括CMP，且導通孔80由於在CMP期間發生的凹入（dishing）而在晶圓70的背側70B處突出。絕緣層114隨後形成於基板72的背表面上，從而包圍導通孔80的突出部分。在一些實施例中，絕緣層114由含矽絕緣體（諸如氮化矽、氧化矽、氮氧化矽或類似者）形成，且可藉由合適的沈積方法（諸如旋轉塗佈、CVD、電漿增強CVD（plasma-enhanced CVD；PECVD）、高密度電漿CVD（high density plasma CVD；HDP-CVD）或類似者）形成。最初，絕緣層114可埋住導通孔80。移除製程可應用於各種層以移除導通孔80上的多餘材料。移除製程可為平坦化製程，諸如化學機械研磨（CMP）、回蝕、其組合或類似者。在平坦化之後，導通孔80及絕緣層114的暴露表面為共面的（在製程變化內）且在晶圓70的背側70B處暴露出。在另一實施例中，省略絕緣層114，且基板72及導通孔80的暴露表面為共面的（在製程變化內）。
在圖7中，凸塊下金屬（under bump metallurgy；UBM）132形成於導通孔80及絕緣層114（或基板72，當省略絕緣層114時）的暴露表面上。作為形成UBM 132的實例，晶種層（未示出）形成於導通孔80及絕緣層114/基板72的暴露表面上。在一些實施例中，晶種層為金屬層，其可為單一層或包含由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及鈦層上的銅層。可使用例如PVD或類似者形成晶種層。隨後在晶種層上形成光阻且使所述光阻圖案化。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以用於圖案化。光阻的圖案對應於UBM 132。圖案化形成穿過光阻的開口以暴露出晶種層。導電材料接著形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由諸如電鍍、無電電鍍或類似者的鍍覆形成。導電材料可包含金屬，諸如銅、鈦、鎢、鋁或類似者。隨後，移除光阻以及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程（諸如使用氧電漿或類似者）移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成UBM 132。
此外，導電連接件136形成於UBM 132上。導電連接件136可為球柵陣列（ball grid array；BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（C4）凸塊、微凸塊、化學鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique；ENEPIG）形成的凸塊或類似者。導電連接件136可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件136藉由經由蒸鍍、電鍍、印刷、焊料轉移、植球或類似者初始地形成焊料層來形成。一旦焊料層已形成於結構上，則可執行回焊以便將材料成形為所要凸塊形狀。在另一實施例中，導電連接件136包括藉由濺鍍、印刷、電鍍、無電電鍍、CVD或類似者形成的金屬柱（諸如銅柱）。金屬柱可不含焊料且具有實質上垂直的側壁。在一些實施例中，金屬頂蓋層形成於金屬柱的頂部上。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似者或其組合，且可藉由鍍覆製程形成。
在圖8中，執行載體剝離以自包封體110分離（剝離）載板112。在載板112藉由釋放層貼合至包封體110的實施例中，剝離包括在釋放層上投射光（諸如雷射光或紫外（ultraviolet；UV）光），以使得釋放層在光的熱下分解從而可移除載板112。隨後翻轉結構且置放於載帶（tape；未示出）上。
隨後使包封體110薄化以暴露積體電路元件50。積體電路元件50的暴露可藉由薄化製程（諸如研磨製程、化學機械研磨（CMP）、回蝕、其組合或類似者）完成。在薄化製程之後，包封體110及積體電路元件50的頂表面為共面的（在製程變化內）。執行薄化直至已移除所要量的包封體110為止。儘管緩衝層108保護外邊緣50E不受應力影響，但相比於緩衝層108，包封體110為所得的積體電路封裝100提供更全面的保護。因此，在薄化之後保留足夠的包封體110，使得積體電路封裝100含有比緩衝層108更多的包封體110（按體積計）。在一些實施例中，緩衝層108的體積為包封體110的體積的約2%至約10%。舉例而言，在每一積體電路封裝100中，當包封體110具有約13立方公釐的體積時，緩衝層108可具有在約0.26立方公釐至約1.3立方公釐範圍內的體積。在此實施例中，嵌條部分108F及間隙部分108G（參看圖3）以及包封體110的頂表面亦為共面的（在製程變化內）。在其他實施例中，緩衝層108的頂表面中的一些或全部配置於包封體110的頂表面下方。
在圖9中，藉由沿例如封裝區100A、封裝區100B之間的切割道區切割來執行單體化製程。單體化製程可包括鋸切、分割或類似者。舉例而言，單體化製程可包括鋸切絕緣層114、包封體110、介電層78、內連線結構74以及基板72。單體化製程使封裝區100A、封裝區100B彼此單體化。所得的單體化的積體電路封裝100來自封裝區100A、封裝區100B中的一者。單體化製程自晶圓70及絕緣層114（若存在）的單體化部分形成中介板140。積體電路封裝100中的每一者包括中介板140。作為單體化製程的結果，中介板140及包封體110的外側壁橫向地共端（coterminous）（在製程變化內）。
積體電路封裝100隨後翻轉且藉由導電連接件136貼合至封裝基板200。封裝基板200包括基板芯202，所述基板芯202可由諸如矽、鍺、金剛石或類似者的半導體材料製成。替代地，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等的組合以及類似者。另外，基板芯202可為SOI基板。一般而言，SOI基板包括半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代實施例中，基板芯202為諸如玻璃纖維強化樹脂芯（fiberglass reinforced resin core）的絕緣芯。一種實例芯材料為諸如FR4的玻璃纖維樹脂。芯材料的替代方案包含雙馬來亞醯胺-三嗪（bismaleimide-triazine；BT）樹脂，或可替代地包含其他印刷電路板（printed circuit board；PCB）材料或膜。諸如味素累積膜（Ajinomoto build-up film；ABF）的累積膜（bulid-up film）或其他疊層物可用於基板芯202。
基板芯202可包括主動元件及被動元件（未示出）。諸如電晶體、電容器、電阻器、此等的組合以及類似者的元件可用於產生用於系統的設計的結構及功能需求。可使用任何合適的方法來形成元件。
基板芯202亦可包括金屬化層及通孔（未示出），以及金屬化層及通孔上的接合墊204。金屬化層可形成於主動元件及被動元件上，且經設計以連接各種元件以形成功能電路。金屬化層可由介電材料（例如，低k介電材料）及導電材料（例如，銅）的交替層形成，其中通孔使導電材料層內連且可經由任何合適的製程（諸如沈積、金屬鑲嵌、雙金屬鑲嵌或類似者）來形成。在一些實施例中，基板芯202實質上不含主動元件及被動元件。
導電連接件136經回焊以將UBM 132貼合至接合墊204。導電連接件136將包括內連線結構74的金屬化圖案的積體電路封裝100連接至包括基板芯202中的金屬化層的封裝基板200。因此，封裝基板200電性連接至積體電路元件50。在一些實施例中，被動元件（例如表面安裝元件（surface mount device；SMD）；未示出）可在積體電路封裝100安裝於封裝基板200上之前貼合至積體電路封裝100（例如接合至UBM 132）。在此類實施例中，被動元件可接合至積體電路封裝100的與導電連接件136相同的表面。在一些實施例中，被動元件（例如，SMD；未示出）可貼合至封裝基板200，例如，貼合至接合墊204。
在一些實施例中，底部填充物206形成於積體電路封裝100與封裝基板200之間，從而包圍導電連接件136及UBM 132。底部填充物206可在貼合積體電路封裝100之後藉由毛細流動製程（capillary flow process）形成，或可在貼合積體電路封裝100之前藉由合適的沈積方法形成。底部填充物206可為自封裝基板200延伸至中介板140（例如絕緣層114）的連續材料。底部填充物206的材料與緩衝層108的應力減小材料不同，且藉由與緩衝層108的應力減小材料不同的方法形成。
可選地，散熱器208貼合至積體電路封裝100。散熱器208可由諸如鋼、不鏽鋼、銅、類似者或其組合的具有高導熱性的材料形成。散熱器208保護積體電路封裝100且形成熱路徑以自積體電路封裝100的各種組件（例如積體電路元件50）傳導熱量。散熱器208與積體電路元件50、包封體110接觸，且可選地與緩衝層108接觸。
圖10為根據一些實施例的積體電路封裝100的剖面圖。此實施例與圖9所描述的實施例類似，不同之處在於間隙部分108G具有凹形頂表面，而嵌條部分108F具有直的頂表面。因此，間隙部分108G的頂表面的至少一部分配置於包封體110的頂表面下方且埋在包封體110的頂表面之下。藉由分配比圖9的實施例更少的緩衝層108的應力減小材料，間隙部分108G可形成有凹形頂表面。舉例而言，在此實施例中，緩衝層108的體積可為圖9的實施例中的緩衝層108的體積的約70%至約95%。
圖11為根據一些實施例的積體電路封裝100的剖面圖。此實施例與圖10所描述的實施例類似，不同之處在於緩衝層108僅在積體電路元件50的側壁部分地向上延伸，使得積體電路元件50的側壁的部分暴露於包封體110。具體而言，緩衝層108覆蓋內連線結構54的側壁及半導體基板52的側壁的一部分（參看圖1）。因此，嵌條部分108F及間隙部分108G的頂表面配置於包封體110的頂表面下方且埋在包封體110的頂表面之下。藉由分配比圖10的實施例更少的緩衝層108的應力減小材料，緩衝層108可形成為僅在積體電路元件50的側壁部分地向上延伸。舉例而言，在此實施例中，緩衝層108的體積可為圖10的實施例中的緩衝層108的體積的約50%至約80%。此外，緩衝層108的厚度T1 大於介電層78的厚度T2 ，此可有助於進一步減小外邊緣50E處的應力。
圖12為根據一些實施例的積體電路封裝100的剖面圖。此實施例與圖10所描述的實施例類似，不同之處在於嵌條部分108F及間隙部分108G各自具有凹形頂表面。因此，間隙部分108G的頂表面的至少一部分配置於包封體110的頂表面下方且埋在包封體110的頂表面之下。藉由分配比圖10的實施例更少的緩衝層108的應力減小材料及/或藉由在應力減小材料中包含界面活性劑，嵌條部分108F及間隙部分108G可形成有凹形頂表面。舉例而言，在此實施例中，緩衝層108的體積可為圖10的實施例中的緩衝層108的體積的約50%至約70%。此外，在此實施例中，緩衝層108在積體電路元件50的側壁完全向上延伸，使得積體電路元件50的側壁的任何部分均不暴露於包封體110。具體而言，緩衝層108覆蓋內連線結構54的側壁及半導體基板52的側壁（參看圖1）。
圖13為根據一些實施例的積體電路封裝100的剖面圖。此實施例與圖12所描述的實施例類似，不同之處在於緩衝層108僅在積體電路元件50的側壁部分地向上延伸，使得積體電路元件50的側壁的部分暴露於包封體110。具體而言，緩衝層108覆蓋內連線結構54的側壁及半導體基板52的側壁的一部分（參看圖1）。因此，嵌條部分108F及間隙部分108G的頂表面配置於包封體110的頂表面下方且埋在包封體110的頂表面之下。藉由分配比圖12的實施例更少的緩衝層108的應力減小材料，緩衝層108可形成為僅在積體電路元件50的側壁部分地向上延伸。舉例而言，在此實施例中，緩衝層108的體積可為圖12的實施例中的緩衝層108的體積的約50%至約80%。緩衝層108的厚度T1 大於介電層78的厚度T2 ，此可有助於進一步減小外邊緣50E處的應力。
圖14為根據一些實施例的積體電路封裝100的剖面圖。此實施例與圖9所描述的實施例類似，不同之處在於緩衝層108至少部分地配置於中介板140與積體電路元件50中的每一者之間。積體電路元件50具有錐形側壁（tapered sidewall），其寬度在自積體電路元件50的背側延伸至積體電路元件50的前側的方向上減少。積體電路元件50可藉由在將積體電路元件50接合至中介板140之前在半導體基板52及/或內連線結構54（參看圖1）的邊緣處執行鋸邊製程（trimming process）而形成有錐形側壁。鋸邊製程可包括機械、雷射或電漿鋸切製程。形成具有錐形側壁的積體電路元件50可有助於進一步減小外邊緣50E處的應力。
圖15為根據一些實施例的積體電路封裝100的剖面圖。此實施例與圖9所描述的實施例類似，不同之處在於將多個積體電路封裝100貼合至相同的封裝基板200，且將相同的散熱器208貼合至積體電路封裝100中的每一者。在實施例中，所得元件為多晶片模組（multi-chip module；MCM）封裝，但應瞭解，實施例可應用於其他3DIC封裝。相同的底部填充物206可形成於封裝基板200與積體電路封裝100中的每一者之間。
圖16A至圖16E為根據各種實施例的積體電路封裝100的俯視圖。示出緩衝層108的若干佈局。如俯視圖中所繪示，積體電路元件50具有四個角50C及四個側壁50S，其中每一側壁50S在兩個角50C之間延伸。如亦更清晰地繪示，積體電路元件50A可在多個方向上具有比積體電路元件50B更大的寬度。
在圖16A中，嵌條部分108F及間隙部分108G兩者在薄化包封體110之後經由包封體110暴露。圖16A可為圖9的實施例的俯視圖。在此實施例中，暴露的嵌條部分108F圍繞積體電路元件50的角50C延伸且沿積體電路元件50的側壁50S連續地延伸。
在圖16B中，嵌條部分108F中的一些在薄化包封體110之後經由包封體110暴露，但間隙部分108G在薄化包封體110之後保持經覆蓋。圖16B可為圖10的實施例的俯視圖。在此實施例中，暴露的嵌條部分108F圍繞積體電路元件50的角50C延伸且沿積體電路元件50的側壁50S不連續地延伸。
在16C中，嵌條部分108F及間隙部分108G均未經由包封體110暴露，而是在薄化包封體110之後保持經覆蓋。圖16C可為圖11及圖13的實施例的俯視圖。
在圖16D中，間隙部分108G在薄化包封體110之後經由包封體110暴露，但嵌條部分108F在薄化包封體110之後保持經覆蓋。圖16D可為圖9的實施例的俯視圖。
在圖16E中，嵌條部分108F中的一些在薄化包封體110之後經由包封體110暴露，但間隙部分108G在薄化包封體110之後保持經覆蓋。圖16E為圖10的實施例的俯視圖。在此實施例中，緩衝層108包括由第一聚合物材料形成的第一部分108A及由第二聚合物材料形成的第二部分108B。第一部分108A可為圍繞積體電路元件50的外邊緣50E的彼等部分。第二部分108B可為圍繞積體電路元件50的內邊緣50N的彼等部分。第一聚合物材料及第二聚合物材料各自與上文針對圖3所論述的應力減小材料類似，且為彼此不同的應力減小材料。舉例而言，第一部分108A可具有比第二部分108B更小的楊氏模數/CTE。換言之，在圖16A至圖16D的實施例中，緩衝層108包含單一應力減小材料，但在圖16E的實施例中，緩衝層108包含多種應力減小材料。可基於積體電路封裝100的各種區域中的所要應力緩衝量來選擇應力減小材料。
實施例可實現優勢。當積體電路元件50藉由混合接合直接接合至晶圓70時，包封體110在高溫下的膨脹可在積體電路元件50上（尤其在外邊緣50E處）施加應力，而所述應力會損壞積體電路元件50及/或晶圓70。舉例而言，介電層58、介電層78可能出現分層。緩衝層108有助於緩衝積體電路封裝100的經歷高應力的區域（諸如積體電路元件50的外邊緣50E）中的應力。具體而言，緩衝層108由在高溫下膨脹小於包封體110的應力減小材料形成，且由此有助於緩衝由包封體110在膨脹期間施加的應力。積體電路封裝100可在製造期間（諸如在測試期間）反覆經受高溫。形成緩衝層108有助於在高溫處理期間保護積體電路封裝100，從而提高積體電路封裝100的良率及可靠性。
在實施例中，一種形成積體電路封裝的方法包括：使用介電質對介電質接合且使用金屬對金屬接合將第一積體電路元件及第二積體電路元件接合至中介板；圍繞第一積體電路元件及第二積體電路元件形成應力減小材料，應力減小材料具有第一楊氏模數；使用模製材料包封應力減小材料、第一積體電路元件以及第二積體電路元件，模製材料具有第二楊氏模數，第一楊氏模數小於第二楊氏模數；以及薄化模製材料以暴露第一積體電路元件及第二積體電路元件。
在所述形成積體電路封裝的方法的一些實施例中，應力減小材料包含第一聚合物材料且模製材料包含第二聚合物材料，第一聚合物材料與第二聚合物材料不同。在所述形成積體電路封裝的方法的一些實施例中，應力減小材料更包含第一填料且模製材料更包含第二填料。在所述形成積體電路封裝的方法的一些實施例中，應力減小材料更包含界面活性劑。在所述形成積體電路封裝的方法的一些實施例中，第一聚合物材料為第一環氧樹脂、聚醯亞胺類材料、苯環丁烷（BCB）類材料、矽酮材料或丙烯酸材料，且第二聚合物材料為第二環氧樹脂。在所述形成積體電路封裝的方法的一些實施例中，應力減小材料具有間隙部分及嵌條部分，間隙部分配置於第一積體電路元件與第二積體電路元件之間，嵌條部分沿第一積體電路元件及第二積體電路元件的外邊緣配置，其中間隙部分在薄化模製材料之後暴露，且嵌條部分在薄化模製材料之後暴露。在所述形成積體電路封裝的方法的一些實施例中，應力減小材料具有間隙部分及嵌條部分，間隙部分配置於第一積體電路元件與第二積體電路元件之間，嵌條部分沿第一積體電路元件及第二積體電路元件的外邊緣配置，其中間隙部分在薄化模製材料之後保持經覆蓋，且嵌條部分在薄化模製材料之後保持經覆蓋。在所述形成積體電路封裝的方法的一些實施例中，應力減小材料具有間隙部分及嵌條部分，間隙部分配置於第一積體電路元件與第二積體電路元件之間，嵌條部分沿第一積體電路元件及第二積體電路元件的外邊緣配置，其中間隙部分在薄化模製材料之後暴露，且嵌條部分在薄化模製材料之後保持經覆蓋。在所述形成積體電路封裝的方法的一些實施例中，應力減小材料具有間隙部分及嵌條部分，間隙部分配置於第一積體電路元件與第二積體電路元件之間，嵌條部分沿第一積體電路元件及第二積體電路元件的外邊緣配置，其中間隙部分在薄化模製材料之後保持經覆蓋，且其中嵌條部分在薄化模製材料之後暴露。
在實施例中，一種積體電路封裝包括：中介板；第一積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至中介板；第二積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至中介板；緩衝層，圍繞第一積體電路元件及第二積體電路元件，緩衝層包含具有第一楊氏模數的應力減小材料；以及包封體，圍繞緩衝層、第一積體電路元件以及第二積體電路元件，包封體包含具有第二楊氏模數的模製材料，第一楊氏模數小於第二楊氏模數。
在所述積體電路封裝的一些實施例中，應力減小材料具有第一熱膨脹係數且模製材料具有第二熱膨脹係數，第一熱膨脹係數大於第二熱膨脹係數。在所述積體電路封裝的一些實施例中，應力減小材料包含具有第一填料負載的第一填料且模製材料包含具有第二填料負載的第二填料，第一填料負載小於第二填料負載。在所述積體電路封裝的一些實施例中，應力減小材料包含具有第一平均填料粒徑的第一填料，且模製材料包含具有第二平均填料粒徑的第二填料，第一平均填料粒徑小於第二平均填料粒徑。在所述積體電路封裝的一些實施例中，應力減小材料具有第一伸長率且模製材料具有第二伸長率，第一伸長率小於第二伸長率。
在實施例中，一種積體電路封裝包括：中介板；第一積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至中介板；第二積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至中介板；緩衝層，具有間隙部分及嵌條部分，間隙部分配置於第一積體電路元件與第二積體電路元件之間，嵌條部分沿第一積體電路元件及第二積體電路元件的外邊緣配置；以及包封體，圍繞緩衝層、第一積體電路元件以及第二積體電路元件，包封體具有與緩衝層不同的楊氏模數、不同的熱膨脹係數、不同的填料負載、不同的平均填料粒徑，以及不同的伸長率。
在所述積體電路封裝的一些實施例中，間隙部分具有凹形頂表面且嵌條部分具有凹形頂表面。在所述積體電路封裝的一些實施例中，間隙部分具有直的頂表面且嵌條部分具有直的頂表面。在所述積體電路封裝的一些實施例中，間隙部分具有凹形頂表面且嵌條部分具有直的頂表面。在所述積體電路封裝的一些實施例中，緩衝層包含單一應力減小材料。在所述積體電路封裝的一些實施例中，緩衝層包含多種應力減小材料。
前文概述若干實施例的特徵，使得所屬技術領域中具有通常知識者可較佳地理解本揭露內容的態樣。所屬技術領域中具有通常知識者應瞭解，其可容易地使用本揭露內容作為設計或修改用於進行本文中所引入的實施例的相同目的及/或實現相同優勢的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範圍，且所屬技術領域中具有通常知識者可在不脫離本揭露內容的精神及範圍的情況下在本文中作出各種改變、替代以及更改。
50、50A、50B:積體電路元件 50C:角 50E:外邊緣 50F、70F:前側 50N:內邊緣 50S:側壁 52:半導體基板 54、74:內連線結構 56、76:晶粒連接件 58、78:介電層 70:晶圓 70B:背側 72:基板 80:導通孔 100:積體電路封裝 100A、100B:封裝區 108:緩衝層 108A:第一部分 108B:第二部分 108F:嵌條部分 108G:間隙部分 110:包封體 112:載板 114:絕緣層 132:凸塊下金屬 136:導電連接件 140:中介板 200:封裝基板 202:基板芯 204:接合墊 206:底部填充物 208:散熱器 T1 、T2 :厚度
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，出於論述清楚起見，可任意增大或減小各種特徵的尺寸。 圖1為積體電路元件的剖面圖。 圖2至圖9為根據一些實施例的在用於形成積體電路封裝的製程期間的中間步驟的剖面圖。 圖10為根據一些實施例的積體電路封裝的剖面圖。 圖11為根據一些實施例的積體電路封裝的剖面圖。 圖12為根據一些實施例的積體電路封裝的剖面圖。 圖13為根據一些實施例的積體電路封裝的剖面圖。 圖14為根據一些實施例的積體電路封裝的剖面圖。 圖15為根據一些實施例的積體電路封裝的剖面圖。 圖16A至圖16E為根據各種實施例的積體電路封裝的俯視圖。
50A、50B:積體電路元件
50E:外邊緣
72:基板
74:內連線結構
78:介電層
100:積體電路封裝
108:緩衝層
108F:嵌條部分
108G:間隙部分
110:包封體
114:絕緣層
132:凸塊下金屬
136:導電連接件
140:中介板
200:封裝基板
202:基板芯
204:接合墊
206:底部填充物
208:散熱器

Claims (20)

  1. 一種形成積體電路封裝的方法，包括： 使用介電質對介電質接合且使用金屬對金屬接合將第一積體電路元件及第二積體電路元件接合至中介板； 圍繞所述第一積體電路元件及所述第二積體電路元件形成應力減小材料，所述應力減小材料具有第一楊氏模數； 使用模製材料包封所述應力減小材料、所述第一積體電路元件以及所述第二積體電路元件，所述模製材料具有第二楊氏模數，所述第一楊氏模數小於所述第二楊氏模數；以及 薄化所述模製材料以暴露所述第一積體電路元件及所述第二積體電路元件。
  2. 如請求項1所述的形成積體電路封裝的方法，其中所述應力減小材料包括第一聚合物材料且所述模製材料包括第二聚合物材料，所述第一聚合物材料與所述第二聚合物材料不同。
  3. 如請求項2所述的形成積體電路封裝的方法，其中所述應力減小材料更包括第一填料且所述模製材料更包括第二填料。
  4. 如請求項2所述的形成積體電路封裝的方法，其中所述應力減小材料更包括界面活性劑。
  5. 如請求項2所述的形成積體電路封裝的方法，其中所述第一聚合物材料為第一環氧樹脂、聚醯亞胺類材料、苯環丁烷（BCB）類材料、矽酮材料或丙烯酸材料，且所述第二聚合物材料為第二環氧樹脂。
  6. 如請求項1所述的形成積體電路封裝的方法，其中所述應力減小材料具有間隙部分及嵌條部分，所述間隙部分配置於所述第一積體電路元件與所述第二積體電路元件之間，所述嵌條部分沿所述第一積體電路元件及所述第二積體電路元件的外邊緣配置，其中所述間隙部分在薄化所述模製材料之後暴露，且所述嵌條部分在薄化所述模製材料之後暴露。
  7. 如請求項1所述的形成積體電路封裝的方法，其中所述應力減小材料具有間隙部分及嵌條部分，所述間隙部分配置於所述第一積體電路元件與所述第二積體電路元件之間，所述嵌條部分沿所述第一積體電路元件及所述第二積體電路元件的外邊緣配置，其中所述間隙部分在薄化所述模製材料之後保持經覆蓋，且所述嵌條部分在薄化所述模製材料之後保持經覆蓋。
  8. 如請求項1所述的形成積體電路封裝的方法，其中所述應力減小材料具有間隙部分及嵌條部分，所述間隙部分配置於所述第一積體電路元件與所述第二積體電路元件之間，所述嵌條部分沿所述第一積體電路元件及所述第二積體電路元件的外邊緣配置，其中所述間隙部分在薄化所述模製材料之後暴露，且所述嵌條部分在薄化所述模製材料之後保持經覆蓋。
  9. 如請求項1所述的形成積體電路封裝的方法，其中所述應力減小材料具有間隙部分及嵌條部分，所述間隙部分配置於所述第一積體電路元件與所述第二積體電路元件之間，所述嵌條部分沿所述第一積體電路元件及所述第二積體電路元件的外邊緣配置，其中所述間隙部分在薄化所述模製材料之後保持經覆蓋，且所述嵌條部分在薄化所述模製材料之後暴露。
  10. 一種積體電路封裝，包括： 中介板； 第一積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至所述中介板； 第二積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至所述中介板； 緩衝層，圍繞所述第一積體電路元件及所述第二積體電路元件，所述緩衝層包括具有第一楊氏模數的應力減小材料；以及 包封體，圍繞所述緩衝層、所述第一積體電路元件以及所述第二積體電路元件，所述包封體包括具有第二楊氏模數的模製材料，所述第一楊氏模數小於所述第二楊氏模數。
  11. 如請求項10所述的積體電路封裝，其中所述應力減小材料具有第一熱膨脹係數且所述模製材料具有第二熱膨脹係數，所述第一熱膨脹係數大於所述第二熱膨脹係數。
  12. 如請求項10所述的積體電路封裝，其中所述應力減小材料包括具有第一填料負載的第一填料且所述模製材料包括具有第二填料負載的第二填料，所述第一填料負載小於所述第二填料負載。
  13. 如請求項10所述的積體電路封裝，其中所述應力減小材料包括具有第一平均填料粒徑的第一填料，且所述模製材料包括具有第二平均填料粒徑的第二填料，所述第一平均填料粒徑小於所述第二平均填料粒徑。
  14. 如請求項10所述的積體電路封裝，其中所述應力減小材料具有第一伸長率且所述模製材料具有第二伸長率，所述第一伸長率小於所述第二伸長率。
  15. 一種積體電路封裝，包括： 中介板； 第一積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至所述中介板； 第二積體電路元件，使用介電質對介電質接合且使用金屬對金屬接合來接合至所述中介板； 緩衝層，具有間隙部分及嵌條部分，所述間隙部分配置於所述第一積體電路元件與所述第二積體電路元件之間，所述嵌條部分沿所述第一積體電路元件及所述第二積體電路元件的外邊緣配置；以及 包封體，圍繞所述緩衝層、所述第一積體電路元件以及所述第二積體電路元件，所述包封體具有與所述緩衝層不同的楊氏模數、不同的熱膨脹係數、不同的填料負載、不同的平均填料粒徑，以及不同的伸長率。
  16. 如請求項15所述的積體電路封裝，其中所述間隙部分具有凹形頂表面且所述嵌條部分具有凹形頂表面。
  17. 如請求項15所述的積體電路封裝，其中所述間隙部分具有直的頂表面且所述嵌條部分具有直的頂表面。
  18. 如請求項15所述的積體電路封裝，其中所述間隙部分具有凹形頂表面且所述嵌條部分具有直的頂表面。
  19. 如請求項15所述的積體電路封裝，其中所述緩衝層包括單一應力減小材料。
  20. 如請求項15所述的積體電路封裝，其中所述緩衝層包括多種應力減小材料。
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