CN109427702B - 散热器件和方法 - Google Patents

散热器件和方法 Download PDF

Info

Publication number
CN109427702B
CN109427702B CN201810461232.5A CN201810461232A CN109427702B CN 109427702 B CN109427702 B CN 109427702B CN 201810461232 A CN201810461232 A CN 201810461232A CN 109427702 B CN109427702 B CN 109427702B
Authority
CN
China
Prior art keywords
dummy
die
substrate
integrated circuit
die stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810461232.5A
Other languages
English (en)
Other versions
CN109427702A (zh
Inventor
林宗澍
洪文兴
李虹錤
陈琮瑜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109427702A publication Critical patent/CN109427702A/zh
Application granted granted Critical
Publication of CN109427702B publication Critical patent/CN109427702B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

在实施例中，器件包括：位于中介层上方并且电连接至中介层的管芯堆叠件，管芯堆叠件包括最顶集成电路管芯，最顶集成电路管芯包括：具有前侧和与前侧相对的背侧的衬底，衬底的前侧包括有源表面；从衬底的背侧至少部分地延伸至衬底内的伪衬底通孔(TSV)，伪TSV与有源表面电隔离；位于最顶集成电路管芯上方的热界面材料；以及位于热界面材料中的伪连接件，热界面材料围绕伪连接件，伪连接件与最顶集成电路管芯的有源表面电隔离。本发明的实施例还涉及散热器件和方法。

Description

散热器件和方法
技术领域
本发明的实施例涉及散热器件和方法。
背景技术
在集成电路的封装中，可以通过接合来堆叠半导体管芯，并且可以将半导体管芯接合至其它封装组件，诸如中介层以及封装衬底。产生的封装件称为三维集成电路(3DIC)。3DIC中的散热具有挑战性。
有效地消散3DIC的内部管芯中产生的热量可能存在瓶颈。在典型的3DIC中，在热量传导至散热器之前，内部管芯中产生的热量必须消散到外部组件。然而，在堆叠管芯和外部组件之间，存在不能有效地传导热量的其它材料，诸如底部填充物、模塑料等。因此，热量可能被捕获在底部堆叠管芯的内部区域中，并且引起尖端局部温度峰值(有时称为热点)。此外，由高功耗管芯产生的热量引起的热点可能导致周围管芯的热串扰问题，从而对周围管芯的性能和整个3DIC封装件的可靠性产生负面影响。
发明内容
本发明的实施例提供了一种半导体器件，包括：管芯堆叠件，位于中介层上方并且电连接至所述中介层，所述管芯堆叠件包括最顶集成电路管芯，所述最顶集成电路管芯包括：衬底，具有前侧和与所述前侧相对的背侧，所述衬底的前侧包括有源表面；伪衬底通孔(TSV)，从所述衬底的背侧至少部分地延伸至所述衬底内，所述伪衬底通孔与所述有源表面电隔离；热界面材料，位于所述最顶集成电路管芯上方；以及伪连接件，位于所述热界面材料中，所述热界面材料围绕所述伪连接件，所述伪连接件与所述最顶集成电路管芯的有源表面电隔离。
本发明的另一实施例提供了一种制造半导体器件的方法，包括：将管芯堆叠件附接至中介层；用密封剂密封所述管芯堆叠件；平坦化所述密封剂，所述密封剂与所述管芯堆叠件的顶面齐平；在所述管芯堆叠件的最顶集成电路管芯中形成凹槽，所述最顶集成电路管芯包括具有有源表面和背面的衬底，所述衬底具有第一高度，所述凹槽从所述衬底的背面延伸第一深度，所述第一深度小于所述第一高度；用第一导电材料填充所述凹槽以形成伪衬底通孔(TSV)；在所述伪衬底通孔上形成伪连接件；将热界面材料分配在所述最顶集成电路管芯上，所述热界面材料围绕所述伪连接件；以及将散热器附接至所述最顶集成电路管芯，所述散热器覆盖并且围绕所述管芯堆叠件和所述中介层。
本发明的又一实施例提供了一种制造半导体器件的方法，包括：将管芯堆叠件附接至中介层；用密封剂密封所述管芯堆叠件；平坦化所述密封剂，所述密封剂与所述管芯堆叠件的顶面齐平；将所述热界面材料分配在所述管芯堆叠件上；在所述热界面材料中形成伪连接件，所述伪连接件的所有侧均由非导电材料围绕；以及将散热器附接至所述管芯堆叠件，所述散热器覆盖并且围绕所述管芯堆叠件和所述中介层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的集成电路管芯的截面图。
图2A和图2B是根据一些实施例的管芯堆叠件的截面图。
图3、图4、图5、图6、图7、图8A、图8B、图9、图10、图11、图12、图13、图14和图15是根据一些实施例的用于形成半导体器件的工艺期间的中间阶段的各个视图。
图16示出了根据一些其它实施例的半导体器件。
图17示出了根据一些其它实施例的半导体器件。
图18示出了根据一些其它实施例的半导体器件。
图19示出了根据一些其它实施例的半导体器件。
图20示出了根据一些其它实施例的半导体器件。
图21示出了根据一些其它实施例的伪连接件。
图22示出了根据一些其它实施例的用于制造半导体器件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，在中介层上形成管芯堆叠件，并且可选地在管芯堆叠件中形成伪通孔。在管芯堆叠件上方形成热界面材料，并且在热界面材料中形成伪连接件。利用热界面材料将散热器附接至管芯堆叠件。形成伪通孔和/或伪连接件可以减小沿着中介层和散热器之间的热路径的热阻，从而减小产生的器件的操作温度。
图1是根据一些实施例的集成电路管芯50的截面图。集成电路管芯50可以是中介层、逻辑器件等。集成电路管芯50包括衬底52、器件54、导电插塞56、层间电介质(ILD)58、互连件60、管芯连接件62和介电材料64。集成电路管芯50可以形成在晶圆(未示出)中，该晶圆可以包括在随后的步骤中分割以形成多个集成电路管芯50的不同器件区域。
衬底52具有有时称为有源侧的正面(例如，图1中朝上的表面)和有时称为无源侧的背面(例如，图1中朝下的表面)。衬底52可以是诸如掺杂或未掺杂的硅的半导体，或绝缘体上半导体(SOI)衬底的有源层。衬底52可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层或梯度衬底的其它衬底。
可以在衬底52的正面中和/或衬底52的正面上形成器件54。器件54可以是晶体管、二极管、电容器、电阻器等。在集成电路管芯50是逻辑管芯的实施例中，器件54包括有源器件。在集成电路管芯50是中介层的实施例中，器件54可以是无源器件或可以被省略，从而使得集成电路管芯50没有有源器件。导电插塞56电和物理连接至器件54。ILD 58围绕器件54和导电插塞56，并且包括一个或多个介电层。
互连件60互连器件54以形成集成电路。可以通过例如衬底52的正面上的介电层中的金属化图案来形成互连件60。金属化图案包括在一个或多个介电层中形成的金属线和通孔。互连件60的金属化图案通过导电插塞56电连接至器件54。
管芯连接件62可以是导电柱(例如，包括诸如铜、铝、钨、镍或它们的合金的金属)，并且机械和电连接至互连件60。可以通过例如镀等形成管芯连接件62。管芯连接件62电连接集成电路管芯50的相应集成电路。
介电材料64位于集成电路管芯50的有源表面上，诸如位于互连件60上。介电材料64横向地密封管芯连接件62，并且介电材料64与集成电路管芯50横向共边界。介电材料64是含硅介电层，并且可以由氧化硅、SiON、SiN等形成，并且可以通过诸如CVD、PECVD、PVD、ALD等的沉积工艺形成。介电材料64可以是互连件60的最顶层。
图2A和图2B是根据一些实施例的管芯堆叠件70A和70B的截面图。管芯堆叠件70A和70B每个均可以具有单一功能(例如，逻辑器件、存储器管芯等)，或可具有多个功能(例如，SoC)。在具体实施例中，管芯堆叠件70A是处理器并且管芯堆叠件70B是存储器模块。此处，管芯堆叠件70A和70B可以可选地称为管芯堆叠件70，其中，对管芯堆叠件70的引用是指管芯堆叠件70A或管芯堆叠件70B。
如图2A所示，管芯堆叠件70A包括两个接合的集成电路管芯50A/50B。管芯堆叠件70A可以是诸如中央处理单元(CPU)、图形处理单元(GPU)、专用集成电路电路(ASIC)等的处理器。在具体实施例中，管芯堆叠件70A是GPU。在一些实施例中，接合第一集成电路管芯50A和第二集成电路管芯50B，从而使得有源表面彼此面对(“面对面”)。第一集成电路管芯50A和第二集成电路管芯50B可以通过混合接合、熔融接合、直接接合、介电接合、金属接合等连接。在一些实施例中，第一集成电路管芯50A是处理器管芯，而第二集成电路管芯50B是界面管芯。界面管芯将处理器管芯桥接至存储器管芯，并且在处理器和存储器管芯之间转换命令
在第一集成电路管芯50A和第二集成电路管芯50B通过混合接合而接合的实施例中，利用诸如每个管芯中的介电材料64的氧化物层形成共价键。在实施接合之前，可以对第一集成电路管芯50A和/或第二集成电路管芯50B实施表面处理，在介电材料64的顶部中形成OH键。下一步，可以实施预接合工艺，其中，将第一集成电路管芯50A和第二集成电路管芯50B的管芯连接件62和介电材料64对准并且按压在一起以形成弱接合。在预接合工艺之后，退火第一集成电路管芯50A和第二集成电路管芯50B以增强弱接合。在退火期间，介电材料64的顶部的OH键断裂，以在第一集成电路管芯50A和第二集成电路管芯50B之间形成Si-O-Si键，从而增强接合。在混合接合期间，在管芯连接件62之间也发生金属接合。
可以形成穿过一个集成电路管芯50的通孔66，从而可以制成外部连接。通孔66可以是硅通孔(TSV)。在所示的实施例中，在第二集成电路管芯50B(例如，界面管芯)中形成通孔66。通孔66延伸穿过相应集成电路管芯50的衬底52，并且可以延伸穿过ILD 58以物理和电连接至互连件60的金属化图案。
如图2B所示，管芯堆叠件70B包括由通孔72连接的多个集成电路管芯50。通孔72可以是例如TSV。管芯堆叠件70B可以是诸如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储数据集(HMC)模块、高带宽存储器(HBM)模块等的存储器器件。在具体实施例中，管芯堆叠件70B是HBM模块。
诸如管芯堆叠件70的管芯堆叠件可以捕获热量，在随后形成的器件封装件中变成热点。具体地，包括处理器件(诸如管芯堆叠件70A)的管芯堆叠件可以具有高功率密度。例如，在管芯堆叠件70A是GPU的实施例中，产生的器件封装件的功率密度可以在从约50W/cm2至约300W/cm2。在操作期间，可能在处理器管芯和界面管芯的界面处捕获热量。
图3至图13是根据一些实施例的用于形成半导体器件300的工艺期间的中间步骤的各个视图。图3至图13是截面图。在图3至图9中，通过将各个集成电路管芯接合至晶圆102形成第一器件封装件100。在实施例中，第一器件封装件100是晶圆上芯片(CoW)封装件，但是应该理解，该实施例可以应用于其它3DIC封装件。图10示出了产生的第一器件封装件100。在图11至图12中，通过将第一器件封装件100安装至衬底形成第二器件封装件200。在实施例中，器件封装件200是衬底上晶圆上芯片(CoWoS)封装件，但是应该理解，该实施例可以应用于其它3DIC封装件。图13示出了采用产生的第二器件封装件200的半导体器件300
晶圆102可以具有形成在其中的各个器件。具体地，可以在可以包括多个器件区域100A和100B(在随后的步骤中被分割以形成第一器件封装件100)的晶圆102中形成中介层、集成电路器件等。
在一些实施例中，在晶圆102中形成中介层。中介层具有用于电连接集成电路管芯中的有源器件(未示出)的互连结构，以形成功能电路。在这样的实施例中，晶圆102包括具有正面(例如，图3中朝上的表面)和背面(例如，图3中朝下的表面)的半导体衬底。互连结构形成在半导体衬底的背面上。在半导体衬底中形成从互连结构延伸至半导体衬底的正面的通孔。通过例如双镶嵌工艺在半导体衬底上的互连结构中形成金属线和通孔。金属线和通孔可以电连接至通孔。中介层可以(或不可以)没有诸如晶体管和二极管的有源器件，并且可以(或不可以)没有诸如电阻器、电感器、电容器等的器件。
虽然本文示出的实施例在其中形成有中介层的晶圆102的上下文中讨论，但是应该理解，可以在晶圆102中形成其它类型的器件。例如，可以在晶圆102中形成诸如逻辑器件的集成电路器件。在这样的实施例中，晶圆102包括具有形成在其中的有源和/或无源器件的半导体衬底。半导体衬底可以是掺杂或未掺杂的硅、或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底中和/或上，并且可以通过由例如半导体衬底上的一个或多个介电层中的金属化图案形成的互连结构互连，以形成集成电路。
在图3中，利用管芯连接件104将管芯堆叠件70附接至晶圆102。在实施例中，可以将一个管芯堆叠件70A(例如GPU)和多个管芯堆叠件70B(例如HBM)放置在晶圆102的每个器件区域上。可以使用例如拾取和放置工具将管芯堆叠件70附接至晶圆102。管芯连接件104可以由诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料形成。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转印、球植等方法形成焊料层来形成管芯连接件104。一旦已经在结构上形成焊料层，则可以实施回流以将管芯连接件104成形为期望的凸块形状。管芯连接件104形成晶圆102上的相应的连接件和管芯堆叠件70之间的接头，并且将晶圆102电连接至管芯堆叠件70。
在图4中，可以在管芯堆叠件70和晶圆102之间形成围绕管芯连接件104的底部填充物106。底部填充物106可以在附接管芯堆叠件70之后通过的毛细管流动工艺形成，或可以在附接管芯堆叠件70之前通过合适的沉积方法形成。
在图5中，在各个组件上形成密封剂108。密封剂108可以是模塑料、环氧树脂等，并且可以通过压缩模塑、传递模塑等施加。可以在晶圆102上形成密封剂108，从而掩埋或覆盖管芯堆叠件70。之后，固化密封剂108。
在图6中，在晶圆102的背侧上形成导电连接件110。可以在形成导电连接件110之前减薄晶圆102的背侧。可以通过化学机械抛光(CMP)、研磨工艺等来完成减薄。导电连接件110电连接至晶圆102的部件(例如，逻辑器件、中介层等)，并且可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。在一些实施例中，通过首先由诸如蒸发、电镀、印刷、焊料转印、球植等常用的方法形成焊料层来形成导电连接件110。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在形成导电连接件110之后，可以将晶圆102放置在带112上以用于随后的处理步骤。
在图7中，减薄密封剂108以暴露管芯堆叠件70的顶面。可以通过CMP、研磨工艺等来完成减薄。在减薄之后，密封剂108与管芯堆叠件70的顶面齐平。
在图8A和图8B中，在管芯堆叠件70中形成凹槽114。图8A是示出在晶圆102的层级处理的截面图，并且图8B是示出在管芯堆叠件70A的层级的详细处理的截面图。凹槽114是之后被填充的衬底通孔(TSV)开口，如以下讨论的。凹槽114形成在管芯堆叠件70的最顶管芯的衬底52中。凹槽114从衬底52的背侧延伸，并且可以形成为完全穿过衬底52或仅部分地延伸至衬底52内。在实施例中，凹槽114仅部分地延伸至衬底52内，从而使得凹槽114从衬底52的背面延伸至小于衬底52的总高度的深度。因此，虽然凹槽114的深度取决于第一器件封装件100的整体设计，在一些实施例中，在衬底52的顶面之下的深度可以在从约50μm至约700μm，例如约300μm的深度。这样的深度允许随后形成的TSV成为用于冷却管芯堆叠件70的良好导热体，同时保持低制造成本。此外，虽然凹槽114的宽度取决于第一器件封装件100的整体设计，但是在一些实施例中，宽度可以在从约10μm至约200μm。可以通过可接受的光刻和蚀刻技术形成凹槽114。例如，可以将合适的光刻胶施加至晶圆102(例如，在密封剂108和管芯堆叠件70上)并且显影光刻胶。之后，显影的光刻胶可以在用于形成凹槽114的蚀刻工艺中用作蚀刻掩模。蚀刻工艺可以是各向异性湿蚀刻或干蚀刻。
一旦已经形成凹槽114，则凹槽114可以填充有衬垫(未单独示出)。衬垫可以是诸如氮化硅、氧化硅、介电聚合物、这些的组合等的介电材料，并且可以通过诸如CVD、氧化、PVD、ALD等的工艺形成。
凹槽114也可以在衬垫上方填充有阻挡层(也未单独示出)。阻挡层可以是诸如氮化钛的导电材料，但是可以可选地利用诸如氮化钽、钛、另一电介质等的其它材料。可以使用诸如PECVD的CVD工艺来形成阻挡层，然而，可以可选地使用诸如溅射或金属有机化学汽相沉积(MOCVD)、ALD等的其它工艺。阻挡层可以形成为与下面的凹槽114的形状一致。
在图9中，在凹槽114中形成导电材料，从而形成伪TSV 116。导电材料可以是铜，但是可以可选地利用诸如铝、钨、合金、掺杂的多晶硅、它们的组合等的其它合适的材料。可以通过在凹槽114中沉积晶种层并且之后将铜电镀至晶种层来形成导电材料，填充或或过填充凹槽114。一旦已经填充凹槽114，则可以通过诸如CMP的研磨工艺去除凹槽114外部的过量的阻挡层和过量的导电材料，但是可以使用任何合适的去除工艺。
在形成导电材料之后，可以实施退火工艺。例如，可以在约400℃的温度下实施热退火约1小时的时间跨度。退火可以增强伪TSV 116和衬底52的界面，并且稳定电镀的导电材料的晶粒结构。
伪TSV 116与周围器件电隔离。虽然伪TSV 116形成在集成电路管芯50的衬底52中，集成电路管芯50本身可以包含器件54，但是伪TSV 116与集成电路管芯50的有源侧电隔离，例如，与集成电路管芯50的器件54电隔离。例如，凹槽114可以形成在集成电路管芯50的衬底52中，从而使得伪TSV 116除了顶侧(例如伪TSV 116的与衬底52的背侧齐平的侧)之外的所有侧均由非导电材料围绕。非导电材料可以是绝缘材料、块状半导体材料(例如，其中不形成器件的半导体材料)等。伪TSV 116可以不物理或电连接至器件54、互连件60的金属等。
虽然伪TSV 116仅示出为形成在管芯堆叠件70A中，但是应该理解，伪TSV 116可以形成在管芯堆叠件70A/70B中的任何一个或全部中。例如，伪TSV 116可以仅形成在管芯堆叠件70A中，仅形成在管芯堆叠件70B或形成在管芯堆叠件70A和70B中。
在图10中，在相应的伪TSV 116上形成伪连接件118。伪连接件118可以形成在每个相应的伪TSV 116上，或伪TSV 116的子集上(例如，伪连接件118可以仅形成在伪TSV 116的子集上并且可以不形成在剩余的伪TSV 116上)。因为伪连接件118形成在伪TSV 116上，所以它们也与衬底52的有源侧电隔离。伪连接件118可以由诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料形成。在所示的实施例中，伪连接件118是由诸如焊料、助焊剂等的可回流材料形成的凸块。伪连接件118可以形成为使得它们仅覆盖相应的伪TSV 116，或可以比伪TSV 116宽，从而使得它们覆盖相应的伪TSV 116并且沿着最顶集成电路管芯50的衬底52的顶面延伸。伪连接件118将伪TSV 116热连接至上面的散热器(如下所示)。伪连接件118足够大，使得在操作期间可以从伪TSV 116转移足够的热量；在实施例中，伪连接件118具有在从约25μm至约100μm(诸如约50μm)的高度。
在图11中，通过分割工艺分割晶圆102和密封剂108，从而形成第一器件封装件100。由于分割工艺，晶圆102被分割成中介层120，其中，第一封装件100的每个均具有中介层120。可以在晶圆102位于带112上时实施分割。沿着例如邻近的器件区域之间(例如，器件区域100A和100B)的划线区域实施分割。在一些实施例中，分割工艺包括锯切工艺、激光工艺或它们的组合。
图12示出了分割之后产生的第一器件封装件100。由于分割工艺，中介层120和密封剂108的边缘是共边界的。换句话说，中介层120的外侧壁具有与密封剂108的外侧壁相同的宽度。
在图13中，通过将第一器件封装件100安装至封装衬底202形成第二器件封装件200。封装衬底202可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用化合物材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等。此外，封装衬底202可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底202基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。用于芯材料的可选物质包括双马来酰亚胺-三嗪BT树脂，或可选地，其它PCB材料或薄膜。诸如ABF的积聚膜或其它层压膜可以用于封装衬底202。
封装衬底202可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于第二器件封装件200的设计的结构和功能需求。可以使用任何合适的方法形成器件。
封装衬底202也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘204。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，其中，互连导电材料层的通孔可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底202基本没有有源和无源器件。
在一些实施例中，回流导电连接件110以将第一器件封装件100附接至接合焊盘204，从而将中介层120接合至封装衬底202。导电连接件110将封装衬底202(包括封装衬底202中的金属化层)电和/或物理连接至第一器件封装件100。在一些实施例中，在安装到封装衬底202(例如，接合至接合焊盘204)之前，可以将无源器件(例如，表面安装器件(SMD)，未示出)附接至第一器件封装件100。在这样的实施例中，无源器件可以与导电连接件110接合至第一器件封装件100的相同表面。
导电连接件110可以在其上形成有环氧树脂助焊剂(未示出)，然后在将第二器件封装件200附接至封装衬底202之后，回流剩余的环氧树脂助焊剂的至少一些环氧部分。该剩余的环氧部分可以用作底部填充物以减小应力并且保护由回流导电连接件110产生的接头。
可以在第一器件封装件100和封装衬底202之间形成围绕导电连接件110的底部填充物206。底部填充物206可以在附接第一器件封装件100之后通过的毛细管流动工艺形成，或可以在附接第一器件封装件100之前通过合适的沉积方法形成。
在图14中，将散热器208附接至第一器件封装件100和封装衬底202，覆盖并且围绕第一器件封装件100。散热器208可以由具有高热导率的材料形成，高热导率的材料诸如钢、不锈钢、铜等或它们的组合。在一些实施例(以下讨论的)中，散热器208涂覆有另一金属，诸如金、镍等。在一些实施例中，散热器208是单一连续材料。在一些实施例中，散热器208包括可以是相同或不同材料的多个工件。
将散热器208粘合至第一器件封装件100和封装衬底202。粘合剂210将散热器208附接至封装衬底202。粘合剂210可以是环氧树脂、胶等，并且可以是导热材料。热界面材料(TIM)212将散热器208附接至第一器件封装件100。TIM 212可以是聚合物材料、焊膏、铟焊膏等，并且可以分配在第一器件封装件100上，诸如在管芯堆叠件70、密封剂108和伪连接件118上。值得注意的是，TIM 212围绕伪连接件118。TIM 212形成为厚度足够大以掩埋伪连接件118。例如，在伪连接件118形成为约50μm的高度的实施例中，TIM 212形成为在从约25μm至约200μm(诸如约100μm)的厚度。
TIM 212热连接第一器件封装件100和散热器208。因为散热器208是第一器件封装件100的主要散热装置，所以TIM 212的热导率可能是操作期间沿着散热器208和管芯堆叠件70的最底管芯之间延伸的热路径P1的整体热阻的热瓶颈。因为伪连接件118被掩埋在TIM212中，所以可以降低沿着热路径P1的热阻。在实施例中，伪连接件118的添加可以将沿着热路径P1的热阻降低十倍或更多。此外，伪TSV 116也可以降低沿着热路径P1的热阻。
图15示出了采用产生的第二器件封装件200的半导体器件300。在半导体器件300中，用TIM 304将散热片302粘合至第二器件封装件200。散热片302可以由选自用于形成散热器208的备选材料的材料形成。散热片302可以由与散热器208相同的材料形成，或可以包括不同的材料。TIM 304可以与TIM 212类似，或可以不同。可以在用于制造第二器件封装件200的工艺之后以不同的工艺形成半导体器件300。例如，第二器件封装件200可以在第一工艺中制造，并且半导体器件300可以在第二器件封装件200的制造和传送之后的第二工艺中形成。
图16示出了根据一些其它实施例的半导体器件300。在所示的实施例中，没有形成伪TSV 116，从而使得管芯堆叠件70基本没有TSV。在这样的实施例中，伪连接件118的所有侧均由非导电材料围绕。虽然伪TSV 116可以降低沿着热路径P1的热阻，但是它们制造成本高。在TIM 212中形成伪连接件118可以充分降低沿着热路径P1的热阻，通过避免TSV的形成来减小制造成本。
图17示出了根据一些其它实施例的半导体器件300。在所示的实施例中，伪连接件118是由诸如铜、铝、钨、合金、掺杂的多晶硅等或它们的组合的导电材料形成的接线柱、柱或凸块。在具体实施例中，伪连接件118是伪铜柱。形成掩埋在TIM 212中的铜柱可以降低沿着热路径P1的热阻。
可以通过可接受的光刻和镀工艺形成伪铜柱。例如，在凹槽114中形成伪TSV 116(例如，见图9)之后，可以将合适的光刻胶(未示出)施加至晶圆102(例如，在密封剂108和管芯堆叠件70上)，并且显影光刻胶。光刻胶可以被图案化为具有暴露伪TSV 116的开口。可以用阻挡层内衬光刻胶中的开口。阻挡层可以是诸如氮化钛、氮化钽、钛、另一电介质等的导电材料，并且可以通过CVD、PECVD、MOCVD、ALD等形成。之后，可以在开口中形成导电材料，从而形成伪连接件118(例如，伪铜柱)。可以通过在开口中沉积晶种层并且之后将导电材料电镀至晶种层来形成导电材料，从而填充开口。之后，可以通过灰化、剥离等来去除光刻胶。
图18示出了根据一些其它实施例的半导体器件300。在所示的实施例中，在第一器件封装件100上形成粘合剂122。粘合剂122位于管芯堆叠件70、密封剂108和伪TSV 116上。可以在分割第一器件封装件100之前或之后将粘合剂122分配在第一器件封装件100上。粘合剂122可以是聚合物材料、焊膏、热粘合剂等，并且可以形成为在从约25μm至约150μm的厚度。伪连接件118形成在粘合剂122上，并且可以通过拾取和放置方法形成。在所示的实施例中，伪连接件118是诸如焊球的凸块。在一些实施例中，伪连接件118在伪TSV 116上方不对准。将TIM 212分配在粘合剂122上和伪连接件118周围。将伪连接件118掩埋在TIM 212中。粘合剂122可能使伪连接件118共形于第一器件封装件100的形状，包括共形于可能已经引入至第一器件封装件100的任何翘曲。因此，可以减小沿着热路径P1的整体热阻。
图19示出了根据一些其它实施例的半导体器件300。在所示的实施例中，在第一器件封装件100上形成伪金属124。伪金属124可以在分割第一器件封装件100之前或之后形成在第一器件封装件100上。伪金属124可以由导电材料或金属形成，导电材料或金属诸如金、铟、铜等或它们的组合。可以通过在晶圆102上方(例如，在密封剂108、管芯堆叠件70和伪TSV 116上)沉积晶种层，并且之后将导电材料电镀至晶种层来形成伪金属124。伪金属124也可以通过将导电材料溅射到晶圆102上来形成。与伪TSV 116相似，伪金属124可以与管芯堆叠件70的有源和/或无源器件(例如，器件54)和其它周围器件电隔离。
伪连接件118形成在伪金属124上，并且可以通过拾取和放置方法形成。在所示的实施例中，伪连接件118是诸如焊球的凸块。将TIM 212分配在伪金属124上和伪连接件118周围。伪连接件118没有掩埋在TIM 212中。而且，在形成之后，伪连接件118具有与TIM 212齐平或延伸在TIM 212之上的顶面。当散热器208附接至第一器件封装件100时，回流伪连接件118以将伪金属124接合至散热器208。从而在TIM 212中形成接合伪金属124和散热器208的焊料接头。在所示的实施例中，散热器208涂覆有另一金属，诸如镍。在回流期间，散热器208的镍涂层与TIM212和伪连接件118的材料混合以在散热器208和TIM 212的界面处形成金属间化合物(IMC)126。IMC 126可以具有不同的区域；例如，IMC 126可以具有第一区域，其中，第一IMC由伪连接件118和散热器208的材料形成，并且可以具有第二区域，其中，第二IMC由TIM 212和散热器208的材料形成。伪金属124和IMC 126可以具有高导热性并且可以共形于第一器件封装件100的形状，包括共形于可能已经引入至第一器件封装件100的任何翘曲。因此，可以减小沿着热路径P1的整体热阻。
图20示出了根据一些其它实施例的半导体器件300。在所示的实施例中，伪连接件118是图案化的金属片的一部分(例如，见图21，图21示出了图案化的金属片的俯视图)。例如，图案化的金属片可以是诸如用于射频干扰(RFI)屏蔽的铜箔，并且可以包括开口128。图案化的金属片可以具有在从约11μm至约25μm的厚度。图案化的金属片设置在TIM 212中，从而使得TIM 212设置在图案化的金属片和第一器件封装件100之间，并且也设置在图案化的金属片和散热器208之间。图案化的金属片可以具有高导热性并且可以共形于第一器件封装件100的形状，包括共形于可能已经引入至第一器件封装件100的任何翘曲。因此，可以减小沿着热路径P1的整体热阻。
图22示出了根据一些其它实施例的用于制造半导体器件300的方法400的流程图。在步骤402中，将诸如管芯堆叠件70A的管芯堆叠件附接至中介层120。在步骤404中，密封管芯堆叠件70A。在步骤406中，可选地在管芯堆叠件中形成伪TSV 116。在步骤408中，在管芯堆叠件上形成伪连接件118。伪连接件118可以根据本文的任何实施例形成。在步骤410中，将TIM 212分配在伪连接件118周围。在步骤412中，使用TIM 212将散热器208附接至管芯堆叠件。在随后的处理步骤中，可以将散热片302附接至散热器208。
实施例可以实现许多优势。TIM 212的热导率可能是堆叠器件中的一个重要的热瓶颈。在TIM 212中形成伪连接件118以及在管芯堆叠件70中形成伪TSV 116可以降低沿着热路径P1的热阻。诸如粘合剂122、伪金属124和共晶化合物126的其它部件的添加可能有助于使TIM 212共形于可能引入至器件封装件100的任何翘曲。因此，可以减小沿着热路径P1的整体热阻。
在实施例中，器件包括：位于中介层上方并且电连接至中介层的管芯堆叠件，管芯堆叠件包括最顶集成电路管芯，最顶集成电路管芯包括：具有前侧和与前侧相对的背侧的衬底，衬底的前侧包括有源表面；从衬底的背侧至少部分地延伸至衬底内的伪衬底通孔(TSV)，伪TSV与有源表面电隔离；位于最顶集成电路管芯上方的热界面材料；以及位于热界面材料中的伪连接件，热界面材料围绕伪连接件，伪连接件与最顶集成电路管芯的有源表面电隔离。
在一些实施例中，伪连接件是设置在伪TSV上的焊料连接件。在一些实施例中，伪连接件是设置在伪TSV上的铜柱。在一些实施例中，该器件还包括：位于最顶集成电路管芯上的粘合剂，伪连接件和热界面材料设置在粘合剂上。在一些实施例中，该器件还包括：位于最顶集成电路管芯上的伪金属，伪连接件和热界面材料设置在伪金属上，伪金属与最顶集成电路管芯的有源表面电隔离；以及位于热界面材料上的共晶化合物，伪连接件将共晶化合物接合至伪金属。在一些实施例中，伪连接件是图案化的金属片。在一些实施例中，该器件还包括：封装衬底，将中介层接合至封装衬底；以及粘合至封装衬底和管芯堆叠件的散热器，散热器覆盖并且围绕管芯堆叠件，热界面材料热连接散热器和管芯堆叠件。在一些实施例中，管芯堆叠件还包括：接合至中介层的界面管芯，最顶集成电路管芯接合至界面管芯。
在实施例中，方法包括：将管芯堆叠件附接至中介层；用密封剂密封管芯堆叠件；平坦化密封剂，密封剂与管芯堆叠件的顶面齐平；在管芯堆叠件的最顶集成电路管芯中形成凹槽，最顶集成电路管芯包括具有有源表面和背面的衬底，该衬底具有第一高度，凹槽从衬底的背面延伸第一深度，第一深度小于第一高度；用第一导电材料填充凹槽以形成伪衬底通孔(TSV)；在伪TSV上形成伪连接件；将热界面材料分配在最顶集成电路管芯上，热界面材料围绕伪连接件；以及将散热器附接至最顶集成电路管芯，散热器覆盖并且围绕管芯堆叠件和中介层。
在一些实施例中，该方法还包括：在晶圆中形成中介层；以及分割晶圆以形成中介层，中介层具有设置在其上的管芯堆叠件。在一些实施例中，伪TSV和伪连接件在分割晶圆之前形成。在一些实施例中，在伪TSV上形成伪连接件包括在伪TSV上形成焊料连接件。在一些实施例中，在伪TSV上形成伪连接件包括：在最顶集成电路管芯上形成光刻胶；图案化光刻胶以形成暴露伪TSV的开口；以及在开口中形成第二导电材料以形成伪连接件。在一些实施例中，该方法还包括：在最顶集成电路管芯上镀伪金属，将热界面材料分配在伪金属上，伪金属与最顶集成电路管芯的有源表面电隔离。在一些实施例中，伪连接件包括焊料连接件，该方法还包括：回流焊料连接件以将伪金属接合至散热器。在一些实施例中，将管芯堆叠件附接至中介层包括：利用导电连接件将管芯堆叠件接合至中介层；以及在管芯堆叠件和中介层之间形成底部填充物，底部填充物围绕导电连接件。
在实施例中，方法包括：将管芯堆叠件附接至中介层；用密封剂密封管芯堆叠件；平坦化密封剂，密封剂与管芯堆叠件的顶面齐平；将热界面材料分配在管芯堆叠件上；在热界面材料中形成伪连接件，伪连接件的所有侧均由非导电材料围绕；以及将散热器附接至管芯堆叠件，散热器覆盖并且围绕管芯堆叠件和中介层。
在一些实施例中，在热界面材料中形成伪连接件包括：在管芯堆叠件上形成伪连接件。在一些实施例中，在热界面材料中形成伪连接件包括：在管芯堆叠件上形成伪金属；以及在伪金属上形成伪连接件。在一些实施例中，在热界面材料中形成伪连接件包括：将图案化的金属片设置在热界面材料中。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
管芯堆叠件，位于中介层上方并且电连接至所述中介层，所述管芯堆叠件包括最顶集成电路管芯，所述最顶集成电路管芯包括：
衬底，具有前侧和与所述前侧相对的背侧，所述衬底的前侧包括有源表面；
伪衬底通孔(TSV)，从所述衬底的背侧至少部分地延伸至所述衬底内，所述伪衬底通孔与所述有源表面电隔离；
热界面材料，位于所述最顶集成电路管芯上方；以及
伪连接件，位于所述热界面材料中，所述热界面材料围绕所述伪连接件，所述伪连接件与所述最顶集成电路管芯的有源表面电隔离，其中，所述伪连接件的与所述最顶集成电路管芯相对的表面掩埋在所述热界面材料中。
2.根据权利要求1所述的半导体器件，其中，所述伪连接件是设置在所述伪衬底通孔上的焊料连接件。
3.根据权利要求1所述的半导体器件，其中，所述伪连接件是设置在所述伪衬底通孔上的铜柱。
4.根据权利要求1所述的半导体器件，还包括：
位于所述最顶集成电路管芯上的粘合剂，所述伪连接件和所述热界面材料设置在所述粘合剂上。
5.根据权利要求1所述的半导体器件，其中，所述伪连接件是图案化的金属片。
6.根据权利要求1所述的半导体器件，还包括：
封装衬底，所述中介层接合至所述封装衬底；以及
散热器，粘合至所述封装衬底和所述管芯堆叠件，所述散热器覆盖并且围绕所述管芯堆叠件，所述热界面材料热连接所述散热器和所述管芯堆叠件。
7.根据权利要求1所述的半导体器件，其中，所述管芯堆叠件还包括：
界面管芯，接合至所述中介层，所述最顶集成电路管芯接合至所述界面管芯。
8.一种半导体器件，包括：
管芯堆叠件，位于中介层上方并且电连接至所述中介层，所述管芯堆叠件包括最顶集成电路管芯，所述最顶集成电路管芯包括：
衬底，具有前侧和与所述前侧相对的背侧，所述衬底的前侧包括有源表面；
伪衬底通孔(TSV)，从所述衬底的背侧至少部分地延伸至所述衬底内，所述伪衬底通孔与所述有源表面电隔离；
热界面材料，位于所述最顶集成电路管芯上方；以及
伪连接件，位于所述热界面材料中，所述热界面材料围绕所述伪连接件，所述伪连接件与所述最顶集成电路管芯的有源表面电隔离，
伪金属，位于所述最顶集成电路管芯上，所述伪连接件和所述热界面材料设置在所述伪金属上，所述伪金属与所述最顶集成电路管芯的有源表面电隔离；以及
共晶化合物，位于所述热界面材料上，所述伪连接件将所述共晶化合物接合至所述伪金属。
9.一种制造半导体器件的方法，包括：
将管芯堆叠件附接至中介层；
用密封剂密封所述管芯堆叠件；
平坦化所述密封剂，所述密封剂与所述管芯堆叠件的顶面齐平；
在所述管芯堆叠件的最顶集成电路管芯中形成凹槽，所述最顶集成电路管芯包括具有有源表面和背面的衬底，所述衬底具有第一高度，所述凹槽从所述衬底的背面延伸第一深度，所述第一深度小于所述第一高度；
用第一导电材料填充所述凹槽以形成伪衬底通孔(TSV)；
在所述伪衬底通孔上形成伪连接件；
将热界面材料分配在所述最顶集成电路管芯上，所述热界面材料围绕所述伪连接件，其中，所述伪连接件的与所述最顶集成电路管芯相对的表面掩埋在所述热界面材料中；以及
将散热器附接至所述最顶集成电路管芯，所述散热器覆盖并且围绕所述管芯堆叠件和所述中介层。
10.根据权利要求9所述的方法，还包括：
在晶圆中形成所述中介层；以及
分割所述晶圆以形成所述中介层，所述中介层具有设置在所述中介层上的所述管芯堆叠件。
11.根据权利要求10所述的方法，其中，所述伪衬底通孔和所述伪连接件在分割所述晶圆之前形成。
12.根据权利要求9所述的方法，其中，在所述伪衬底通孔上形成所述伪连接件包括在所述伪衬底通孔上形成焊料连接件。
13.根据权利要求9所述的方法，其中，在所述伪衬底通孔上形成所述伪连接件包括：
在所述最顶集成电路管芯上形成光刻胶；
图案化所述光刻胶以形成暴露所述伪衬底通孔的开口；以及
在所述开口中形成第二导电材料以形成所述伪连接件。
14.根据权利要求9所述的方法，其中，将所述管芯堆叠件附接至所述中介层包括：
利用导电连接件将所述管芯堆叠件接合至所述中介层；以及
在所述管芯堆叠件和所述中介层之间形成底部填充物，所述底部填充物围绕所述导电连接件。
15.一种制造半导体器件的方法，包括：
将管芯堆叠件附接至中介层；
用密封剂密封所述管芯堆叠件；
平坦化所述密封剂，所述密封剂与所述管芯堆叠件的顶面齐平；
在所述管芯堆叠件的最顶集成电路管芯中形成凹槽，所述最顶集成电路管芯包括具有有源表面和背面的衬底，所述衬底具有第一高度，所述凹槽从所述衬底的背面延伸第一深度，所述第一深度小于所述第一高度；
用第一导电材料填充所述凹槽以形成伪衬底通孔(TSV)；
在所述伪衬底通孔上形成伪连接件；
将热界面材料分配在所述最顶集成电路管芯上，所述热界面材料围绕所述伪连接件，其中，所述伪连接件掩埋在所述热界面材料中；以及
将散热器附接至所述最顶集成电路管芯，所述散热器覆盖并且围绕所述管芯堆叠件和所述中介层，
其中，所述方法还包括：
在所述最顶集成电路管芯上镀伪金属，所述热界面材料分配在所述伪金属上，所述伪金属与所述最顶集成电路管芯的有源表面电隔离。
16.根据权利要求15所述的方法，其中，所述伪连接件包括焊料连接件，所述方法还包括：
回流所述焊料连接件以将所述伪金属接合至所述散热器。
17.一种制造半导体器件的方法，包括：
将管芯堆叠件附接至中介层；
用密封剂密封所述管芯堆叠件；
平坦化所述密封剂，所述密封剂与所述管芯堆叠件的顶面齐平；
将热界面材料分配在所述管芯堆叠件上；
在所述热界面材料中形成伪连接件，所述伪连接件的所有侧均由所述热界面材料围绕，并且所述伪连接件的与所述管芯堆叠件相对的表面掩埋在所述热界面材料中；以及
将散热器附接至所述管芯堆叠件，所述散热器覆盖并且围绕所述管芯堆叠件和所述中介层。
18.根据权利要求17所述的方法，其中，在所述热界面材料中形成所述伪连接件包括：
在所述管芯堆叠件上形成所述伪连接件。
19.根据权利要求17所述的方法，其中，在所述热界面材料中形成所述伪连接件包括：
在所述管芯堆叠件上形成伪金属；以及
在所述伪金属上形成所述伪连接件。
20.根据权利要求17所述的方法，其中，在所述热界面材料中形成所述伪连接件包括：
将图案化的金属片设置在所述热界面材料中。
CN201810461232.5A 2017-08-31 2018-05-15 散热器件和方法 Active CN109427702B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762552902P 2017-08-31 2017-08-31
US62/552,902 2017-08-31
US15/864,896 2018-01-08
US15/864,896 US10461014B2 (en) 2017-08-31 2018-01-08 Heat spreading device and method

Publications (2)

Publication Number Publication Date
CN109427702A CN109427702A (zh) 2019-03-05
CN109427702B true CN109427702B (zh) 2020-07-17

Family

ID=65435602

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810461232.5A Active CN109427702B (zh) 2017-08-31 2018-05-15 散热器件和方法

Country Status (4)

Country Link
US (3) US10461014B2 (zh)
KR (1) KR102183614B1 (zh)
CN (1) CN109427702B (zh)
TW (1) TWI653720B (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10515867B2 (en) * 2017-11-14 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR102404058B1 (ko) * 2017-12-28 2022-05-31 삼성전자주식회사 반도체 패키지
US11756856B2 (en) * 2018-10-02 2023-09-12 Intel Corporation Package architecture including thermoelectric cooler structures
US11594463B2 (en) * 2018-10-11 2023-02-28 Intel Corporation Substrate thermal layer for heat spreader connection
KR102566772B1 (ko) * 2018-11-09 2023-08-14 삼성전자주식회사 반도체 패키지
CN109640521B (zh) * 2018-11-20 2020-06-30 奥特斯科技(重庆)有限公司 制造具有嵌入式集群的部件承载件的方法以及部件承载件
TWI721383B (zh) * 2019-03-08 2021-03-11 力成科技股份有限公司 具有多個積體電路單元的封裝結構及其製作方法
US12062592B2 (en) * 2019-05-22 2024-08-13 Intel Corporation Integrated circuit packages with thermal interface materials with different material compositions
US11158566B2 (en) * 2019-05-24 2021-10-26 Google Llc Integrated circuit with a ring-shaped hot spot area and multidirectional cooling
US11282763B2 (en) * 2019-06-24 2022-03-22 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device having a lid with through-holes
KR102651418B1 (ko) 2019-07-25 2024-03-27 삼성전자 주식회사 차폐 시트 및 방열 부재를 포함하는 전자 장치
US11728238B2 (en) * 2019-07-29 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with heat dissipation films and manufacturing method thereof
US20210104448A1 (en) * 2019-10-08 2021-04-08 Intel Corporation Lateral heat removal for 3d stack thermal management
US11410968B2 (en) 2019-10-18 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US11404395B2 (en) 2019-11-15 2022-08-02 Samsung Electronics Co., Ltd. Semiconductor package including underfill material layer and method of forming the same
KR20210081891A (ko) 2019-12-24 2021-07-02 삼성전자주식회사 반도체 패키지
US11854935B2 (en) 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias
US11923267B2 (en) * 2020-03-26 2024-03-05 Intel Corporation IC die with solderable thermal interface structures for assemblies including solder array thermal interconnects
US11935808B2 (en) * 2020-03-26 2024-03-19 Intel Corporation IC die and heat spreaders with solderable thermal interface structures for multi-chip assemblies including solder array thermal interconnects
US11984377B2 (en) 2020-03-26 2024-05-14 Intel Corporation IC die and heat spreaders with solderable thermal interface structures for assemblies including solder array thermal interconnects
DE102021101251A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Schutz vor antenneneffekten und schutz vor elektrostatischen entladungen für dreidimensionale integrierte schaltkreise
KR20210128681A (ko) 2020-04-17 2021-10-27 에스케이하이닉스 주식회사 저항 소자를 구비하는 반도체 장치
KR20210135107A (ko) 2020-05-04 2021-11-12 삼성전자주식회사 반도체 패키지
US11694939B2 (en) * 2020-05-22 2023-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package, integrated optical communication system
US11715755B2 (en) 2020-06-15 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for forming integrated high density MIM capacitor
JP7528557B2 (ja) * 2020-06-19 2024-08-06 日本電気株式会社 量子デバイス及びその製造方法
US11769752B2 (en) * 2020-07-24 2023-09-26 Micron Technology, Inc. Stacked semiconductor die assemblies with substrate heat sinks and associated systems and methods
US11239136B1 (en) 2020-07-28 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Adhesive and thermal interface material on a plurality of dies covered by a lid
US11410910B2 (en) * 2020-07-30 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device including liquid-cooled lid and methods of forming the same
EP4224529A4 (en) * 2020-10-28 2024-03-06 Huawei Technologies Co., Ltd. MULTI-CHIP PACKAGING STRUCTURE, MANUFACTURING METHOD AND ELECTRONIC DEVICE
CN116547805A (zh) * 2020-12-11 2023-08-04 Qorvo美国公司 具有硅裸片作为用于高功率低热导率裸片的散热器的3d封装
US11908767B2 (en) * 2021-01-13 2024-02-20 Mediatek Inc. Semiconductor package structure
EP4372789A4 (en) * 2021-08-02 2024-10-02 Huawei Tech Co Ltd CHIP STACKING STRUCTURE AND MANUFACTURING METHOD THEREFOR, AS WELL AS CHIP HOUSING STRUCTURE AND ELECTRONIC DEVICE
JP2023031660A (ja) * 2021-08-25 2023-03-09 キオクシア株式会社 半導体装置及び電子機器
US12094792B2 (en) 2021-08-30 2024-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having lid with protrusion and manufacturing method thereof
TWI838772B (zh) 2022-06-20 2024-04-11 財團法人工業技術研究院 低熔點合金複材與複材結構
US20240071847A1 (en) * 2022-08-26 2024-02-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method
JP2024133776A (ja) * 2023-03-20 2024-10-03 ソニーセミコンダクタソリューションズ株式会社 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421995B (zh) * 2011-04-27 2014-01-01 Unimicron Technology Corp 半導體封裝結構及其製法
CN104966677A (zh) * 2015-07-08 2015-10-07 华进半导体封装先导技术研发中心有限公司 扇出型芯片封装器件及其制备方法

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100391093B1 (ko) 2001-01-04 2003-07-12 삼성전자주식회사 히트 싱크가 부착된 볼 그리드 어레이 패키지
US7019977B2 (en) * 2003-12-17 2006-03-28 Intel Corporation Method of attaching non-adhesive thermal interface materials
US8367034B2 (en) 2004-06-04 2013-02-05 The Trustees Of Columbia University In The City Of New York Methods for preparing single-walled carbon nanotubes
US8030757B2 (en) * 2007-06-29 2011-10-04 Intel Corporation Forming a semiconductor package including a thermal interface material
US10181454B2 (en) * 2010-03-03 2019-01-15 Ati Technologies Ulc Dummy TSV to improve process uniformity and heat dissipation
KR101715761B1 (ko) * 2010-12-31 2017-03-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
FR2970671B1 (fr) * 2011-01-21 2016-12-30 Saint Gobain Vitrage lumineux
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
TWI434629B (zh) 2011-08-19 2014-04-11 Unimicron Technology Corp 半導體封裝結構及其製法
JP5838065B2 (ja) * 2011-09-29 2015-12-24 新光電気工業株式会社 熱伝導部材及び熱伝導部材を用いた接合構造
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US20130155636A1 (en) * 2011-12-16 2013-06-20 Changyok Park Dummy through-silicon via capacitor
KR20130094107A (ko) * 2012-02-15 2013-08-23 삼성전자주식회사 열 분산기를 갖는 반도체 패키지 및 그 형성 방법
KR20130105175A (ko) * 2012-03-16 2013-09-25 삼성전자주식회사 보호 층을 갖는 반도체 패키지 및 그 형성 방법
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8963317B2 (en) * 2012-09-21 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dissipation through seal rings in 3DIC structure
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
KR101428754B1 (ko) 2013-05-14 2014-08-11 (주)실리콘화일 방열 특성이 개선된 반도체 장치
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9368479B2 (en) * 2014-03-07 2016-06-14 Invensas Corporation Thermal vias disposed in a substrate proximate to a well thereof
US9412675B2 (en) * 2014-05-19 2016-08-09 Micron Technology, Inc. Interconnect structure with improved conductive properties and associated systems and methods
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
KR102254104B1 (ko) 2014-09-29 2021-05-20 삼성전자주식회사 반도체 패키지
US9653373B2 (en) * 2015-04-09 2017-05-16 Samsung Electronics Co., Ltd. Semiconductor package including heat spreader and method for manufacturing the same
CN105590906B (zh) * 2016-01-11 2019-02-01 江苏科技大学 一种用于扇出式圆片级封装的散热构件及制造方法
US10580717B2 (en) * 2016-01-11 2020-03-03 Intel Corporation Multiple-chip package with multiple thermal interface materials
JP6764666B2 (ja) * 2016-03-18 2020-10-07 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9997464B2 (en) * 2016-04-29 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy features in redistribution layers (RDLS) and methods of forming same
US9960150B2 (en) * 2016-06-13 2018-05-01 Micron Technology, Inc. Semiconductor device assembly with through-mold cooling channel formed in encapsulant
US10199356B2 (en) * 2017-02-24 2019-02-05 Micron Technology, Inc. Semiconductor device assembles with electrically functional heat transfer structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421995B (zh) * 2011-04-27 2014-01-01 Unimicron Technology Corp 半導體封裝結構及其製法
CN104966677A (zh) * 2015-07-08 2015-10-07 华进半导体封装先导技术研发中心有限公司 扇出型芯片封装器件及其制备方法

Also Published As

Publication number Publication date
TW201913920A (zh) 2019-04-01
US11018073B2 (en) 2021-05-25
CN109427702A (zh) 2019-03-05
US10461014B2 (en) 2019-10-29
US20190067157A1 (en) 2019-02-28
US20210280491A1 (en) 2021-09-09
TWI653720B (zh) 2019-03-11
US20200051888A1 (en) 2020-02-13
KR20190024628A (ko) 2019-03-08
KR102183614B1 (ko) 2020-11-27

Similar Documents

Publication Publication Date Title
CN109427702B (zh) 散热器件和方法
US10867884B2 (en) Heat spreading device and method
US11942403B2 (en) Integrated circuit package and method
KR102193505B1 (ko) 반도체 패키지 및 그 형성 방법
US11621205B2 (en) Underfill structure for semiconductor packages and methods of forming the same
TWI642157B (zh) 半導體封裝件及其形成方法
US11244939B2 (en) Package structure and method of forming the same
US11164824B2 (en) Package structure and method of fabricating the same
US11756855B2 (en) Method of fabricating package structure
US11469197B2 (en) Integrated circuit package and method
KR102564124B1 (ko) 집적 회로 패키지 및 그 형성 방법
KR20240005646A (ko) 집적 회로 패키지 및 방법
US20230402403A1 (en) Semiconductor package and manufacturing method of semiconductor package
TW202345307A (zh) 裝置封裝、半導體封裝及封裝方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant