CN111326505A - 具有电中介体的堆叠管芯半导体封装 - Google Patents
具有电中介体的堆叠管芯半导体封装 Download PDFInfo
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- CN111326505A CN111326505A CN201911282206.7A CN201911282206A CN111326505A CN 111326505 A CN111326505 A CN 111326505A CN 201911282206 A CN201911282206 A CN 201911282206A CN 111326505 A CN111326505 A CN 111326505A
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Abstract
一种半导体芯片组装件包括:第一和第二半导体管芯,每个包括面对面的上侧和下侧以及外边缘侧;以及具有面对面的第一和第二导电表面以及在导电表面之间的导电连接的电中介体。第二半导体管芯安装在第一半导体管芯和中介体的顶部上,使得第二半导体管芯的下侧面对第一半导体管芯和中介体,第二半导体管芯的第一横向部分至少部分地覆盖第一半导体管芯的上侧,并且第二半导体管芯的第二横向部分延伸超过第一半导体管芯的外边缘侧。第一导电表面电连接到设置在第二半导体管芯的下侧上的第一端子。
Description
技术领域
本发明涉及半导体器件封装,并且特别地涉及堆叠管芯半导体封装。
背景技术
面积消耗是许多半导体应用中的重要设计考虑。在诸如移动电话和RF应用的应用中,非常期望减小电子子组件(例如,放大器、处理器、接收器等)的必要电路板占用面积。为此原因,一些封装设计采用了堆叠技术,其中多个半导体管芯(芯片)或多个半导体封装被堆叠在彼此的顶部上。在芯片上芯片堆叠技术的情况下,两个半导体管芯以利用到管芯的接合线连接的堆叠布置而彼此附接。然后,利用线接合连接的堆叠芯片布置被模制以形成最终封装。
在一些应用中,期望将两个不同尺寸芯片堆叠在彼此的顶部上。常规地,较小芯片被堆叠在较大芯片的顶部上。这种配置允许在芯片的外围未覆盖区域处可电接入(accessible)较大芯片的端子。然而,这种芯片布置不是很适合于其中较小芯片在操作期间生成比较大芯片更多热的应用。在这种情况下,优选的是,将较小芯片放置在封装的底部处,使得其可以与外部散热器紧密或直接接触。
迄今为止,用于将较大芯片堆叠在较小芯片顶部上的封装解决方案具有各种缺点。常规的设计采用相对较长且复杂的接合线连接,其具有高寄生值和/或利用了中间再分布层,这增加了设计的成本和复杂性。
发明内容
公开了一种半导体芯片组装件。根据一个实施例,半导体芯片组装件包括第一和第二半导体管芯。第一和第二半导体管芯各自包括面对面的上侧和下侧以及在第一和第二半导体管芯的相应上侧和下侧之间延伸的外边缘侧。半导体芯片组装件还包括电中介体(interposer),该电中介体具有设置在第一端处的第一导电表面、设置在与第一端相对的第二端处的第二导电表面、以及在第一和第二导电表面之间的导电连接。第二半导体管芯安装在第一半导体管芯和中介体的顶部上,使得:第二半导体管芯的下侧面对第一半导体管芯的上侧和中介体的第一端,第二半导体管芯的第一横向(lateral)部分至少部分地覆盖第一半导体管芯的上侧,并且第二半导体管芯的第二横向部分延伸超过第一半导体管芯的外边缘侧并且在中介体的第一端上方。第一导电表面电连接到设置在第二半导体管芯的下侧上的第二半导体管芯的第一端子。
根据另一实施例,半导体芯片组装件包括具有面对面的上侧和下侧的放大器管芯、以及设置在放大器管芯的上侧上的输入端子。半导体芯片组装件还包括具有面对面的上侧和下侧的控制器管芯、设置在控制器管芯的下侧上的输出端子和输入端子。半导体芯片组装件还包括电中介体,该电中介体具有设置在第一端处的第一导电表面、设置在与第一端相对的第二端处的第二导电表面、以及在第一和第二导电表面之间的导电连接。半导体芯片组装件还包括设置在第一半导体管芯的下侧处或下方的平坦连接界面,该平坦连接界面具有多个导电I/O端子。控制器管芯安装在放大器管芯的顶部上,使得具有控制器管芯的输出端子的控制器管芯的第一横向部分与放大器管芯的输入端子对准并电连接,并且具有控制器管芯的输入端子的控制器管芯的第二横向部分与中介体的第一导电表面对准并电连接。电中介体在I/O端子中的第一I/O端子与控制器管芯的输入端子之间提供电连接。
公开了一种提供半导体芯片组装件的方法。根据一个实施例,该方法包括提供第一和第二半导体管芯,该第一和第二半导体管芯各自具有面对面的上侧和下侧以及在第一和第二半导体管芯的相应上侧和下侧之间延伸的外边缘侧。该方法还包括提供电中介体,该电中介体具有设置在第一端处的第一导电表面、设置在与第一端相对的第二端处的第二导电表面、以及在第一和第二导电表面之间的导电连接。该方法还包括将第二半导体管芯安装在第一半导体管芯和中介体的顶部上,使得:第二半导体管芯的下侧面对第一半导体管芯的上侧和中介体的第一端,第二半导体管芯的第一横向部分至少部分地覆盖第一半导体管芯的上侧,并且第二半导体管芯的第二横向部分延伸超过第一半导体管芯的外边缘侧并且在中介体的第一端上方。该方法还包括将第一导电表面电连接到设置在第二半导体管芯的下侧上的第一导电端子。
本领域技术人员在阅读以下详细描述并查看附图后将会认识到附加的特征和优点。
附图说明
附图中的元件不一定相对于彼此按比例。相同的附图标记表示对应的类似部分。各种所示实施例的特征可以组合,除非它们彼此排斥。实施例在附图中描绘并在随后的说明书中详述。
图1描绘根据一个实施例的其中较大管芯堆叠在较小管芯的顶部上并且电中介体提供到较大管芯的可外部接入的电连接的半导体芯片组装件;
包括图2A和2B的图2描绘根据一个实施例的生产半导体芯片组装件的方法。图2A描绘放置在临时载体上的一批中介体和较小管芯的等距视图,而图2B是来自图2A的区域的放大视图;
包括图3A和3B的图3描绘在封装较小管芯和中介体的第一模制过程之后的图2的组装件。图3A描绘该组装件的等距视图,而图3B是来自图3A的区域的放大视图;
包括图4A、4B和4C的图4描绘在封装较大管芯的第二模制过程之后的图3的组装件。图4A描绘该批组装件的等距视图,图4B描绘单个化后的芯片组装件的顶侧的等距视图,而图4C描绘单个化后的芯片组装件的底侧的等距视图;
包括图5A和5B的图5描绘可以根据图2-4的方法使用的电中介体的替选实施例。图5A描绘电中介体和第一半导体管芯在临时载体上的放置。图5B描绘在模制和连接到第二半导体管芯之后的器件;
图6描绘可以根据图2-4的方法使用的电中介体的替选实施例;
包括图7A和7B的图7描绘根据一个实施例的使用图6的电中介体来形成半导体管芯组装件的方法。图7A描绘放置在临时载体上的一批中介体和较小管芯的等距视图,而图7B描绘在第一模制过程之后的图7A的该批组装件;
图8描绘根据一个实施例的使用图6的电中介体而形成的半导体芯片组装件。
具体实施方式
根据本文描述的实施例,半导体芯片组装件包括第二半导体管芯,其堆叠在第一半导体管芯的顶部上,使得第二(上)半导体管芯横向地悬垂超过第一(下)半导体管芯的外边缘侧。该组装件还包括挨着下管芯且在上管芯的悬垂部分下方提供的电中介体。该电中介体在第二(上)半导体管芯的下侧上的端子与在组装件的底侧处可外部接入的I/O端子之间提供直接低电阻电连接。该中介体有利地提供了用于将较大器件封装在较小器件顶部上的低成本解决方案,其中较大器件的端子可通过低电阻连接而电接入。
参考图1,半导体芯片组装件100包括第一和第二半导体管芯102、104。第一和第二半导体管芯102、104中的每一个包括面对面的上侧106和下侧108以及在第一和第二半导体管芯102、104的相应面对面的上侧106和下侧108之间延伸的外边缘侧110。上侧106、下侧108和外边缘侧110是第一和第二半导体管芯102、104的半导体材料的最外表面。
第一和第二半导体管芯102、104各自包括向第一和第二半导体管芯102、104的集成电路提供输入/输出/功率连接(例如,栅极、源极等)的端子。这些端子可以通过导电接合焊盘来提供。在一些实施例中,这些接合焊盘与其被设置到的半导体表面(即,上侧106及下侧108)共面。作为替选,这些接合焊盘可以延伸超过管芯的半导体材料,例如作为柱形结构、焊接凸块、球下金属化等。在所描绘的实施例中,第二半导体管芯104的下侧108包括第一端子112及第二端子114,且第一半导体管芯102的上侧106包括第三端子116。如所示,第三端子116延伸超过第一半导体管芯102的上侧106,并且第一和第二端子112、114与第二半导体管芯104的下侧108共面。
半导体芯片组装件100还包括电中介体118。电中介体118包括设置在第一端122处的第一平坦导电表面120和设置在与第一端122相对(即,背对)的第二端126处的第二平坦导电表面124。第一和第二平坦导电表面120、124通过设置在电中介体118内的导电连接123彼此电连接。
电中介体118在结构上配置成提供电连接界面,该电连接界面允许第二半导体管芯104以表面安装方式搁置在电中介体118上且电连接到电中介体118。根据一个实施例,第一平坦导电表面120和第三端子116的平坦上表面基本上彼此共面。以此方式,第一平坦导电表面120和第三端子116提供了在表面安装配置中与第二半导体管芯104的下侧108直接对接的单独的端子。如所示,第一平坦导电表面120与电中介体128的第一端122共面。在其他实施例中,第一平坦导电表面120可以从第一端122突出来。
在一个实施例中,电中介体118被配置为独立的元件。也就是说,电中介体118可以在没有使其保持就位的任何机构的情况下物理地搁置在平坦表面(例如,载体)上。为此,电中介体118的第二端126足够平坦以使电中介体118稳定,并且电中介体118具有足够的结构完整性(例如,机械刚性)以允许电中介体128独立地搁置在平坦表面上。
在一个实施例中,电中介体118的厚度与第一半导体管芯102的厚度相关。例如,电中介体118可以具有在第一和第二端122、126之间测量的厚度,该厚度基本上等于(例如,在+/-5%内)第一半导体管芯102的在其上侧106和下侧108之间测量的厚度。以此方式,电中介体118和第一半导体管芯102可以挨着彼此搁置在平坦表面上,并且提供用于安装第一半导体管芯102的大致平面。
一般而言,电中介体118可以包括各种各样的导电材料,例如铝、铜、其合金等。根据一个实施例,电中介体118具有由电绝缘材料形成的绝缘体128,所述电绝缘材料诸如塑料(例如,环氧树脂、模制复合材料等)、玻璃纤维材料(例如,FR-2、FR-4、FR-6、CEM-1、球形玻璃纤维)等。在该配置中,绝缘体128包括在电中介体118的第一和第二端122、126之间延伸的绝缘侧壁130;第一和第二平坦导电表面120、124通过设置在绝缘体128的顶部和下方的接合焊盘来提供;而第一和第二导电表面120、124之间的导电连接123通过包含在刚性绝缘体128内的电导体来提供。作为替选,电中介体118可以由完全导电(exclusivelyconductive)结构来提供,其中第一和第二平坦导电表面120、124表示结构的外表面。下面将进一步详细描述每种配置的各种示例。
第二半导体管芯104安装在第一半导体管芯102和电中介体118的顶部上,使得第二半导体管芯104的下侧108面对第一半导体管芯102的上侧106和电中介体118的第一端122。在一个实施例中,第二半导体管芯104的下侧108直接接触第一半导体管芯102和电中介体118的第一端122。作为替选,这些表面可以通过例如导电结构和/或模制材料彼此分开。另外,第二半导体管芯104被安装成使得第二半导体管芯104的第一横向部分132至少部分地覆盖第一半导体管芯102的上侧106。换句话说,第二半导体管芯104的第一横向部分132与第一半导体管芯102的至少一部分直接重叠,且第二半导体管芯104的下侧108在第一横向部分132中不可物理接入。另外,第二半导体管芯104被安装成使得第二半导体管芯104的第二横向部分134延伸超过第一半导体管芯102的外边缘侧110且在电中介体118的第一端122上方。换句话说,第二半导体管芯104的第二横向部分134与第一半导体管芯102不直接重叠,使得第二半导体管芯104的下侧108在第二横向部分134中可物理接入。
第二半导体管芯104被安装成使得第二半导体管芯104的第二端子114与第一半导体管芯102的第三端子116对准并电连接。另外,第二半导体管芯104被安装成使得第二半导体管芯104的第一端子112与电中介体118的第一平坦导电表面120对准且电连接。在此上下文中,"与……对准"意味着相应导电表面的至少部分彼此直接重叠,使得直接电连接是可能的。可以通过直接表面到表面接触和/或使用导电媒介(例如焊料、烧结物、导电胶等)来实现电连接。
半导体芯片组装件100还包括电绝缘模制复合材料,其对第一和第二半导体管芯102、104以及电中介体118进行封装。模制复合材料可以包括多种电绝缘材料,诸如陶瓷、环氧树脂材料和热固性塑料,仅举几例。在所描绘的实施例中,第一半导体管芯102和电中介体118被第一模制体136封装,而第二半导体管芯104被与第一模制体136分开形成的第二模制体138封装。可选地,可以在第一和第二模制体136、138之间的拐角界面处提供底部填充(underfill)140,以密封和保护第一和第二半导体管芯102、104和电中介体118之间的电连接。
半导体芯片组装件100包括平坦连接界面142。平坦连接界面142是半导体芯片组装件100的大致平坦表面,其设置在第一半导体管芯102的下侧108处或下方。平坦连接界面142包括多个I/O端子144,其提供到第一和第二半导体管芯102、104的各种端子的电连接性。平坦连接界面142被配置成使得半导体芯片组装件100可以安装在诸如印刷电路板的外部装置上,其中I/O端子144直接接触且电连接到外部装置中的对应端子。可选地,导电焊球145或导电凸块等可以设置在I/O端子144上,以便于焊接。
根据一个实施例,电中介体118的第二端126提供平坦连接界面142的至少部分。例如,电中介体118的第二平坦导电表面124可以与第一半导体管芯102的下侧108基本上共面,并从第一模制体136暴露,使得其在半导体芯片组装件100的底部处可电接入。在这种配置中,第二平坦导电表面124直接提供可以电连接到外部装置的I/O端子144。作为替选,可以在第二平坦导电表面124与I/O端子144中的一个之间提供其他导电结构(例如,通孔结构)。
一般而言,第一和第二半导体管芯102、104可以具有各种不同的器件配置。这些器件结构的示例包括MOSFET(金属氧化物半导体场效应晶体管)器件、LDMOS(横向扩散金属氧化物半导体)器件、HEMT(高电子迁移率晶体管)器件、二极管、晶闸管、控制器、放大器和处理器,仅举几例。第一和第二半导体管芯102、104中的一个或两个可以被配置为竖直器件(即、在垂直于相应的上侧106和下侧108的方向上导电的器件),或者作为替选被配置为横向器件(即,在平行于相应的上侧106和下侧108的方向上导电的器件)。第二半导体管芯可以包括暴露的导体147(例如,金属)。在包括横向配置的各种实施例中,暴露的导体147是非电活性的(electrically inactive)并且用作热耗散机构。作为替选,在包括竖直配置的实施例中,暴露的导体147被配置为第一半导体管芯102的端子(例如,源极或漏极端子),并因此提供I/O端子144中的一个。
根据一个实施例,半导体芯片组装件100被配置为组合的放大器/控制器。在此配置中,第一半导体管芯102是放大器管芯,而第二半导体管芯104是驱动器/控制器管芯。更特别地,第一半导体管芯102可以被配置为基于GaN(砷化镓)的HEMT(高电子迁移率晶体管)器件,并且控制器管芯可以被配置为基于硅的ASIC(专用集成电路)。在这种配置中,控制器管芯被配置成向放大器管芯提供要被放大的信号,并且操作放大器管芯,例如开/关控制、量值等。放大器管芯在输入端子处接收要被放大的信号,并且在输出端子处提供该信号的经放大版本。在一个示例中,第一端子112是控制器管芯的输入端子,第二端子114是控制器管芯的输出端子,而第三端子116是放大器管芯的输入端子。RF信号的未经放大版本经由电中介体118被外部提供给控制器管芯的输入端子,其继而经由第二端子114和第三端子116之间的导电连接被提供给放大器管芯。RF信号的经放大版本可以通过类似的导电端子连接(未示出)和另外的中介体118返回到I/O端子144中的一个。相同的概念可以用于在两个管芯之间传输功率或参考电势电压。
根据一个实施例,第二半导体管芯104大于第一半导体管芯102。即,由第二半导体管芯104的外边缘侧110的周界所限定的第二半导体管芯104的横向面积大于由第一半导体管芯102的外边缘侧110的周界所限定的第一半导体管芯102的横向面积。图1示出了对应于该实施例的第二半导体管芯104的虚线区域。在这种情况下,第二半导体管芯104在所有方向上横向悬垂超过第一半导体管芯102的外边缘侧110。第二半导体管芯104可以在这些横向悬伸部分中包括另外的端子,所述另外的端子以与先前描绘的方式类似的方式通过中介体连接到I/O端子144。该图还包括以虚线的附加电中介体118,其包括对应的第一和第二平坦导电表面120、124,并提供到I/O端子144中的一个的另一电连接。该电中介体118可以是与连接到第一端子112的电中介体118不同的分立结构。作为替选,电中介体118可以为连续结构,其形成围绕第一半导体管芯102的封闭环路且包括多个隔离的导电连接123。此外,作为提供如本文所述的竖直电连接的附加或代替,电中介体118可以被配置有水平布线以提供横向分开的端子之间的电连接性。
在一个示例中,半导体芯片组装件100可以直接安装在衬底(例如PCB)上,其中堆叠布置提供节省多芯片配置的空间。衬底可以包括许多其他器件,例如开关、功率转换器、滤波器、逻辑电路和无源组件,诸如电容器、电阻器、电感器等。这些组件可以例如通过焊料、烧结、线接合等而连接到衬底。
参考图2,根据一个实施例,描绘了用于形成参考图1所描述的半导体芯片组装件100的技术。根据该技术,同时形成多个半导体芯片组装件100。该技术可以使用标准尺寸的封装处理板来执行,例如24"x18"板、70 mm x25 mm板、300 mm2圆形板等。
在图2的实施例中,电中介体118形成围绕中心开口146的封闭环路。也就是说,电中介体118围绕形成中心开口146的三维体积连续地延伸。在所描绘的实施例中,封闭环路具有矩形形状。更一般地,封闭环路可以具有各种封闭几何形状中的任何一种,例如圆形、多边形等。
在图2的实施例中,电中介体118通过印刷电路板衬底来提供。在该示例中,电中介体118包括金属化(例如,铜)和绝缘体(例如,诸如FR-4的预浸渍复合纤维)的交替层。第一和第二平坦导电表面120、124通过设置在PCB衬底的相对端处的导电接合焊盘来提供。导电连接123可以通过延伸穿过PCB衬底的各层的通孔来提供。
根据该技术,提供临时载体148。一般而言,临时载体148可以是适于通过各种半导体处理工具来处置和传递电子组件的任何平坦表面。在一个示例中,临时载体148包括热释放带。
电中介体118被放置在临时载体148上,使得电中介体118的第二端126面对并搁置在临时载体148上。此外,第一半导体管芯102放置在临时载体148上,其中第一半导体管芯102的下侧108搁置在临时载体148上。第一半导体管芯102放置在电中介体118的中心开口146中。在所描绘的实施例中,中心开口146的面积大于第一半导体管芯102的面积。结果,第一半导体管芯102的外边缘侧110在所有方向上与电中介体118的内侧壁130间隔开。
参考图3,执行第一模制过程。根据该技术,电绝缘模制材料150形成在第一半导体管芯102和电中介体118上和周围。这可以使用已知的模制技术来完成,诸如注射模制、传递模制、压缩模制等。模制材料150填充第一半导体管芯102与中介体的侧壁130之间的区域。另外,一些模制材料150可以覆盖第一半导体管芯102的上侧106和/或电中介体118的第一端122。
在执行第一模制过程之后,执行平坦化步骤。这可以根据如抛光或研磨的已知平坦化技术来完成。平坦化步骤去除了多余的模制材料,并提供了组装件的上侧处的基本平坦表面。此外,平坦化步骤从模制材料150暴露第一半导体管芯102的端子和电中介体118的第一平坦导电表面120。如图2和3中所示,第一半导体管芯102包括导电柱152,其从第一半导体管芯102的上侧106延伸且提供第一半导体管芯102的端子(例如,第一和第二端子112、114)。这些柱152可以在平坦化过程期间容易地被平坦化并暴露,同时保持第一半导体管芯102的上侧106和平坦化机构之间的余量。
参考图4,在执行图3的模制和平坦化步骤之后,第二半导体管芯104被安装在第一半导体管芯102的顶部上和电中介体118的顶部上。在此实施例中,第二半导体管芯104大于由电中介体118形成的封闭环路且因此大于第一半导体管芯102。结果,第二半导体管芯104完全覆盖了第一半导体管芯102,并且在所有方向上横向延伸超过第一半导体管芯102的外边缘侧110。此外,第二半导体管芯104在所有方向上到达电中介体118,使得封闭环路完全在第二半导体管芯104下方。
安装第二半导体管芯104包括将第二半导体管芯104的下侧108上的端子电连接到电中介体118的第一导电表面,例如,如参考图1所描述的。这可以例如使用诸如焊料或烧结物之类的导电粘合剂来完成。
在形成电连接之后,执行第二模制过程以封装第二半导体管芯104。结果,形成第二模制体138。这可以使用已知的模制技术来完成,诸如注射模制、传递模制等。可选地,在执行第二模制过程之前,底部填充140可以形成在第一和第二模制体的相交处。这可以使用已知的技术来完成。
在完成第二模制过程和底部填充过程之后,执行切割(例如,锯切)过程以在相邻组装件之间切断模制复合材料。结果,提供了如图4B和4C所示的多个单独的半导体管芯组装件100。在单个化之前或之后,焊球145可以形成在半导体管芯组装件的下侧108上,如图4C所示。
参考图5,根据另一实施例,描绘了电中介体118。在该实施例中,电中介体118被配置为模制互连衬底(MIS)。模制互连衬底以与图2所示的电中介体118类似的几何形状形成围绕中心开口146的封闭环路。模制互连衬底包括多个模制塑料层(例如环氧树脂)和布置在多个模制塑料层上的一个或多个金属化层。在一个或多个金属化层中形成导电迹线。这些导电迹线可以形成导电连接123的一部分。导电连接123还可以包括延伸穿过模制塑料层的通孔结构。
如图5A所示,在提供模制互连衬底之后,将其放置在临时载体148上。可以在临时载体148上提供粘合带,以在二者之间提供粘性接合。随后,将第一半导体管芯102放置在中心开口146中。随后,执行模制过程以用模制复合材料填充中心开口146并覆盖导电柱152。随后,去除临时载体148。例如以与参考图3A所述的类似方式执行平坦化步骤,其形成暴露导电柱152的模制复合材料的平坦上表面。
如图5B中所示,第二半导体管芯104附接且电连接到第一半导体管芯102的端子和电中介体118。在该示例中,使用倒装芯片技术,其中导电凸块145(例如,Sn凸块)被提供在第二半导体管芯104上。可选地,可以以与先前提供的方式类似的方式在拐角界面处提供底部填充140。可选地,可以以与前述类似的方式提供第二模制体138(图5中未示出)。
模制互连衬底的一个优点是它非常适合于典型的平坦化技术,诸如抛光和研磨。特别地,与其他材料(诸如玻璃纤维衬底)相比,模制互连衬底(例如模制塑料)更适于研磨。更一般地,图5的概念可以使用任何多层衬底来实现。
参考图6,根据另一实施例,描绘了电中介体118。根据该技术,电中介体118由导电片金属(例如铜)的平坦片来提供。平坦片的厚度可以与第一半导体管芯102的在上侧106和下侧108之间测量的厚度大致相同(例如,+/-5%)。
平坦片被构造成包括中心开口146和延伸到中心开口146中的一个或多个突起154。这种结构化可以使用已知的技术来完成,诸如蚀刻、冲压、冲孔等。在形成中心开口146和突起154之后,突起154的厚度可以在中心开口146的边缘侧和突起154的端部之间的位置处局部减小。结果,在中心开口的边缘侧和突起154的端部之间形成凹面156。突起154的端部包括保持片金属的原始厚度的竖直柱158。这些竖直柱158提供电中介体118的第一和第二平坦表面120、124中的一个,其中片金属的面对面的平坦侧提供了第一和第二平坦表面中的另一个。根据一个实施例,通过执行蚀刻过程来形成凹面156,由此将突起154的中心部分选择性地暴露于蚀刻剂化学品。
参考图7,参考图6描述的结构化片金属被放置在临时载体148上,所述临时载体可以与参考图2描述的临时载体148类似或相同。在该实施例中,结构化片金属被布置有向下面对临时载体148的凹面156。第一半导体管芯102被放置在中心开口146内,使得第一半导体管芯102的下侧108面对并搁置在临时载体148上。随后,执行与如先前描述的第一模制过程类似或相同的第一模制过程,使得中心开口146填充有电绝缘模制材料150。随后,执行与先前描述的平坦化过程类似或相同的平坦化过程以暴露出第一半导体管芯102的端子和突起154的平表面。结果,提供了如图7B所示的组装件,其中第一半导体管芯102的端子和电中介体118的第一导电表面是可电接入的。如可以看到的,突起154的平表面从模制复合材料150暴露,并且提供了电中介体118的第一平坦导电表面102。在模制复合材料150的相对侧(未图示),竖直柱158形成隔离的接合焊盘,其作为I/O端子144而可电接入。随后,第二半导体管芯104可以安装在第一半导体管芯102的顶部上,并且可以执行如前所述的电连接、第二模制过程、底部填充和单个化步骤。结果,提供了半导体芯片组装件100。
参考图8,根据一个实施例,描绘了半导体芯片组装件100。根据参考图7描述的相同技术来形成该半导体芯片组装件100,除了片金属安装在临时载体148上,其中凹面156背对临时载体148。结果,竖直柱158形成提供电中介体118的第一导电表面120的第一模制体136中的隔离的接合焊盘。在第一模制体136的相对侧处,突起154的平坦表面从模制复合材料暴露,并提供电中介体118的第二平坦导电表面124。此布置允许容易地将暴露的圆形接合焊盘(即,竖直柱158)焊接到第一半导体管芯102的端子。在半导体芯片组装件100的底侧处,为平坦连接界面142提供大表面积连接表面。
在可以与其他实施例组合的半导体芯片组装件的实施例中,半导体芯片组装件包括:第一和第二半导体管芯,该第一和第二半导体管芯各自包括面对面的上侧和下侧以及在第一和第二半导体管芯的相应上侧和下侧之间延伸的外边缘侧;以及电中介体,其包括设置在第一端处的第一导电表面、设置在与第一端相对的第二端处的第二导电表面、以及在第一和第二导电表面之间的导电连接,其中第二半导体管芯安装在第一半导体管芯和中介体的顶部上,使得:第二半导体管芯的下侧面对第一半导体管芯的上侧和中介体的第一端,第二半导体管芯的第一横向部分至少部分地覆盖第一半导体管芯的上侧,并且第二半导体管芯的第二横向部分延伸超过第一半导体管芯的外边缘侧并且在中介体的第一端上方,其中第一导电表面电连接到设置在第二半导体管芯的下侧上的第二半导体管芯的第一端子。
在可以与其他实施例组合的半导体芯片组装件的实施例中,半导体芯片组装件包括,第一半导体管芯包括具有导电表面的第三端子,其设置在第一半导体管芯的上侧处或上方,并且中介体的第一导电表面与第三端子的导电表面基本上共面。
在可以与其他实施例组合的半导体芯片组装件的实施例中,第三端子的导电表面设置在第一半导体管芯的上侧上方,并且其中第一导电表面突出远离电中介体的第一端的绝缘表面。
在可以与其他实施例组合的半导体芯片组装件的实施例中,电中介体形成围绕中心开口的封闭环路,并且第一半导体管芯设置在中心开口内。
在可以与其他实施例组合的半导体芯片组装件的实施例中,第二半导体管芯完全覆盖第一半导体管芯并且在所有方向上横向延伸超过第一半导体的外边缘侧,使得封闭环路在第二半导体管芯下方。
在可以与其他实施例组合的半导体芯片组装件的实施例中,中介体包括绝缘体,其包括在中介体的第一端和第二端之间延伸的电绝缘侧壁,并且其中导电连接通过包含在绝缘体内的电导体来提供。
在可以与其他实施例组合的半导体芯片组装件的实施例中,中介体由印刷电路板衬底形成,并且其中导电连接包括延伸穿过印刷电路板衬底的一个或多个层的导电通孔。
在可以与其他实施例组合的半导体芯片组装件的实施例中,中介体由模制互连衬底形成,其包括一个或多个模制塑料层和布置在一个或多个模制塑料层上的一个或多个金属化层,并且导电连接包括形成在一个或多个金属化层中的导电迹线。
在可以与其他实施例组合的半导体芯片组装件的实施例中,中介体包括:导电片金属的平坦片;一个或多个突起,从中心开口的边缘侧延伸;位于一个或多个突起的端处的竖直柱;以及在竖直柱与中心开口的边缘侧之间的一个或多个突起中的凹面。
在可以与其他实施例组合的半导体芯片组装件的实施例中,凹面背对第二半导体管芯的下侧,并且第一导电表面通过与凹面中的一个相对的一个或多个突起的平表面来提供。
在可以与其他实施例组合的半导体芯片组装件的实施例中,凹面面向第二半导体管芯的下侧,并且第一导电表面通过与凹面中的一个紧邻的竖直柱的表面来提供。
在可以与其他实施例组合的半导体芯片组装件的实施例中,半导体芯片组装件包括放大器管芯,包括面对面的上侧和下侧、以及设置在放大器管芯的上侧上的输入端子;控制器管芯,包括面对面的上侧和下侧、设置在控制器管芯的下侧上的输出端子和输入端子;电中介体,包括设置在第一端处的第一导电表面、设置在与所述第一端相对的第二端处的第二导电表面、以及在第一导电表面与第二导电表面之间的导电连接;以及平坦连接界面,设置在第一半导体管芯的下侧处或下方,所述平坦连接界面包括多个导电I/O端子,其中控制器管芯安装在放大器管芯的顶部上,使得包括控制器管芯的输出端子的控制器管芯的第一横向部分与放大器管芯的输入端子对准并电连接,并且包括控制器管芯的输入端子的控制器管芯的第二横向部分与中介体的第一导电表面对准并电连接,并且其中电中介体在I/O端子中的第一I/O端子和控制器管芯的输入端子之间提供电连接。
在可以与其他实施例组合的半导体芯片组装件的实施例中,所述半导体芯片组装件还包括封装控制器管芯和中介体的电绝缘模制复合材料体,其中第一半导体管芯的下侧和第二导电表面在模制复合材料体的底侧处暴露,并且其中第一I/O端子通过第二导电表面来提供。
在可以与其他实施例组合的提供半导体芯片组装件的方法的实施例中,该方法包括提供第一和第二半导体管芯,所述第一和第二半导体管芯各自包括面对面的上侧和下侧以及在第一和第二半导体管芯的相应上侧和下侧之间延伸的外边缘侧;提供电中介体,其包括设置在第一端处的第一导电表面、设置在与所述第一端相对的第二端处的第二导电表面、以及在第一导电表面与第二导电表面之间的导电连接;以及将第二半导体管芯安装在第一半导体管芯和中介体的顶部上,使得:第二半导体管芯的下侧面对第一半导体管芯的上侧和中介体的第一端;第二半导体管芯的第一横向部分至少部分地覆盖第一半导体管芯的上侧;以及第二半导体管芯的第二横向部分延伸超过第一半导体管芯的外边缘侧并且在中介体的第一端上方,以及将第一导电表面电连接到设置在第二半导体管芯的下侧上的第一导电端子。
在可以与其他实施例组合的提供半导体芯片组装件的方法的实施例中,第一半导体管芯包括具有导电表面的第三端子,其设置在第一半导体管芯的上侧上方,其中第一导电表面突出远离电中介体的第一端的绝缘表面,并且将第二半导体管芯安装在第一半导体管芯和中介体的顶部上包括将中介体的第一导电表面布置成与第三端子的导电表面基本上共面。
在可以与其他实施例组合的提供半导体芯片组装件的方法的实施例中,将第二半导体管芯安装在第一半导体管芯和中介体的顶部上包括:将第一半导体管芯和中介体放置在临时载体上,使得半导体管芯的下侧和中介体的第二端直接面对并搁置在临时载体上;执行第一模制过程,其利用电绝缘模制复合材料来封装第一半导体管芯和中介体;以及执行平坦化过程,其从模制复合材料暴露中介体的第一导电表面和第三端子的导电表面。
在可以与其他实施例组合的提供半导体芯片组装件的方法的实施例中,电中介体形成围绕中心开口的封闭环路,并且布置第一半导体管芯和中介体包括将第一半导体管芯放置在中心开口内以使得外边缘侧在所有方向上与封闭环路间隔开,并且执行第一模制过程包括用电绝缘模制复合材料填充中心开口。
在可以与其他实施例组合的提供半导体芯片组装件的方法的实施例中,提供电中介体包括:提供导电片金属的平坦片;将平坦片构造成包括中心开口和从封闭环路的边缘侧延伸的一个或多个突起;以及减小在封闭环路的边缘侧与突起的端部之间的一个或多个突起的厚度,从而在封闭环路的边缘侧与突起的端部处的竖直柱之间形成凹面。
在可以与其他实施例组合的提供半导体芯片组装件的方法的实施例中,布置第一半导体管芯和中介体包括将电中介体放置在临时载体上以使得凹面面对临时载体。
在可以与其他实施例组合的提供半导体芯片组装件的方法的实施例中,布置第一半导体管芯和中介体包括将电中介体放置在临时载体上以使得凹面背对临时载体。
术语"电连接"、"直接电连接"等描述了例如相关元件之间的线连接的电连接元件之间的永久低欧姆(即低电阻)连接。相比之下,术语"电耦合"描述了在相关元件之间具有不可忽略的阻抗(电阻性或电抗性)的连接。例如,诸如晶体管的有源元件以及诸如电感器、电容器、二极管、电阻器等的无源元件可以将两个元件电耦合在一起。
术语"基本上"包括与要求的绝对一致性以及由于制造过程变化、组装和可能导致与期望参数的偏差的其他因素而引起的与要求的绝对一致性的微小偏差。假设偏差在过程公差内以便实现实际一致性,并且本文所述的组件能够根据应用要求起作用,则术语"基本上"涵盖了这些偏差中的任何偏差。
如本文所用的诸如"相同"、"匹配"的术语旨在意指相同、几乎相同或近似,使得在不脱离本发明精神的情况下,设想了一些合理的变化量。此外,诸如"第一"、"第二"等的术语用于描述各种元件、区、部分等,并且也不意图进行限制。在整个说明书中,相同的术语指相同的元件。
诸如"下"、"下方"、"下部"、"上方"、"上部"等的空间相对术语出于方便描述被用于解释一个元件相对于第二元件的定位。这些术语旨在包括除了与图中所示的那些不同的取向之外的设备的不同取向。
如本文所用,术语"具有"、"含有"、"包括"、"包含"等是开放式术语,其指示所陈述的元件或特征的存在,但不排除附加的元件或特征。冠词"一"、"一个"和"该"意图包括复数以及单数,除非上下文另外清楚地指出。
应当理解,除非另外特别指出,否则本文所述的各种实施例的特征可以彼此组合。
尽管这里已经说明和描述了具体实施例,但是本领域普通技术人员应当理解,在不脱离本发明范围的情况下,各种替代和/或等效实现可以替代所示出和描述的具体实施例。本申请旨在覆盖这里所讨论的具体实施例的任何修改或变化。因此,意图的是,本发明仅由权利要求及其等同物来限定。
Claims (20)
1.一种半导体芯片组装件,包括:
第一和第二半导体管芯,所述第一和第二半导体管芯各自包括面对面的上侧和下侧以及在所述第一和第二半导体管芯的相应上侧和下侧之间延伸的外边缘侧;以及
电中介体,其包括设置在第一端处的第一导电表面、设置在与所述第一端相对的第二端处的第二导电表面、以及在第一导电表面与第二导电表面之间的导电连接;
其中第二半导体管芯安装在第一半导体管芯和中介体的顶部上,使得:
第二半导体管芯的下侧面对第一半导体管芯的上侧和中介体的第一端;
第二半导体管芯的第一横向部分至少部分地覆盖第一半导体管芯的上侧;并且
第二半导体管芯的第二横向部分延伸超过第一半导体管芯的外边缘侧并且在中介体的第一端上方,
其中第一导电表面电连接到设置在第二半导体管芯的下侧上的第二半导体管芯的第一端子。
2.根据权利要求1所述的半导体芯片组装件,其中第一半导体管芯包括具有导电表面的第三端子,其设置在第一半导体管芯的上侧处或上方,并且其中,中介体的第一导电表面与第三端子的导电表面基本上共面。
3.根据权利要求2所述的半导体芯片组装件,其中第三端子的导电表面设置在第一半导体管芯的上侧上方,并且其中第一导电表面突出远离电中介体的第一端的绝缘表面。
4.根据权利要求2所述的半导体芯片组装件,其中电中介体形成围绕中心开口的封闭环路,并且其中第一半导体管芯设置在中心开口内。
5.根据权利要求4所述的半导体芯片组装件,其中第二半导体管芯完全覆盖第一半导体管芯并且在所有方向上横向延伸超过第一半导体的外边缘侧,并且其中封闭环路至少部分地在第二半导体管芯下方。
6.根据权利要求5所述的半导体芯片组装件,其中,中介体包括绝缘体,其包括在中介体的第一端和第二端之间延伸的电绝缘侧壁,并且其中导电连接通过包含在绝缘体内的电导体来提供。
7.根据权利要求6所述的半导体芯片组装件,其中,中介体由印刷电路板衬底形成,并且其中导电连接包括延伸穿过印刷电路板衬底的一个或多个层的导电通孔。
8.根据权利要求6所述的半导体芯片组装件,其中,中介体由模制互连衬底形成,其包括一个或多个模制塑料层和布置在一个或多个模制塑料层上的一个或多个金属化层,并且其中导电连接包括形成在一个或多个金属化层中的导电迹线。
9.根据权利要求4所述的半导体芯片组装件,其中,中介体包括:
导电片金属的平坦片;
一个或多个突起,从中心开口的边缘侧延伸;
位于一个或多个突起的端处的竖直柱;以及
在竖直柱与中心开口的边缘侧之间的一个或多个突起中的凹面。
10.根据权利要求9所述的半导体芯片组装件,其中,凹面背对第二半导体管芯的下侧,并且第一导电表面通过与凹面中的一个相对的一个或多个突起的平表面来提供。
11.根据权利要求9所述的半导体芯片组装件,其中,凹面面向第二半导体管芯的下侧,并且第一导电表面通过与凹面中的一个紧邻的竖直柱的表面来提供。
12.一种半导体芯片组装件,包括:
放大器管芯,包括面对面的上侧和下侧、以及设置在放大器管芯的上侧上的输入端子;
控制器管芯,包括面对面的上侧和下侧、设置在控制器管芯的下侧上的输出端子和输入端子;
电中介体,包括设置在第一端处的第一导电表面、设置在与所述第一端相对的第二端处的第二导电表面、以及在第一导电表面与第二导电表面之间的导电连接;以及
平坦连接界面,设置在第一半导体管芯的下侧处或下方,所述平坦连接界面包括多个导电I/O端子,
其中控制器管芯安装在放大器管芯的顶部上,使得包括控制器管芯的输出端子的控制器管芯的第一横向部分与放大器管芯的输入端子对准并电连接,并且包括控制器管芯的输入端子的控制器管芯的第二横向部分与中介体的第一导电表面对准并电连接,并且
其中电中介体在I/O端子中的第一I/O端子和控制器管芯的输入端子之间提供电连接。
13.根据权利要求12所述的半导体芯片组装件,其中所述半导体芯片组装件还包括封装控制器管芯和中介体的电绝缘模制复合材料体,其中第一半导体管芯的下侧和第二导电表面在模制复合材料体的底侧处暴露,并且其中第一I/O端子通过第二导电表面来提供。
14.一种提供半导体芯片组装件的方法,所述方法包括:
提供第一和第二半导体管芯,所述第一和第二半导体管芯各自包括面对面的上侧和下侧以及在第一和第二半导体管芯的相应上侧和下侧之间延伸的外边缘侧;
提供电中介体,其包括设置在第一端处的第一导电表面、设置在与所述第一端相对的第二端处的第二导电表面、以及在第一导电表面与第二导电表面之间的导电连接;以及
将第二半导体管芯安装在第一半导体管芯和中介体的顶部上,使得:
第二半导体管芯的下侧面对第一半导体管芯的上侧和中介体的第一端;
第二半导体管芯的第一横向部分至少部分地覆盖第一半导体管芯的上侧;以及
第二半导体管芯的第二横向部分延伸超过第一半导体管芯的外边缘侧并且在中介体的第一端上方,以及
将第一导电表面电连接到设置在第二半导体管芯的下侧上的第一导电端子。
15.根据权利要求14所述的方法,其中,第一半导体管芯包括具有导电表面的第三端子,其设置在第一半导体管芯的上侧上方,其中第一导电表面突出远离电中介体的第一端的绝缘表面,并且其中将第二半导体管芯安装在第一半导体管芯和中介体的顶部上包括将中介体的第一导电表面布置成与第三端子的导电表面基本上共面。
16.根据权利要求15所述的方法,其中,将第二半导体管芯安装在第一半导体管芯和中介体的顶部上包括:
将第一半导体管芯和中介体放置在临时载体上,使得半导体管芯的下侧和中介体的第二端直接面对并搁置在临时载体上;
执行第一模制过程,其利用电绝缘模制复合材料来封装第一半导体管芯和中介体;以及
执行平坦化过程,其从模制复合材料暴露中介体的第一导电表面和第三端子的导电表面。
17.根据权利要求16所述的方法,其中,电中介体形成围绕中心开口的封闭环路,并且其中布置第一半导体管芯和中介体包括将第一半导体管芯放置在中心开口内以使得外边缘侧在所有方向上与封闭环路间隔开,并且其中执行第一模制过程包括用电绝缘模制复合材料填充中心开口。
18.根据权利要求17所述的方法,其中,提供电中介体包括:
提供导电片金属的平坦片;
将平坦片构造成包括中心开口和从封闭环路的边缘侧延伸的一个或多个突起;以及
减小在封闭环路的边缘侧与突起的端部之间的一个或多个突起的厚度,从而在封闭环路的边缘侧与突起的端部处的竖直柱之间形成凹面。
19.根据权利要求18所述的方法,其中,布置第一半导体管芯和中介体包括将电中介体放置在临时载体上以使得凹面面对临时载体。
20.根据权利要求18所述的方法,其中,布置第一半导体管芯和中介体包括将电中介体放置在临时载体上以使得凹面背对临时载体。
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