TWI778654B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TWI778654B
TWI778654B TW110120989A TW110120989A TWI778654B TW I778654 B TWI778654 B TW I778654B TW 110120989 A TW110120989 A TW 110120989A TW 110120989 A TW110120989 A TW 110120989A TW I778654 B TWI778654 B TW I778654B
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electronic
conductive
cladding layer
package
manufacturing
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TW202249229A (zh
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符毅民
何祈慶
王愉博
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矽品精密工業股份有限公司
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Priority to TW110120989A priority Critical patent/TWI778654B/zh
Priority to CN202110760921.8A priority patent/CN115458485A/zh
Priority to US17/829,533 priority patent/US20220399246A1/en
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Abstract

一種電子封裝件，係將一橫向擴散金屬氧化物半導體(LDMOS)形式電子結構接置於一互補式金屬氧化物半導體(CMOS)形式電子元件上，以整合成晶片模組，因而能縮短兩者之間的電性傳輸路徑，以加速兩者間的電訊傳遞時間。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種具有多晶片模組之電子封裝件及其製法。
現今高速運算應用的終端產品(如自動駕駛、超級電腦或行動裝置等)正蓬勃發展，其內部皆設有經封裝完成之半導體封裝元件(晶片結合於封裝基板上)，藉此使相關終端產品發揮作用，並應用於前述相關領域。
目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組，或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
圖1係習知電子裝置1之立體示意圖。如圖1所示，該電子裝置1係包括：一配置有複數晶片元件11之電路板10、設於該電路板10上之電子元件16、一功能元件12以及封裝體13。
在高壓功率集成電路中，常採用高壓的橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor，縮寫LDMOS)型之半導體晶 片(如其中一晶片元件11所用之晶片規格)滿足耐高壓、實現功率控制等方面的要求，以利於設計微波/射頻功率電路。
再者，藉由互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor，縮寫作CMOS)型之電子元件16配合該LDMOS型之半導體晶片，以同時為多媒體服務提供更高的數據傳輸率。
惟，習知電子裝置1中，係將LDMOS型之半導體晶片與CMOS型之電子元件16分別置放於該電路板10之表面之不同位置上，使該兩種形式之晶片需藉由該電路板10內之電路進行電性連接，致使該晶片元件11與該電子元件16之間的訊號傳輸速度不夠快，導致無法達到現今終端產品的電性效能需求。
再者，該晶片元件11與該電子元件16佔用該電路板10之封裝區域表面(該封裝體13之佈設區域)上過多之佈設面積，使該電路板10之佈設空間有限，因而難以配置更多功能元件12，導致單一電子裝置1已無法符合現今終端產品相關輕薄短小、低功耗、高電性效能等需求。
另一方面，若需增設其它功能(如天線功能)之功能元件14，則需擴增該電路板10之佈設面積，如圖1所示之封裝體13外之區域，其中，該功能元件14係藉由一傳輸線17電性連接該電子元件16，且該封裝體13覆蓋該晶片元件11與該部分傳輸線17。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：電子元件；電子結構，係設於該電子元件上且電性連接該電子元件，以令該電子元件與該電子結構作為晶片模組；至少一導電柱，係設於該電子元件上且電性連接該電子元件；以及包覆層，係形成於該電子元件上，以包覆該電子結構與該導電柱。
本發明復提供一種電子封裝件之製法，係包括：將至少一電子結構與至少一導電柱設於一電子元件上，且使該電子元件電性連接該電子結構與該導電柱，以令該電子元件與該電子結構作為晶片模組；以及形成一包覆層於該電子元件上，以包覆該電子結構與該導電柱。
前述之電子封裝件及其製法中，該電子結構係藉由複數導電凸塊電性連接該電子元件。例如，該電子結構係藉由導電體結合該導電凸塊。
前述之電子封裝件及其製法中，該包覆層之表面係齊平該導電柱之端面。
前述之電子封裝件及其製法中，該導電柱之端面係外露出該包覆層之表面。
前述之電子封裝件及其製法中，復包括形成至少一導電元件於該包覆層上，且令該導電元件電性連接該導電柱。
前述之電子封裝件及其製法中，復包括形成線路結構於該包覆層上，且令該線路結構電性連接該導電柱。例如，復包括形成至少一導電元件於該線路結構上，且令該導電元件電性連接該線路結構。或者，該線路結構係為單一金屬層形式。亦或，該線路結構係接觸該電子結構。
前述之電子封裝件及其製法中，復包括先以封裝層覆蓋該電子元件周圍，再將該包覆層形成於該封裝層上，使該包覆層包覆該電子結構與該導電柱。
由上可知，本發明之電子封裝件及其製法中，主要藉由將該電子結構堆疊於該電子元件上以近距離配合該電子元件，故相較於習知技術，本發明之電子封裝件可節省終端產品之電路板或載板上之置放空間或置放面積，因而有利於終端產品之電路板或載板之元件配置，使終端產品之電路板或載板於其它佈設區域上可依需求增設其它功能之電子組件。
再者，將將該電子元件及該電子結構整合成一晶片模組，可縮短兩者之間的電性傳輸路徑，以加速兩者間的電訊傳遞時間，故相較於習知技術，本發明之電子封裝件更能符合終端產品之電性效能需求。
1:電子裝置
10:電路板
11:晶片元件
12,14:功能元件
13:封裝體
16:電子元件
17:傳輸線
2,3:電子封裝件
2a:晶片模組
21:電子結構
21a:第一側
21b:第二側
210:電極墊
22:導電凸塊
23:導電柱
23b:端面
24:結合層
25:包覆層
25a:第一表面
25b:第二表面
26:線路結構
27:導電元件
28:散熱結構
29:電子元件
29a:作用面
29b:非作用面
290:電極墊
35:封裝層
38:導電體
9:承載板
90:黏著層
91:離形層
S:切割路徑
圖1係為習知電子裝置之立體示意圖。
圖2A至圖2F係為本發明之電子封裝件之製法之第一實施例之剖視示意圖。
圖3A至圖3F係為本發明之電子封裝件之製法之第二實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的 下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2F係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如圖2A所示，提供一電子結構21，且該電子結構21具有相對之第一側21a與第二側21b。
於本實施例中，該電子結構21係為主動元件，如橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor，縮寫LDMOS)型之半導體晶片，其第一側21a具有複數用以結合導電凸塊22之導電體38。例如，該電子結構21之第一側21a上具有複數電極墊210，以結合該導電體38。
如圖2B所示，提供一設於承載板9上之電子元件29，且該電子元件29上形成有複數導電柱23。
該電子元件29可為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。於本實施例中，該電子元件29係為半導體晶片，如互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor，縮寫作CMOS)型之功能晶片，其具有相對之作用面29a與非作用面29b，且其作用面29a上具有複數電極墊290，並以其非作用面29b設於該承載板9上。
再者，該承載板9係例如為半導體材質(如矽或玻璃)之板體，其上可依需求形成有一離形層91(或黏著層90)，以供該電子元件29設於該離形層91上。
又，該導電柱23係設於該電子元件29之其中一部分電極墊290上並電性連接該電極墊290，且形成該導電柱23之材質係為如銅之金屬材或銲錫材。
如圖2C所示，將該電子結構21以其導電凸塊22設於該電子元件29之作用面29a上。
於本實施例中，該電子結構21係以覆晶方式藉由複數導電凸塊22結合至該電子元件29之另一部分電極墊290上以電性連接該電極墊290。例如，可依需求以如底膠之結合層24包覆該些導電凸塊22與導電體38。
如圖2D所示，形成一包覆層25於該承載板9之離形層91上及該電子元件29之作用面29a上，以令該包覆層25包覆該電子結構21、結合層24與該些導電柱23，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合該承載板9之離形層91。接著，藉由整平製程，使該包覆層25之第二表面25b齊平該導電柱23之端面23b與該電子結構21之第二側21b，令該導電柱23之端面23b與該電子結構21之第二側21b外露出該包覆層25之第二表面25b。
於本實施例中，該包覆層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載板9上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質、該電子結構21之第二側21b之部分材質與該包覆層25之部分材質。
又，若未形成該結合層24，該包覆層25可包覆該些導電凸塊22與導電體38。
如圖2E所示，形成一線路結構26於該包覆層25之第二表面25b上，且令該線路結構26電性連接該些導電柱23，並使該線路結構26接觸該電子結構21之第二側21b。
於本實施例中，該線路結構26係為單一金屬層形式。例如，形成該金屬層之材質係為銅，且其接觸該電子結構21以供散熱用。
再者，可於該線路結構26上形成複數如銲球之導電元件27。
如圖2F所示，移除該承載板9及其上之離形層91與黏著層90，以外露該電子元件29之非作用面29b與該包覆層25之第一表面25a，再沿如圖2E所示之切割路徑S進行切單製程，以獲取該電子封裝件2。
於本實施例中，該電子封裝件2可於後續製程中藉由該些導電元件27接置於一如電路板之電子裝置(圖未示)上。
再者，該電子封裝件2可依需求於該包覆層25之第一表面25a上配置一散熱結構28，如散熱架、散熱鰭片、散熱膠或其它適當散熱材，其接觸該電子元件29之非作用面29b。
因此，本發明之製法係將CMOS(如電子元件29)及LDMOS(如電子結構21)整合成一晶片模組2a，如圖2C所示，以節省終端產品之電路板或載板上之置放空間或置放面積，故相較於習知技術，本發明之電子封裝件2有利於終端產品之電路板或載板之元件配置，使終端產品之電路板或載板於其它佈設區域上可依需求增設其它功能之電子組件。
再者，將CMOS(如電子元件29)及LDMOS(如電子結構21)整合成一晶片模組2a，可縮短兩者之間的電性傳輸路徑，以加速兩者間的電訊傳遞時間，故相較於習知技術，本發明之電子封裝件2更能符合終端產品之電性效能需求。
圖3A至圖3F係為本發明之電子封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於封裝之態樣，其它製程大致相同，故以下不再贅述相同處。
如圖3A所示，首先採用如圖2A至圖2B所示之製程。
如圖3B所示，於該承載板9之離形層91上形成一封裝層35，以覆蓋該電子元件29之周圍。
於本實施例中，該封裝層35係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該承載板9上。
如圖3C所示，將該電子結構21以其導電凸塊22設於該電子元件29之作用面29a上。
如圖3D所示，形成一包覆層25於該封裝層35上及該電子元件29之作用面29a上，以令該包覆層25包覆該電子結構21、結合層24與該些導電柱23，其中，該包覆層25係以其第一表面25a結合該封裝層35。接著，進行整平製程。
於本實施例中，該包覆層25與該封裝層35之材質可依需求相同或相異。
如圖3E所示，形成一線路結構26於該包覆層25之第二表面25b上，並於該線路結構26上形成複數如銲球之導電元件27。
如圖3F所示，移除該承載板9及其上之離形層91與黏著層90，以外露該電子元件29之非作用面29b與該封裝層35，再沿如圖3E所示之切割路徑S進行切單製程，以獲取該電子封裝件3，且可依需求於該封裝層35上配置一散熱結構28，如散熱片，其接觸該電子元件29之非作用面29b。
本發明復提供一種電子封裝件2,3，係包括：一電子結構21、一電子元件29、複數導電柱23以及一包覆層25。
所述之電子結構21係設於該電子元件29上且電性連接該電子元件29，以令該電子元件29與該電子結構21作為晶片模組2a。
所述之導電柱23係設於該電子元件29上且電性連接該電子元件29。
所述之包覆層25係形成於該電子元件29上，以包覆該電子結構21與導電柱23。
於一實施例中，該電子結構21係藉由複數導電凸塊22電性連接該電子元件29。例如，該電子結構21係藉由導電體38結合該導電凸塊22。
於一實施例中，該包覆層25之第二表面25b係齊平該導電柱23之端面23b。
於一實施例中，該導電柱23之端面23b係外露出該包覆層25之第二表面25b。
於一實施例中，所述之電子封裝件2,3復包括形成於該包覆層25上之複數導電元件27，以令該複數導電元件27電性連接該導電柱23。
於一實施例中，所述之電子封裝件2,3復包括形成於該包覆層25上之線路結構26，以令該線路結構26電性連接該導電柱23。進一步，所述之電子封裝件2,3復包括形成於該線路結構26上之複數導電元件27，以令該複數導電元件27電性連接該線路結構26。例如，該線路結構26係為單一金屬層形式。或者，該線路結構26係接觸該電子結構21。
於一實施例中，所述之電子封裝件3復包括覆蓋該電子元件29周圍之封裝層35，以令該包覆層25形成於該封裝層35上。
綜上所述，本發明之電子封裝件及其製法，係藉由將該電子結構堆疊於該電子元件上以近距離配合該電子元件，故本發明無需重新設計電路板，因而能大幅節省製作成本，且無需擴增電路板之尺寸，以利於滿足微小化之需求，並有利於呈現高電性效能。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
21:電子結構
22:導電凸塊
23:導電柱
24:結合層
25:包覆層
25a:第一表面
25b:第二表面
26:線路結構
27:導電元件
28:散熱結構
29:電子元件
29b:非作用面
38:導電體

Claims (20)

  1. 一種電子封裝件，係包括：電子元件；電子結構，係設於該電子元件上且電性連接該電子元件，以令該電子元件與該電子結構作為晶片模組；至少一導電柱，係設於該電子元件上且電性連接該電子元件；包覆層，係形成於該電子元件上，以包覆該電子結構與該導電柱，且該電子結構之一側露出於該包覆層外；以及一線路結構，係形成於該包覆層上，以接觸該電子結構之一側，俾供該電子結構散熱用。
  2. 如請求項1所述之電子封裝件，其中，該電子結構係藉由複數導電凸塊電性連接該電子元件。
  3. 如請求項2所述之電子封裝件，其中，該電子結構係藉由導電體結合該導電凸塊。
  4. 如請求項1所述之電子封裝件，其中，該包覆層之表面係齊平該導電柱之端面。
  5. 如請求項1所述之電子封裝件，其中，該導電柱之端面係外露出該包覆層之表面。
  6. 如請求項1所述之電子封裝件，復包括至少一形成於該包覆層上之導電元件，且令該導電元件電性連接該導電柱。
  7. 如請求項1所述之電子封裝件，其中，該線路結構電性連接該導電柱。
  8. 如請求項7所述之電子封裝件，復包括至少一形成於該線路結構上之導電元件，且令該導電元件電性連接該線路結構。
  9. 如請求項7所述之電子封裝件，其中，該線路結構係為單一金屬層形式。
  10. 如請求項1所述之電子封裝件，復包括覆蓋該電子元件周圍之封裝層，以令該包覆層形成於該封裝層上。
  11. 一種電子封裝件之製法，係包括：將至少一電子結構與至少一導電柱設於一電子元件上，且使該電子元件電性連接該電子結構與該導電柱，以令該電子元件與該電子結構作為晶片模組；形成一包覆層於該電子元件上，以包覆該電子結構與該導電柱，且令該電子結構之一側露出於該包覆層外；以及形成一線路結構於該包覆層上，以接觸該電子結構之一側，俾供該電子結構散熱用。
  12. 如請求項11所述之電子封裝件之製法，其中，該電子結構係藉由複數導電凸塊電性連接該電子元件。
  13. 如請求項12所述之電子封裝件之製法，其中，該電子結構係藉由導電體結合該導電凸塊。
  14. 如請求項11所述之電子封裝件之製法，其中，該包覆層之表面係齊平該導電柱之端面。
  15. 如請求項11所述之電子封裝件之製法，其中，該導電柱之端面係外露出該包覆層之表面。
  16. 如請求項11所述之電子封裝件之製法，復包括形成至少一導電元件於該包覆層上，且令該導電元件電性連接該導電柱。
  17. 如請求項11所述之電子封裝件之製法，其中，該線路結構電性連接該導電柱。
  18. 如請求項17所述之電子封裝件之製法，復包括形成至少一導電元件於該線路結構上，且令該導電元件電性連接該線路結構。
  19. 如請求項17所述之電子封裝件之製法，其中，該線路結構係為單一金屬層形式。
  20. 如請求項11所述之電子封裝件之製法，復包括先以封裝層覆蓋該電子元件周圍，再將該包覆層形成於該封裝層上，使該包覆層包覆該電子結構與該導電柱。
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Citations (3)

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Publication number Priority date Publication date Assignee Title
TW201719829A (zh) * 2015-11-16 2017-06-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202013634A (zh) * 2018-09-19 2020-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202036808A (zh) * 2019-03-18 2020-10-01 矽品精密工業股份有限公司 電子封裝件及其製法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201719829A (zh) * 2015-11-16 2017-06-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202013634A (zh) * 2018-09-19 2020-04-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202036808A (zh) * 2019-03-18 2020-10-01 矽品精密工業股份有限公司 電子封裝件及其製法

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