CN115458485A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN115458485A
CN115458485A CN202110760921.8A CN202110760921A CN115458485A CN 115458485 A CN115458485 A CN 115458485A CN 202110760921 A CN202110760921 A CN 202110760921A CN 115458485 A CN115458485 A CN 115458485A
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electronic
conductive
layer
encapsulation layer
electrically connected
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符毅民
何祈庆
王愉博
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

本发明涉及一种电子封装件及其制法，包括将一横向扩散金属氧化物半导体(LDMOS)形式电子结构接置于一互补式金属氧化物半导体(CMOS)形式电子元件上，以整合成芯片模块，因而能缩短两者之间的电性传输路径，以加速两者间的电讯传递时间。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体装置，尤指一种具有多芯片模块的电子封装件及其制法。
背景技术
现今高速运算应用的终端产品(如自动驾驶、超级电脑或行动装置等)正蓬勃发展，其内部皆设有经封装完成的半导体封装元件(芯片结合于封装基板上)，借此使相关终端产品发挥作用，并应用于前述相关领域。
目前应用于芯片封装领域的技术，包含有例如芯片尺寸构装(Chip ScalePackage，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模块封装(Multi-Chip Module，简称MCM)等覆晶型态的封装模块，或将芯片立体堆叠化整合为三维积体电路(3D IC)芯片堆叠技术等。
图1为现有电子装置1的立体示意图。如图1所示，该电子装置1包括：一配置有多个芯片元件11的电路板10、设于该电路板10上的电子元件16、一功能元件12以及封装体13。
在高压功率集成电路中，常采用高压的横向扩散金属氧化物半导体(LaterallyDiffused Metal Oxide Semiconductor，缩写LDMOS)型的半导体芯片(如其中一芯片元件11所用的芯片规格)满足耐高压、实现功率控制等方面的要求，以利于设计微波/射频功率电路。
此外，经由互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，缩写作CMOS)型的电子元件16配合该LDMOS型的半导体芯片，以同时为多媒体服务提供更高的数据传输率。
然而，现有电子装置1中，将LDMOS型的半导体芯片与CMOS型的电子元件16分别置放于该电路板10的表面的不同位置上，使该两种形式的芯片需经由该电路板10内的电路进行电性连接，致使该芯片元件11与该电子元件16之间的信号传输速度不够快，导致无法达到现今终端产品的电性效能需求。
此外，该芯片元件11与该电子元件16占用该电路板10的封装区域表面(该封装体13的布设区域)上过多的布设面积，使该电路板10的布设空间有限，因而难以配置更多功能元件12，导致单一电子装置1已无法符合现今终端产品相关轻薄短小、低功耗、高电性效能等需求。
另一方面，若需增设其它功能(如天线功能)的功能元件14，则需扩增该电路板10的布设面积，如图1所示的封装体13外的区域，其中，该功能元件14经由一传输线17电性连接该电子元件16，且该封装体13覆盖该芯片元件11与该部分传输线17。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，能缩短两者之间的电性传输路径，以加速两者间的电讯传递时间。
本发明的电子封装件，包括：电子元件；电子结构，其设于该电子元件上且电性连接该电子元件，以令该电子元件与该电子结构作为芯片模块；至少一导电柱，其设于该电子元件上且电性连接该电子元件；以及包覆层，其形成于该电子元件上，以包覆该电子结构与该导电柱。
本发明还提供一种电子封装件的制法，包括：将至少一电子结构与至少一导电柱设于一电子元件上，且使该电子元件电性连接该电子结构与该导电柱，以令该电子元件与该电子结构作为芯片模块；以及形成一包覆层于该电子元件上，以包覆该电子结构与该导电柱。
前述的电子封装件及其制法中，该电子结构经由多个导电凸块电性连接该电子元件。例如，该电子结构经由导电体结合该导电凸块。
前述的电子封装件及其制法中，该包覆层的表面齐平该导电柱的端面。
前述的电子封装件及其制法中，该导电柱的端面外露出该包覆层的表面。
前述的电子封装件及其制法中，还包括形成至少一导电元件于该包覆层上，且令该导电元件电性连接该导电柱。
前述的电子封装件及其制法中，还包括形成线路结构于该包覆层上，且令该线路结构电性连接该导电柱。例如，还包括形成至少一导电元件于该线路结构上，且令该导电元件电性连接该线路结构。或者，该线路结构为单一金属层形式。抑或，该线路结构接触该电子结构。
前述的电子封装件及其制法中，还包括先以封装层覆盖该电子元件周围，再将该包覆层形成于该封装层上，使该包覆层包覆该电子结构与该导电柱。
由上可知，本发明的电子封装件及其制法中，主要经由将该电子结构堆叠于该电子元件上以近距离配合该电子元件，故相比于现有技术，本发明的电子封装件可节省终端产品的电路板或载板上的置放空间或置放面积，因而有利于终端产品的电路板或载板的元件配置，使终端产品的电路板或载板于其它布设区域上可依需求增设其它功能的电子组件。
此外，将该电子元件及该电子结构整合成一芯片模块，可缩短两者之间的电性传输路径，以加速两者间的电讯传递时间，故相比于现有技术，本发明的电子封装件更能符合终端产品的电性效能需求。
附图说明
图1为现有电子装置的立体示意图。
图2A至图2F为本发明的电子封装件的制法的第一实施例的剖视示意图。
图3A至图3F为本发明的电子封装件的制法的第二实施例的剖视示意图。
附图标记说明
1:电子装置
10:电路板
11:芯片元件
12,14:功能元件
13:封装体
16:电子元件
17:传输线
2,3:电子封装件
2a:芯片模块
21:电子结构
21a:第一侧
21b:第二侧
210:电极垫
22:导电凸块
23:导电柱
23b:端面
24:结合层
25:包覆层
25a:第一表面
25b:第二表面
26:线路结构
27:导电元件
28:散热结构
29:电子元件
29a:作用面
29b:非作用面
290:电极垫
35:封装层
38:导电体
9:承载板
90:粘着层
91:离形层
S:切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明的电子封装件2的制法的第一实施例的剖面示意图。
如图2A所示，提供一电子结构21，且该电子结构21具有相对的第一侧21a与第二侧21b。
于本实施例中，该电子结构21为主动元件，如横向扩散金属氧化物半导体(Laterally Diffused Metal Oxide Semiconductor，缩写LDMOS)型的半导体芯片，其第一侧21a具有多个用以结合导电凸块22的导电体38。例如，该电子结构21的第一侧21a上具有多个电极垫210，以结合该导电体38。
如图2B所示，提供一设于承载板9上的电子元件29，且该电子元件29上形成有多个导电柱23。
该电子元件29可为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。于本实施例中，该电子元件29为半导体芯片，如互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，缩写作CMOS)型的功能芯片，其具有相对的作用面29a与非作用面29b，且其作用面29a上具有多个电极垫290，并以其非作用面29b设于该承载板9上。
此外，该承载板9例如为半导体材料(如硅或玻璃)的板体，其上可依需求形成有一离形层91(或粘着层90)，以供该电子元件29设于该离形层91上。
另外，该导电柱23设于该电子元件29的其中一部分电极垫290上并电性连接该电极垫290，且形成该导电柱23的材料为如铜的金属材或焊锡材。
如图2C所示，将该电子结构21以其导电凸块22设于该电子元件29的作用面29a上。
于本实施例中，该电子结构21以覆晶方式经由多个导电凸块22结合至该电子元件29的另一部分电极垫290上以电性连接该电极垫290。例如，可依需求以如底胶的结合层24包覆该些导电凸块22与导电体38。
如图2D所示，形成一包覆层25于该承载板9的离形层91上及该电子元件29的作用面29a上，以令该包覆层25包覆该电子结构21、结合层24与该些导电柱23，其中，该包覆层25具有相对的第一表面25a与第二表面25b，且其以第一表面25a结合该承载板9的离形层91。接着，经由整平制程，使该包覆层25的第二表面25b齐平该导电柱23的端面23b与该电子结构21的第二侧21b，令该导电柱23的端面23b与该电子结构21的第二侧21b外露出该包覆层25的第二表面25b。
于本实施例中，该包覆层25为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、环氧树脂(epoxy)或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该承载板9上。
此外，该整平制程经由研磨方式，移除该导电柱23的部分材料、该电子结构21的第二侧21b的部分材料与该包覆层25的部分材料。
另外，若未形成该结合层24，该包覆层25可包覆该些导电凸块22与导电体38。
如图2E所示，形成一线路结构26于该包覆层25的第二表面25b上，且令该线路结构26电性连接该些导电柱23，并使该线路结构26接触该电子结构21的第二侧21b。
于本实施例中，该线路结构26为单一金属层形式。例如，形成该金属层的材料为铜，且其接触该电子结构21以供散热用。
此外，可于该线路结构26上形成多个如焊球的导电元件27。
如图2F所示，移除该承载板9及其上的离形层91与粘着层90，以外露该电子元件29的非作用面29b与该包覆层25的第一表面25a，再沿如图2E所示的切割路径S进行切单制程，以获取该电子封装件2。
于本实施例中，该电子封装件2可于后续制程中经由该些导电元件27接置于一如电路板的电子装置(图未示)上。
此外，该电子封装件2可依需求于该包覆层25的第一表面25a上配置一散热结构28，如散热架、散热鳍片、散热胶或其它适当散热材，其接触该电子元件29的非作用面29b。
因此，本发明的制法将CMOS(如电子元件29)及LDMOS(如电子结构21)整合成一芯片模块2a，如图2C所示，以节省终端产品的电路板或载板上的置放空间或置放面积，故相比于现有技术，本发明的电子封装件2有利于终端产品的电路板或载板的元件配置，使终端产品的电路板或载板于其它布设区域上可依需求增设其它功能的电子组件。
此外，将CMOS(如电子元件29)及LDMOS(如电子结构21)整合成一芯片模块2a，可缩短两者之间的电性传输路径，以加速两者间的电讯传递时间，故相比于现有技术，本发明的电子封装件2更能符合终端产品的电性效能需求。
图3A至图3F为本发明的电子封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于封装的实施例，其它制程大致相同，故以下不再赘述相同处。
如图3A所示，首先采用如图2A至图2B所示的制程。
如图3B所示，于该承载板9的离形层91上形成一封装层35，以覆盖该电子元件29的周围。
于本实施例中，该封装层35为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、环氧树脂(epoxy)或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该承载板9上。
如图3C所示，将该电子结构21以其导电凸块22设于该电子元件29的作用面29a上。
如图3D所示，形成一包覆层25于该封装层35上及该电子元件29的作用面29a上，以令该包覆层25包覆该电子结构21、结合层24与该些导电柱23，其中，该包覆层25以其第一表面25a结合该封装层35。接着，进行整平制程。
于本实施例中，该包覆层25与该封装层35的材料可依需求相同或相异。
如图3E所示，形成一线路结构26于该包覆层25的第二表面25b上，并于该线路结构26上形成多个如焊球的导电元件27。
如图3F所示，移除该承载板9及其上的离形层91与粘着层90，以外露该电子元件29的非作用面29b与该封装层35，再沿如图3E所示的切割路径S进行切单制程，以获取该电子封装件3，且可依需求于该封装层35上配置一散热结构28，如散热片，其接触该电子元件29的非作用面29b。
本发明还提供一种电子封装件2,3，包括：一电子结构21、一电子元件29、多个导电柱23以及一包覆层25。
所述的电子结构21设于该电子元件29上且电性连接该电子元件29，以令该电子元件29与该电子结构21作为芯片模块2a。
所述的导电柱23设于该电子元件29上且电性连接该电子元件29。
所述的包覆层25形成于该电子元件29上，以包覆该电子结构21与导电柱23。
于一实施例中，该电子结构21经由多个导电凸块22电性连接该电子元件29。例如，该电子结构21经由导电体38结合该导电凸块22。
于一实施例中，该包覆层25的第二表面25b齐平该导电柱23的端面23b。
于一实施例中，该导电柱23的端面23b外露出该包覆层25的第二表面25b。
于一实施例中，所述的电子封装件2,3还包括形成于该包覆层25上的多个导电元件27，以令该多个导电元件27电性连接该导电柱23。
于一实施例中，所述的电子封装件2,3还包括形成于该包覆层25上的线路结构26，以令该线路结构26电性连接该导电柱23。进一步，所述的电子封装件2,3还包括形成于该线路结构26上的多个导电元件27，以令该多个导电元件27电性连接该线路结构26。例如，该线路结构26为单一金属层形式。或者，该线路结构26接触该电子结构21。
于一实施例中，所述的电子封装件3还包括覆盖该电子元件29周围的封装层35，以令该包覆层25形成于该封装层35上。
综上所述，本发明的电子封装件及其制法，经由将该电子结构堆叠于该电子元件上以近距离配合该电子元件，故本发明无需重新设计电路板，因而能大幅节省制作成本，且无需扩增电路板的尺寸，以利于满足微小化的需求，并有利于呈现高电性效能。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (22)

1.一种电子封装件，其特征在于，包括：
电子元件；
电子结构，其设于该电子元件上且电性连接该电子元件，以令该电子元件与该电子结构作为芯片模块；
至少一导电柱，其设于该电子元件上且电性连接该电子元件；以及
包覆层，其形成于该电子元件上，以包覆该电子结构与该导电柱。
2.如权利要求1所述的电子封装件，其特征在于，该电子结构经由多个导电凸块电性连接该电子元件。
3.如权利要求2所述的电子封装件，其特征在于，该电子结构经由导电体结合该导电凸块。
4.如权利要求1所述的电子封装件，其特征在于，该包覆层的表面齐平该导电柱的端面。
5.如权利要求1所述的电子封装件，其特征在于，该导电柱的端面外露出该包覆层的表面。
6.如权利要求1所述的电子封装件，其特征在于，该电子封装件还包括至少一形成于该包覆层上的导电元件，且令该导电元件电性连接该导电柱。
7.如权利要求1所述的电子封装件，其特征在于，该电子封装件还包括形成于该包覆层上的线路结构，且令该线路结构电性连接该导电柱。
8.如权利要求7所述的电子封装件，其特征在于，该电子封装件还包括至少一形成于该线路结构上的导电元件，且令该导电元件电性连接该线路结构。
9.如权利要求7所述的电子封装件，其特征在于，该线路结构为单一金属层形式。
10.如权利要求7所述的电子封装件，其特征在于，该线路结构接触该电子结构。
11.如权利要求1所述的电子封装件，其特征在于，该电子封装件还包括覆盖该电子元件周围的封装层，以令该包覆层形成于该封装层上。
12.一种电子封装件的制法，其特征在于，包括：
将至少一电子结构与至少一导电柱设于一电子元件上，且使该电子元件电性连接该电子结构与该导电柱，以令该电子元件与该电子结构作为芯片模块；以及
形成一包覆层于该电子元件上，以包覆该电子结构与该导电柱。
13.如权利要求12所述的电子封装件的制法，其特征在于，该电子结构经由多个导电凸块电性连接该电子元件。
14.如权利要求13所述的电子封装件的制法，其特征在于，该电子结构经由导电体结合该导电凸块。
15.如权利要求12所述的电子封装件的制法，其特征在于，该包覆层的表面齐平该导电柱的端面。
16.如权利要求12所述的电子封装件的制法，其特征在于，该导电柱的端面外露出该包覆层的表面。
17.如权利要求12所述的电子封装件的制法，其特征在于，该制法还包括形成至少一导电元件于该包覆层上，且令该导电元件电性连接该导电柱。
18.如权利要求12所述的电子封装件的制法，其特征在于，该制法还包括形成线路结构于该包覆层上，且令该线路结构电性连接该导电柱。
19.如权利要求18所述的电子封装件的制法，其特征在于，该制法还包括形成至少一导电元件于该线路结构上，且令该导电元件电性连接该线路结构。
20.如权利要求18所述的电子封装件的制法，其特征在于，该线路结构为单一金属层形式。
21.如权利要求18所述的电子封装件的制法，其特征在于，该线路结构接触该电子结构。
22.如权利要求12所述的电子封装件的制法，其特征在于，该制法还包括先以封装层覆盖该电子元件周围，再将该包覆层形成于该封装层上，使该包覆层包覆该电子结构与该导电柱。
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