CN115312490A - 电子模块及其制法与电子封装件 - Google Patents
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Abstract
一种电子模块及其制法与电子封装件,包括于电子元件的侧面与非作用面上依序形成第一金属层、一绝缘层、及第二金属层,供作为电容结构,其中,该电容结构外露出该电子元件的作用面,以经由将该电容结构直接形成于该电子元件上,使该电容结构与该电子元件之间的距离最小化,因而能达到抑制阻抗的最佳效果。
Description
技术领域
本发明有关一种半导体芯片,尤指一种具电容结构的电子模块及其制法与电子封装件。
背景技术
随着现今高速运算应用的终端产品(如自动驾驶、超级电脑或行动装置等产品)蓬勃发展,该些产品的内部电子元件也碰到技术上的瓶颈与挑战。例如,半导体芯片接置于基板上,当该基板的金属走线(trace)的回路电流连接到该半导体芯片时,会产生高频电源阻抗,因而会产生噪声,故该半导体芯片容易在临界位置上因干扰而产生错误的信号,进而产生错误的动作。
因此,业界遂于该基板的周围的不同位置上设置去耦电容(DecouplingCapacitor,简称Decap),以抑制高频电源阻抗的发生。
图1A现有电子装置1的剖面示意图。如图1A所示,该电子装置1包含一半导体封装件1a,其于一封装基板11与半导体芯片10之间设置一硅中介板(Through Siliconinterposer,简称TSI)13,该硅中介板13具有导电硅穿孔(Through-silicon via,简称TSV)130及形成于该导电硅穿孔130上的线路重布结构(Redistribution layer,简称RDL)131,令该硅中介板13以其中介侧13b的导电硅穿孔130经由多个导电元件16电性结合具较大间距的封装基板11的焊垫110,并以底胶15包覆该些导电元件16,而具较小间距的半导体芯片10的电极垫100经由多个焊锡凸块101电性结合该硅中介板13的置晶侧13a的线路重布结构131,再以底胶14包覆该些焊锡凸块101。最后,形成一封装胶体12于该封装基板11上,以令该封装胶体12包覆该半导体芯片10与该硅中介板13。
该电子装置1还包含一电路板1b,以于该半导体封装件1a的封装基板11下侧形成多个焊球17,以结合该电路板1b。
于现有电子装置1中,若将未配置去耦电容结构的情况所产生的阻抗值定义为1x,则当将至少一去耦电容元件18a放置于该电子装置1中的不同位置上时,越靠近该半导体芯片10,所产生的阻抗抑制的效果越好,如下表一所示:
表一。
因此,基于上述原理,业界遂将去耦电容(Decap)结构一体制作于该硅中介板13内。如图1B所示,该硅中介板13于制作导电硅穿孔130时,一并制作多个间隔排列且未贯穿该硅中介板13的导电开孔132,以令该些导电开孔132作为去耦电容18b,使该去耦电容18b经由该线路重布结构131电性导通该半导体芯片10,故该去耦电容18b可非常靠近该半导体芯片10,以达到抑制阻抗的效果(阻抗值如表一所示的0.058x)。
然而,于该硅中介板13中,该些导电开孔132需配合该导电硅穿孔130制作,因而需于孔洞中进行填充介电材、电镀金属材等制程,故会产生制程时间冗长、制作成本提高、制作难度大增、制作良率降低等问题,因而完全不符合降低该电子装置1的成本的需求。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷,本发明提供一种电子模块及其制法与电子封装件,能达到抑制阻抗的最佳效果。
本发明的电子模块,其包括:电子元件,其具有相对的作用面与非作用面及邻接该作用面与非作用面的侧面,且该作用面具有多个电极垫;以及电容结构,其形成于该电子元件上且外露出该作用面,其中,该电容结构包含有一设于该电子元件上且电性连接该多个电极垫的第一金属层、一设于该第一金属层上的绝缘层、及设于该绝缘层上并电性耦合该第一金属层的第二金属层,且该第一金属层未接触该第二金属层。
本发明还提供一种电子模块的制法,包括:于一承载件上设置电子元件,其中,该电子元件具有相对的作用面与非作用面及邻接该作用面与非作用面的侧面,且该作用面具有多个电极垫,以令该电子元件以该作用面结合至该承载件上;于该电子元件上依序形成第一金属层、绝缘层及第二金属层,且该第一金属层未接触该第二金属层,以令该第一金属层、绝缘层及第二金属层作为电容结构;以及移除该承载件。
前述的电子模块及其制法中,该电容结构形成于该电子元件的非作用面及/或该侧面上。
前述的电子模块及其制法中,该电容结构为去耦电容型式。
前述的电子模块及其制法中,该电子元件的内部配置有至少一电性连接该电极垫的导线,以令该第一金属层电性连接该导线。例如,该导线外露于该电子元件的侧面及/或该非作用面。
前述的电子模块及其制法中,该电子元件具有单一组电源传输结构,使该电容结构电性连接该电源传输结构。
前述的电子模块及其制法中,该电子元件具有多组电源传输结构,使该电容结构电性连接该多组电源传输结构。例如,该第一金属层包含相互间隔(分开而不相连)的多个电性连接部,以令该多个电性连接部分别电性连接不同组的该电源传输结构。进一步,该非作用面于各该电性连接部之间形成有分隔区域,以令该第一金属层未遮盖该分隔区域,使该绝缘层形成于该分隔区域上而接触该非作用面。
本发明另提供一种电子封装件,包括:承载结构,其具有线路层;以及前述的电子模块,其设于该承载结构上,且该电容结构电性连接该线路层。
前述的电子封装件中,还包括电性连接该电子元件的布线结构。例如,该布线结构具有相对的第一表面与第二表面,以令该电子模块配置于该第一表面上,且于该第二表面上配置至少一第二电子元件。或者,该承载结构的线路层与该布线结构之间经由多个导电柱相互电性连接。
前述的电子封装件中,该承载结构上形成有多个电性连接该线路层的导电柱。例如,还包括包覆该多个导电柱、电子元件与该电容结构的包覆层。
前述的电子封装件中,还包括包覆该电子元件与该电容结构的包覆层。
由上可知,本发明的电子模块及其制法与电子封装件中,主要经由将该电容结构直接形成于该电子元件上,以令该电容结构邻接该电子元件,故相比于现有技术,本发明的电子模块不仅能使去耦电容(即该电容结构)与半导体芯片(即该电子元件)之间的距离最小化,因而能达到抑制阻抗的最佳效果,且能符合降低制作成本的需求。
附图说明
图1A为现有电子装置的剖面示意图。
图1B为图1A的硅中介板的另一态样的剖面示意图。
图2A至图2E为本发明的电子封装件的制法的剖视示意图。
图3A至图3F为本发明的电子模块的制法的剖视示意图。
图3E-1至图3F-1为图3E至图3F的另一方式的剖视示意图。
图3E-2为图3E-1的局部上视示意图。
附图标记说明
1:电子装置
1b,2b:电路板
1a:半导体封装件
10:半导体芯片
100,210,300,300b,300c:电极垫
101:焊锡凸块
11:封装基板
110:焊垫
12:封装胶体
13:硅中介板
13a:置晶侧
13b:中介侧
130:导电硅穿孔
131:线路重布结构
132:导电开孔
14,15:底胶
16,29:导电元件
17:焊球
18a:去耦电容元件
18b:去耦电容
2:电子封装件
20:承载结构
20a:第一侧
20b:第二侧
200:第一介电层
201:第一线路层
21:第一电子元件
21a,30a:作用面
21b,30b:非作用面
21c,30c:侧面
210a,300a:接点
211,301,301b,301c:导线
212:导电体
22,32:电容结构
220,32b:绝缘层
221,32a:第一金属层
222,32c:第二金属层
23:导电柱
24:第二电子元件
25:包覆层
26:布线结构
26a:第一表面
26b:第二表面
260:第二介电层
261:第二线路层
27:导电凸块
28:封装层
3,3a:电子模块
30,31:电子元件
321,322:电性连接部
4:晶圆
8,9:承载件
90:板体
91:结合层
A:分隔区域
L,S:切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书附图所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2E为本发明的具有电容结构22的电子封装件2的制法的剖面示意图。
如图2A所示,将一承载结构20设于一承载件9上,且该承载结构20具有相对的第一侧20a与第二侧20b,且该承载结构20的第一侧20a上设置有至少一第一电子元件21及多个导电柱23(如以铜的金属材或焊锡材制作)。
于本实施例中,该承载结构20例如为具有核心层与线路结构的封装基板、无核心层(coreless)形式线路结构的封装基板、具导电硅穿孔(Through-silicon via,简称TSV)的硅中介板(Through Silicon interposer,简称TSI)或其它板型,其包含至少一第一介电层200及至少一结合该第一介电层200的第一线路层201,如至少一扇出(fan out)型重布线路层(redistribution layer,简称RDL)。例如,形成该第一线路层201的材料为铜,且形成该第一介电层200的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)的介电材。应可理解地,该承载结构20也可为其它承载芯片的基材,如导线架(lead frame)、晶圆(wafer)、或其它具有金属布线(routing)的板体等,并不限于上述。
此外,该承载结构20的第二侧20a经由多个导电元件29设于该承载件9上。例如,该承载件9包含如半导体材、介电材、陶瓷材、玻璃或金属材的板体90,但不限于此,且该承载件9的尺寸可依需求选择晶圆型基板(Wafer form substrate)或一般整版面型基板(Panelform substrate),并可经由如离型膜或胶材的结合层91,其以涂布或贴合方式形成于该板体90上,使该承载结构20压合于该结合层91上,且令该些导电元件29嵌埋于该结合层91中。
另外,该第一电子元件21为主动元件、被动元件或其组合者,其中,该主动元件例如为半导体芯片,而该被动元件例如为电阻、电容及电感。于本实施例中,于本实施例中,该第一电子元件21为半导体芯片,其具有相对的作用面21a与非作用面21b及邻接该作用面21a与非作用面21b的侧面21c,该第一电子元件21以其非作用面21b设于该承载结构20的第一侧20a上,而该作用面21a具有多个电极垫210(其可位于如图2A所示的作用面21a的中间处)及多个接点210a(其可位于如图2A所示的作用面21a的外围处),其中,该第一电子元件21的内部配置有至少一电性连接该电极垫210的导线211及多个电性连接该接点210a的集成电路(图未示),且该导线211外露于该第一电子元件21的侧面21c。例如,于该电极垫210及该接点210a上可依需求形成有如柱状、针状或其它凸块状的导电体212,并于该作用面21a上形成有一绝缘保护膜(图略),以令该导电体212外露于该绝缘保护膜。
另外,该第一电子元件21的非作用面21b与侧面21c上形成有一电性连接该第一电子元件21的电容结构22,如去耦电容(Decap),其包含一设于该第一电子元件21(非作用面与侧面)上且电性连接该导线211的第一金属层221、一设于该第一金属层221上的绝缘层220、及设于该绝缘层220上并电性耦合该第一金属层221的第二金属层222,以令该第一电子元件21经由该电容结构22设于该承载结构20的第一侧20a上,且该第二金属层222电性连接该第一线路层201以作为该电容结构22的接地端。例如,形成该第一金属层221与第二金属层222的材料为铜,且形成该绝缘层220的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)等的介电材。
如图2B所示,形成一包覆层25于该承载结构20的第一侧20a上,以令该包覆层25包覆该第一电子元件21、电容结构22与该些导电柱23。接着,形成一布线结构26于该包覆层25上,以令该布线结构26电性连接该些导电柱23与该第一电子元件21。
于本实施例中,形成该包覆层25的材料为聚酰亚胺(polyimide,简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound)等绝缘材,但并不限于上述。例如,可采用压合(lamination)或模压(molding)等方式将该包覆层25形成于该承载结构20的第一侧20a上。
此外,可依需求进行整平制程,以令该包覆层25的上表面齐平该导电柱23的端面与该导电体212的顶面,使该导电柱23的端面与该导电体212的顶面外露出该包覆层25。例如,可经由研磨方式进行该整平制程,以移除该导电柱23的部分材料、该导电体212的部分材料与该包覆层25的部分材料。
另外,该布线结构26具有相对的第一表面26a与第二表面26b,以令该布线结构26以其第一表面26a结合该包覆层25,使该第一电子元件21与该导电柱23配置于该第一表面26a上。
另外,该布线结构26具有至少一第二介电层260及设于该第二介电层260上的第二线路层261(如RDL),以令该布线结构26的第二线路层261电性连接该些导电柱23与该第一电子元件21上的导电体212。例如,形成该第二线路层261的材料为铜,且形成该第二介电层260的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)的介电材。
如图2C所示,设置至少一第二电子元件24于该布线结构26的第二表面26b上,再以一封装层28包覆该第二电子元件24。
于本实施例中,该第二电子元件24为主动元件、被动元件或其二者组合,且该主动元件例如为半导体芯片,而该被动元件例如为电阻、电容及电感。例如,该第二电子元件24以覆晶方式经由多个如焊锡凸块、铜凸块或其它等的导电凸块27电性连接该布线结构26的第二线路层261;然而,有关该第二电子元件24连接该布线结构26的方式繁多,如打线封装方式,并不限于上述。
此外,该封装层28可同时包覆该第二电子元件24与该些导电凸块27。或者,也可先形成底胶(图略)于该第二电子元件24与该布线结构26的第二表面26b之间以包覆该些导电凸块27,再形成该封装层28以包覆该底胶与该第二电子元件24。
另外,该封装层28为绝缘材,如聚酰亚胺(polyimide,简称PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound),其可用压合(lamination)或模压(molding)的方式形成于该布线结构26上。应可理解地,形成该封装层28的材料可相同或不相同该包覆层25的材料。
另外,该封装层28可依需求包覆该第二电子元件24的背面(图未示)或外露该第二电子元件24的背面(如图2C所示)。
如图2D所示,移除该承载件9及其上的结合层91,以外露出该多个导电元件29。
如图2E所示,沿如图2D所示的切割路径S进行切单制程,以获取多个电子封装件2,使该电子封装件2可经由该些导电元件29接置于一电路板2b上。
因此,本发明的电子封装件2主要采用金属-绝缘层-金属二极体(Metal-insulator-metal diode,简称MIM diode)技术,将该电容结构22形成于该第一电子元件21上,以令该电容结构22邻接该第一电子元件21,使去耦电容(Decap)最靠近半导体芯片,故相比于现有技术,依据前述表一的原理,本发明的电子封装件2将该电容结构22与该第一电子元件21嵌埋于该包覆层25中的同一处,使两者之间的距离最小化,因而能达到抑制阻抗的最佳效果(阻抗值小于0.058x,约0.01x~0.04x),进一步能消弭阻抗所产生的噪声。
图3A至图3F为本发明的具有电容结构22的第一电子元件21的相关电子模块3的制法的剖面示意图。
如图3A至图3B所示,将一晶圆4进行切单制程,以获取多个电子元件30。接着,将多个电子元件30间隔排设于一整版面承载件8上。
于本实施例中,该电子元件30如第一电子元件21的构造,其具有相对的作用面30a与非作用面30b,该作用面30a具有多个电极垫300及多个接点300a,且该电子元件30的内部配置有多个电性连接该电极垫300的导线301,并以该作用面30a结合至该承载件8上。应可理解地,可于该电极垫300与该接点300a上依需求形成如图2A所示的导电体212,并以绝缘保护膜(图略)包覆该导电体212,以令该电子元件30以该绝缘保护膜结合于该承载件8上。
此外,于切单该晶圆4后,该导线301将外露于该电子元件30的侧面30c。应可理解地,该导线301也可外露于该电子元件30的非作用面30b。
如图3C至图3E所示,于该电子元件30的非作用面30b与侧面30c上依序形成第一金属层32a、绝缘层32b及第二金属层32c,且该第一金属层32a未接触该第二金属层32c,以令该第一金属层32a、绝缘层32b及第二金属层32c作为电容结构32,如去耦电容(Decap),使该电容结构32包覆该电子元件30。
于本实施例中,该第一金属层32a采用电镀、沉积或其它方式涂布于该电子元件30的全部或部分的非作用面30b及/或全部或部分的侧面30c上,且该绝缘层32b涂布于该第一金属层32a的全部表面上,而该第二金属层32c采用电镀、沉积或其它方式涂布于该第一金属层32a的全部表面上。
此外,该第一金属层32a接触该导线301,以经由该导线301电性连接该电极垫300,且该第一金属层32a未电性连接该些接点300a。例如,该电容结构32对应该电子元件30的单一组电源传输结构(即该些电极垫300),因而该第一金属层32a仅为单一电性连接部,且该第二金属层32c作为该电容结构32的接地埠。
或者,如图3E-1所示,该电容结构32也可对应该电子元件31的多组电源传输结构。例如,该电子元件31具有两组电源传输结构,且该第一金属层32a包含多个相互分开而不相连的电性连接部321,322,如图3E-2所示,以令该多个电性连接部321,322分别电性连接不同组的电源传输结构(即不同的导线301b,301c或不同的电极垫300b,300c),而该第二金属层32c作为该电容结构32的接地埠。具体地,该非作用面30b于该电性连接部321,322之间形成有分隔区域A,以令该第一金属层32a未遮盖该分隔区域A,使该绝缘层32b形成于该分隔区域A上而接触该非作用面30b。
如图3F所示,接续图3E的制程,以沿如图3E所示的切割路径L进行切单制程,再移除该承载件8,从而获取多个电子模块3,且该电容结构32未形成于该电子元件30,31的作用面30a上。
于本实施例中,将该电子模块3应用于图2E所示的电子封装件2中,该电子元件30仅具有一组电源传输结构(即该些电极垫300),故该电子元件30能提供一个第二电子元件24所需的电源,而其它第二电子元件24需连接其它电源。
此外,若接续图3E-1的制程,可获取如图3F-1所示的电子模块3a,且将该电子模块3a应用于图2E所示的电子封装件2中,该电子元件31具有两组电源传输结构(即该些电极垫300b,300c),故该电子元件30能提供两个第二电子元件24所需的电源。
应可理解地,基于该电子元件30,31的电源传输结构的组数,该第一金属层32a的电性连接部321,322的数量可依需求设计,并不限于上述。
因此,本发明的电子模块3,3a主要采用金属-绝缘层-金属二极体(Metal-insulator-metal diode,简称MIM diode)技术,将该电容结构32形成于该电子元件30,31上,以简化制程,故相比于现有技术的硅板钻孔作业,本发明的电子模块3,3a的制作简单、制程时间短、生产良率高及制作成本低,因而能符合降低该电子封装件2及其后续产品应用的成本的需求。
本发明提供一种电子模块3,3a,包括:一电子元件30,31以及一电容结构32。
所述的电子元件30,31具有相对的作用面30a与非作用面30b及邻接该作用面30a与非作用面30b的侧面30c,且该作用面30a具有多个电极垫300,300b,300c。
所述的电容结构32形成于该电子元件30,31上且外露出该作用面30a,其中,该电容结构32包含有一设于该电子元件30,31上且电性连接该多个电极垫300,300b,300c的第一金属层32a、一设于该第一金属层32a上的绝缘层32b、及设于该绝缘层32b上并电性耦合该第一金属层32a的第二金属层32c,且该第一金属层32a未接触该第二金属层32c。
于一实施例中,该电容结构32形成于该电子元件30,31的非作用面30a及/或该侧面30c上。
于一实施例中,该电容结构32为去耦电容型式。
于一实施例中,该电子元件30,31的内部配置有至少一电性连接该电极垫300,300b,300c的导线301,301b,301c,以令该第一金属层32a电性连接该导线301,301b,301c。例如,该导线301,301b,301c外露于该电子元件30,31的侧面30c及/或该非作用面30b。
于一实施例中,该电子元件30具有单一组电源传输结构(即相连的电极垫300与导线301),使该电容结构32电性连接该电源传输结构。
于一实施例中,该电子元件31具有多组电源传输结构(即相连的电极垫300b与导线301b,以及相连的电极垫300c与导线301c),使该电容结构32电性连接该多组电源传输结构。例如,该第一金属层32a包含多个相互分开而不相连的电性连接部321,322,以令该多个电性连接部321,322分别电性连接不同组的该电源传输结构。进一步,该非作用面30b于各该电性连接部321,322之间形成有分隔区域A,以令该第一金属层32a未遮盖该分隔区域A,使该绝缘层32b形成于该分隔区域A上而接触该非作用面30b。
于一实施例中,该电子模块3,3a可应用于一电子封装件2中,该电子封装件2将该电子模块3,3a设于一具有第一线路层201的承载结构20上,且该电子模块3,3a包含有该电子元件30,31(或第一电子元件21)及该电容结构22,32,且该电容结构22,32电性连接该第一线路层201。
所述的电子模块3,3a的电子元件30,31(或第一电子元件21)的电极垫300,210电性连接一布线结构26。
于一实施例中,该布线结构26具有相对的第一表面26a与第二表面26b,以令该电子模块3,3a配置于该第一表面26a上,且于该第二表面26b上配置至少一第二电子元件24。或者,该承载结构20的第一线路层201与该布线结构26之间经由多个导电柱23相互电性连接。
于一实施例中,该承载结构20上形成有多个电性连接该第一线路层201的导电柱23。
于一实施例中,所述的电子封装件2还包括一包覆该多个导电柱23、该电子元件30,31(或第一电子元件21)与该电容结构22,32的包覆层25。
综上所述,本发明的电子模块及其制法与电子封装件,主要经由于该电子元件上直接形成多层复合式电容结构,以令该电容结构邻接该电子元件,故本发明的电子模块不仅能使去耦电容与半导体芯片之间的距离最小化,因而能达到抑制阻抗的最佳效果,且能符合降低制作成本的需求。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (26)
1.一种电子模块,其特征在于,包括:
电子元件,其具有相对的作用面与非作用面及邻接该作用面与非作用面的侧面,且该作用面具有多个电极垫;以及
电容结构,其形成于该电子元件上且外露出该作用面,其中,该电容结构包含有一设于该电子元件上且电性连接该多个电极垫的第一金属层、一设于该第一金属层上的绝缘层、及设于该绝缘层上并电性耦合该第一金属层的第二金属层,且该第一金属层未接触该第二金属层。
2.如权利要求1所述的电子模块,其特征在于,该电容结构形成于该电子元件的非作用面及/或该侧面上。
3.如权利要求1所述的电子模块,其特征在于,该电容结构为去耦电容型式。
4.如权利要求1所述的电子模块,其特征在于,该电子元件的内部配置有至少一电性连接该电极垫的导线,以令该第一金属层电性连接该导线。
5.如权利要求4所述的电子模块,其特征在于,该导线外露于该电子元件的侧面及/或该非作用面。
6.如权利要求1所述的电子模块,其特征在于,该电子元件具有单一组电源传输结构,使该电容结构电性连接该电源传输结构。
7.如权利要求1所述的电子模块,其特征在于,该电子元件具有多组电源传输结构,使该电容结构电性连接该多组电源传输结构。
8.如权利要求7所述的电子模块,其特征在于,该第一金属层包含相互间隔的多个电性连接部,以令该多个电性连接部分别电性连接不同组的该电源传输结构。
9.如权利要求8所述的电子模块,其特征在于,该非作用面于各该电性连接部之间形成有分隔区域,以令该第一金属层未遮盖该分隔区域,使该绝缘层形成于该分隔区域上而接触该非作用面。
10.一种电子封装件,其特征在于,包括:
承载结构,其具有线路层;以及
如权利要求1至9中任一项所述的电子模块,其设于该承载结构上,且该电容结构电性连接该线路层。
11.如权利要求10所述的电子封装件,其特征在于,该电子封装件还包括电性连接该电子元件的布线结构。
12.如权利要求11所述的电子封装件,其特征在于,该布线结构具有相对的第一表面与第二表面,以令该电子模块配置于该第一表面上,且于该第二表面上配置至少一第二电子元件。
13.如权利要求11所述的电子封装件,其特征在于,该承载结构的线路层与该布线结构之间经由多个导电柱相互电性连接。
14.如权利要求10所述的电子封装件,其特征在于,该承载结构上形成有多个电性连接该线路层的导电柱。
15.如权利要求14所述的电子封装件,其特征在于,该电子封装件还包括包覆该多个导电柱、电子元件与该电容结构的包覆层。
16.如权利要求10所述的电子封装件,其特征在于,该电子封装件还包括包覆该电子元件与该电容结构的包覆层。
17.一种电子模块的制法,其特征在于,包括:
于一承载件上设置电子元件,其中,该电子元件具有相对的作用面与非作用面及邻接该作用面与非作用面的侧面,且该作用面具有多个电极垫,以令该电子元件以该作用面结合至该承载件上;
于该电子元件上依序形成第一金属层、绝缘层及第二金属层,且该第一金属层未接触该第二金属层,以令该第一金属层、绝缘层及第二金属层作为电容结构;以及
移除该承载件。
18.如权利要求17所述的电子模块的制法,其特征在于,该电容结构形成于该电子元件的非作用面及/或该侧面上。
19.如权利要求17所述的电子模块的制法,其特征在于,该电容结构未形成于该电子元件的作用面上。
20.如权利要求17所述的电子模块的制法,其特征在于,该电子元件的内部配置有至少一电性连接该电极垫的导线,以令该导线外露于该电子元件的侧面及/或该非作用面。
21.如权利要求17所述的电子模块的制法,其特征在于,该电容结构为去耦电容型式。
22.如权利要求17所述的电子模块的制法,其特征在于,该电子元件的内部配置有至少一电性连接该电极垫的导线,以令该第一金属层电性连接该导线。
23.如权利要求17所述的电子模块的制法,其特征在于,该电子元件具有单一组电源传输结构,使该电容结构电性连接该电源传输结构。
24.如权利要求17所述的电子模块的制法,其特征在于,该电子元件具有多组电源传输结构,使该电容结构电性连接该多组电源传输结构。
25.如权利要求24所述的电子模块的制法,其特征在于,该第一金属层包含相互间隔的多个电性连接部,以令该多个电性连接部分别电性连接不同组的该电源传输结构。
26.如权利要求25所述的电子模块的制法,其特征在于,该非作用面于各该电性连接部之间形成有分隔区域,以令该第一金属层未遮盖该分隔区域,使该绝缘层形成于该分隔区域上而接触该非作用面。
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