CN115295425A - 半导体器件和在sip模块的包封物内形成电路图案的方法 - Google Patents

半导体器件和在sip模块的包封物内形成电路图案的方法 Download PDF

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CN115295425A
CN115295425A CN202210325234.8A CN202210325234A CN115295425A CN 115295425 A CN115295425 A CN 115295425A CN 202210325234 A CN202210325234 A CN 202210325234A CN 115295425 A CN115295425 A CN 115295425A
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circuit pattern
encapsulant
substrate
electrical component
semiconductor device
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J·H·郑
C·O·金
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

公开了半导体器件和在SIP模块的包封物内形成电路图案的方法。一种半导体器件，具有电组件组装，电组件组装具有基板和部署在基板上的多个电组件。导电柱被形成在基板上。模制化合物片材被部署在电组件组装上。包括第一电路图案的载体被部署在模制化合物片材上。抵靠模制化合物片材按压载体以将第一包封物部署在电组件组装之上和周围并且将第一电路图案嵌入在第一包封物中。屏蔽层可以被形成在电组件组装上。移除载体以暴露出第一电路图案。第二包封物被沉积在第一包封物和第一电路图案上。在第二包封物上形成第二电路图案。半导体封装被部署在第一电路图案上。

Description

半导体器件和在SIP模块的包封物内形成电路图案的方法
技术领域
本发明一般涉及半导体器件，并且更具体地涉及半导体器件和在部署于系统级封装(SIP)模块中的电组件上的包封物内形成电路图案的方法。
背景技术
半导体器件通常出现在现代电子产品中。半导体器件执行宽范围的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子设备、进行光电作用以及创建用于电视显示的视觉图像。半导体器件出现在通信、功率转换、网络、计算机、娱乐和消费产品的领域中。半导体器件还出现在军事应用、航空、汽车、工业控制器和办公设备中。
特别地，在高频应用(诸如射频(RF)无线通信)中，半导体器件通常包含一个或多个集成无源器件(IPD)以执行必要的电气功能。多个半导体管芯和IPD可以针对小空间中的更高密度和扩展的电气功能性而被集成到SIP模块中。在SIP模块内，半导体管芯和IPD被安装到基板以用于结构支承和电互连。
针对半导体器件的共同设计目标是减少占位面积和外廓，同时获得功能性。半导体器件需要在更小区域中容纳更高密度的组件。在许多已知的封装布局、中，底部互连基板提供与形成在基板上的电路图案或RDL的机械和电连接，以支持到半导体器件的外部电互连。为了在半导体封装的顶部上进行电互连，典型地将另外的互连基板放置在封装的顶部上。顶部侧互连基板添加了制造成本并且增加SIP模块的总体高度，这与设计目标相反。
附图说明
图1a至图1c图示具有由划片街区(saw street)分离的多个半导体管芯的半导体晶片；
图2a至图2l图示在SIP模块的包封物中形成电路图案的处理；
图3a至图3d图示在具有电磁屏蔽的SIP模块的包封物中形成电路图案的处理；
图4a至图4e图示在SIP模块的包封物中形成多层电路图案的处理；以及
图5图示具有安装到印刷电路板(PCB)的表面的不同类型的封装的PCB。
具体实施方式
在以下的描述中参照各图在一个或多个实施例中描述本发明，各图中同样的标号表示相同或相似的要素。虽然就用于实现本发明的目的的最佳方式描述了本发明，但是本领域技术人员将领会，本发明旨在覆盖可以包括在由所附权利要求限定的本发明的精神和范围内的替换、修改和等同物以及由以下公开和附图支持的它们的等同物。如在此使用的术语“半导体管芯”指代用语的单数形式和复数形式这两者，并且因此可以指代单个半导体器件和多个半导体器件这两者。
半导体器件一般是使用两种复杂的制造处制造的：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含被电连接以形成功能电路的有源电组件和无源电组件。诸如晶体管和二极管的有源电组件具有控制电流流动的能力。诸如电容器、电感器和电阻器的无源电组件创建电压和电流之间的执行电路功能所需要的关系。
后端制造指代将完成的晶片切割或单体化成单独的半导体管芯，并且封装半导体管芯以用于结构支承、电互连和环境隔离。为了单体化半导体管芯，晶片被沿着晶片的被称为划片街区或划痕区的非功能区划刻并且断裂。使用激光切割工具或锯切刃将晶片单体化。在单体化之后，将单独的半导体管芯安装到封装基板，封装基板包括用于与其它系统组件互连的管脚或接触焊盘。然后将形成在半导体管芯上的接触焊盘连接到封装内的接触焊盘。可以利用导电层、凸块、柱形凸块、导电焊膏或布线接合来进行电连接。包封物或其它模制材料被沉积在封装上以提供物理支承和电隔离。然后将完成的封装插入到电系统中，并且使半导体器件的功能性可用于其它系统组件。
图1a示出具有基底基板材料102的半导体晶片100，基底基板材料102诸如为硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或用于结构支承的其它块体材料。多个半导体管芯或组件104被形成在晶片100上，由非有源的、管芯间晶片区域或划片街区106分离开。划片街区106提供切割区域以将半导体晶片100单体化成单独的半导体管芯104。在一个实施例中，半导体晶片100具有100-450毫米(mm)的宽度或直径。
图1b示出半导体晶片100的一部分的横截面视图。每个半导体管芯104具有背侧或非有源表面108和有源表面110，其包含被实现为形成在管芯内并且被根据管芯的电设计和功能电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括一个或多个晶体管、二极管和形成在有源表面110内的其它电路元件，以实现模拟电路或数字电路，诸如数字信号处理器(DSP)、专用集成电路(ASIC)、存储器或其它信号处理电路。半导体管芯104还可以包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。
使用PVD、CVD、电解电镀、无电电镀处理或其它合适的金属沉积处理在有源表面110上形成导电层112。导电层112可以是一层或多层的铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)或其它合适的导电材料。导电层112作为电连接到有源表面110上的电路的接触焊盘进行操作。
使用蒸发、电解电镀、无电电镀、球滴或丝网印刷处理在导电层112上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它们的组合，具有可选的助熔剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或接合处理将凸块材料接合到导电层112。在一个实施例中，通过将凸块材料加热到其熔点以上来使凸块材料回流以形成球或凸块114。在一个实施例中，凸块114被形成在具有润湿层、阻挡层和粘合剂层的凸块下金属化(UBM)上方。凸块114也可以被压缩接合或热压缩接合到导电层112。凸块114表示可以被形成在导电层112上的一种类型的互连结构。互连结构还可以使用接合布线、导电焊膏、柱形凸块、微凸块或其它电互连。
在图1c中，使用锯切刃或激光切割工具118通过划片街区106将半导体晶片100单体化成单独的半导体管芯104。单独的半导体管芯104可以被检查和电测试以用于标识单体化之后的KGD。
图2a至图2l图示在SIP模块的包封物内形成电路图案的处理。图2a示出包括导电层122和绝缘层124的互连基板120的横截面视图。导电层122可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层122提供跨基板120的水平电互连和在基板120的顶部表面126和底部表面128之间的竖向电互连。导电层122的部分可以是电共用的或电隔离的，这取决于半导体管芯104和其它电组件的设计和功能。绝缘层124包含一层或多层的二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、阻焊剂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)和具有类似的绝缘和结构性质的其它材料。绝缘层124提供导电层122之间的隔离。
在图2b中，多个电组件130a-130d被安装到互连基板120的表面126，并且电气地和机械地连接到导电层122。使用拾取和放置操作将每个电组件130a-130d定位在基板120上。例如，电组件130a和130c可以是来自图1c的半导体管芯104，其具有朝向基板120的表面126定向并且电连接到导电层122的有源表面110和凸块114。电组件130b和130d是分立的电子器件或IPD，诸如晶体管、二极管、电阻器、电容器和电感器。电组件130b使用端子132和134来与互连基板120上的导电层122进行电气和机械连接。电组件130d使用端子136和138来与互连基板120上的导电层122进行电气和机械连接。替换地，电组件130a-130d可以包括其它半导体管芯、半导体封装、表面安装器件、分立的电子器件、分立的晶体管、二极管或IPD。如在图2c中示出那样，电组件130a-130d被安装到互连基板120，其中凸块114和端子132-138与导电层122进行机械和电气连接。
导电柱或梁140形成在互连基板120上并且电连接到导电层122。导电柱140可以被用于竖向电互连。替换地，多个导电柱140或导电壁140提供电组件130a-103b和电组件130c-130d之间的电磁屏蔽。图2c示出被安装到互连基板120的电组件130a-130d和导电柱140，其中凸块114和端子132-138与导电层122进行机械和电连接。
在图2e中，环氧树脂模制化合物(EMC)片材150被部署在电组件130a-130d和互连基板120上。载体154的表面152包括电路图案156，其被指定为通过使用迹线、重分布层(RDL)、接触焊盘和其它互连结构来互连各种电组件。图2f示出载体154的表面152上的电路图案156的顶视图。例如，电路图案156a提供迹线线路，电路图案156b提供接触焊盘，并且电路图案156c提供RDL。载体154被部署在EMC片材150上，其中表面152和电路图案156朝向EMC片材的表面158定向。在力F下，载体154将电路图案156按压到EMC片材150的表面158中，并且将EMC片材按压到电组件130a-130d和导电柱140上。在利用力F按压之后，EMC片材150覆盖电组件130a-130d、导电柱140和互连基板120，如图2g中示出那样。电路图案156嵌入在EMC片材150的表面158中。EMC片材150现在被认为是部署在电组件130a-130d、导电柱140和互连基板120上的包封物160。包封物160可以是聚合物复合材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有适当填充物的聚合物。包封物160是不导电的，提供结构支承，并且在环境上保护半导体器件不受外部因素和污染物的影响。电路图案156嵌入在包封物160的表面162内。
在图2h中，通过研磨机166移除载体154，以暴露出表面162和电路图案156，现在电路图案至少部分地嵌入包封物160内。研磨机166使包封物160的表面162和电路图案156的表面168平坦化。替换地，通过化学蚀刻、化学机械抛光(CMP)、机械剥除、机械研磨、热烘、紫外(UV)光、激光扫描或湿法剥离来移除载体154，以暴露出包封物160的表面162和电路图案156的表面168。图2i示出研磨后的SIP模块或半导体组件组装170，其中电路图案156至少部分地嵌入包封物160。导电柱140可以是通过形成穿过包封物的多个通孔并且在通孔中沉积导电材料以形成导电柱而在包封物160之后形成的。
在图2j中，使用蚀刻、钻孔或利用激光器174的LDA将多个通孔172形成到包封物160的表面162中。通孔172与导电柱140对准并且延伸到导电柱。电路图案156可以通过导电柱140进行到互连基板120的电连接。
使用蒸发、电解电镀、无电电镀、球滴或丝网印刷处理在互连基板120的表面128上的导电层122上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和它们的组合，具有可选的助熔剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或接合处理将凸块材料接合到导电层122。在一个实施例中，通过将凸块材料加热到其熔点以上来使凸块材料回流以形成球或凸块176。在一个实施例中，凸块176被形成在具有润湿层、阻挡层和粘合剂层的UBM上方。凸块176也可以被压缩接合或热压缩接合到导电层122。凸块176表示可以被形成在导电层122上的一种类型的互连结构。互连结构还可以使用接合布线、导电焊膏、柱形凸块、微凸块或其它电互连。
图2k示出从包封物160上露出的电路图案156的表面168和导电柱140的顶视图。电路图案156在包封物160的表面162上提供电互连，例如作为RDL。外部端子可以根据系统设计连接到电路图案156。替换地，如图2l所示，附加的半导体管芯或半导体封装可以安装到电路图案156。半导体管芯180通过凸块182与电路图案156机械和电连接。具有互连基板、半导体管芯和包封物的半导体封装186经由凸块188与电路图案156进行机械和电连接。如在此描述的那样，形成在包封物160中的电路图案156减小了封装厚度，并且还减少了制造步骤和相关成本。
在替换的实施例中，从图2g继续，电组件130a-130d可以包含IPD，其易受EMI、RFI、谐波失真和器件间干扰影响或生成EMI、RFI、谐波失真和器件间干扰。例如，包含在电组件130a-130d内的IPD提供高频应用所需要的电气特性，高频应用诸如为谐振器、高通滤波器、低通滤波器、带通滤波器、对称Hi-Q谐振变压器和调谐电容器。替换地，电组件130a-130d包含在高频下开关的数字电路，这可能干扰SIP模块情况下IPD的操作。在图3a中，电磁屏蔽层200形成在载体154的顶部表面202上以及载体和SIP模块的侧表面204上，以减少或抑制EMI、RFI和例如由高速数字器件辐射的其它器件间干扰影响SIP模块内或相邻于SIP模块的邻近器件。
在图3b中，通过研磨机166移除载体154，以暴露出包封物160的表面162和电路图案156的表面168，其现在至少部分地嵌入在包封物160内。具有相似功能的组件被分配有相同的参考标号。研磨机166使包封物160的表面162和电路图案156的表面168平坦化。替换地，通过化学蚀刻、CMP、机械剥除、机械研磨、热烘、UV光、激光扫描或湿法剥离来移除载体154，以暴露出包封物160的表面162和电路图案156的表面168。图3c示出研磨后的SIP模块或半导体组件组装210，其中电路图案156至少部分地嵌入包封物160。
在图3d中，使用蚀刻、钻孔或利用激光器214的LDA将多个通孔212形成到包封物160的表面162中。通孔212与导电柱140对准并且延伸到导电柱140。电路图案156可以通过导电柱140进行到互连基板120的电连接。
使用蒸发、电解电镀、无电电镀、球滴或丝网印刷处理在互连基板120的表面128上的导电层122上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和它们的组合，具有可选的助熔剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或接合处理将凸块材料接合到导电层122。在一个实施例中，通过将凸块材料加热到其熔点以上来使凸块材料回流以形成球或凸块216。在一个实施例中，凸块216被形成在具有润湿层、阻挡层和粘合剂层的UBM上方。凸块216也可以被压缩接合或热压缩接合到导电层122。凸块216表示可以被形成在导电层122上的一种类型的互连结构。互连结构还可以使用接合布线、导电焊膏、柱形凸块、微凸块或其它电互连。
电路图案156在包封物160的表面162上提供电互连，例如作为RDL。如在此描述的那样，形成在包封物160中的电路图案156减小封装厚度，并且还减少制造步骤和相关成本。外部端子可以根据系统设计连接到电路图案156。替换地，类似于图2l，附加的半导体管芯或半导体封装可以被安装到电路图案156。
在另一实施例中，从图2i继续，使用焊膏印刷、压缩模制、转印模制、液体包封物模制、真空层压、旋涂或其它合适的施加器将包封物或模制化合物220沉积在包封物160和电路图案156上，如在图4a中示出那样。包封物220可以是聚合物复合材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有适当填充物的聚合物。包封物220是不导电的，提供结构支承，并且在环境上保护半导体器件不受外部因素和污染物的影响。
在图4b中，使用蚀刻、钻孔或利用激光器230的LDA将多个通孔224形成到包封物220的表面226中。通孔224与电路图案156和导电柱140对准并且延伸到电路图案156和导电柱140。电路图案156可以通过导电柱140进行到互连基板120的电连接。
在图4c中，使用PVD、CVD、电解电镀、无电电镀处理或其它合适的金属沉积处理，在包封物220的表面226上图案化并且形成导电层234，并且将其图案化并且形成到通孔224中。导电层234可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。SIP模块或半导体组件组装236示出嵌入在包封物160和包封物220之间的第一层级电路图案156。导电层234作为第二层级电路图案238操作以提供用于SIP模块236的附加电互连。
使用蒸发、电解电镀、无电电镀、球滴或丝网印刷处理在互连基板120的表面128上的导电层122上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料和它们的组合，具有可选的助熔剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附接或接合处理将凸块材料接合到导电层122。在一个实施例中，通过将凸块材料加热到其熔点以上来使凸块材料回流以形成球或凸块240。在一个实施例中，凸块240被形成在具有润湿层、阻挡层和粘合剂层的UBM上方。凸块240也可以被压缩接合或热压缩接合到导电层122。凸块240表示可以被形成在导电层122上的一种类型的互连结构。互连结构还可以使用接合布线、导电焊膏、柱形凸块、微凸块或其它电互连。
电路图案156和238在包封物160的表面162和包封物220的表面226上提供多个层级的电互连，例如作为多层级RDL。外部端子可以根据系统设计连接到电路图案156。替换地，如在图4d中示出那样，附加的半导体管芯或半导体封装可以被安装到电路图案156。半导体管芯244经由凸块246进行到电路图案238的机械和电连接。具有互连基板、半导体管芯和包封物的半导体封装248经由凸块250进行到电路图案238的机械和电连接。图4e示出安装到SIP模块236的半导体管芯244和半导体封装248，具有到电路图案238的机械和电连接。如在此描述的那样，形成在包封物160和220中的电路图案156和238减小封装厚度，并且还减少制造步骤和相关成本。
图5图示具有芯片载体基板或PCB 302的电子设备300，其中多个半导体封装被安装在PCB 302的表面上，包括SIP模块170、210和236。取决于应用，电子设备300可以具有一种类型的半导体封装或者多种类型的半导体封装。
电子设备300可以是使用半导体封装来执行一个或多个电气功能的单独的系统。替换地，电子设备300可以是更大系统的子组件。例如，电子设备300可以是平板电脑、蜂窝电话、数码相机、通信系统或其它电子设备的一部分。替换地，电子设备300可以是图形卡、网络接口卡或可以被插入到计算机中的其它信号处理卡。半导体封装可以包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立器件或其它半导体管芯或电组件。小型化和重量减轻对于产品被市场接受而言是至关重要的。可以减小半导体器件之间的距离以实现更高的密度。
在图5中，PCB 302提供用于安装在PCB上的半导体封装的结构支承和电互连的一般基板。使用蒸发、电解电镀、无电电镀、丝网印刷或其它合适的金属沉积处理在PCB 302的层的表面上或内部形成导电信号迹线304。信号迹线304提供在半导体封装、安装的组件和其它外部系统组件的每个之间的电通信。迹线304还向每个半导体封装提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装层级。第一层级封装是用于将半导体管芯机械地和电气地附接到中间基板的技术。第二层级封装涉及将中间基板机械地和电气地附接到PCB。在其它实施例中，半导体器件可以仅具有第一层级封装，其中管芯被机械地和电气地直接安装到PCB。为了说明的目的，在PCB 302上示出若干种类型的第一层级封装，包括接合布线封装306和倒装芯片308。附加地，示出安装在PCB 302上的若干种类型的第二层级封装，包括球栅阵列(BGA)310、凸块芯片载体(BCC)312、平面网格阵列(LGA)316、多芯片模块(MCM)或SIP模块318、四方扁平无引线封装(QFN)320、四方扁平封装322、嵌入式晶片级球栅阵列(eWLB)324和晶片级芯片尺度封装(WLCSP)326。在一个实施例中，eWLB 324是扇出晶片级封装(Fo-WLP)并且WLCSP 326是扇入晶片级封装(Fi-WLP)。取决于系统要求，配置有第一层级封装类别和第二层级封装类别的任何组合的半导体封装的任何组合以及其它电组件可以被连接到PCB 302。在一些实施例中，电子设备300包括单个附接的半导体封装，而其它实施例要求多个互连的封装。通过在单个基板上组合一个或多个半导体封装，制造商可以将预制组件合并到电子设备和系统中。因为半导体封装包括复杂的功能性，所以可以使用更便宜的组件和流水线制造处理来制造电子设备。所得到的设备不太可能失效，并且制造起来更便宜，造成对于消费者而言的更低的成本。
虽然已经详细地说明了本发明的一个或多个实施例，但是本领域技术人员将领会，可以在不脱离如在随后的权利要求中阐述的本发明的范围的情况下作出对那些实施例修改和适配。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供电组件组装；
将模制化合物片材部署在电组件组装上；
将包括第一电路图案的载体部署在模制化合物片材上；以及
抵靠模制化合物片材按压载体，以将第一包封物部署在电组件组装之上和周围，并且将第一电路图案嵌入在第一包封物中。
2.根据权利要求1所述的方法，进一步包括移除载体以暴露出第一电路图案。
3.根据权利要求2所述的方法，进一步包括：
在第一包封物和第一电路图案上部署第二包封物；以及
在第二包封物上形成第二电路图案。
4.根据权利要求1所述的方法，进一步包括在电组件组装上形成屏蔽层。
5.一种制造半导体器件的方法，包括：
提供基板；
在基板上部署模制化合物片材；
将包括第一电路图案的载体部署在模制化合物片材上；以及
抵靠模制化合物片材按压载体，以将第一包封物部署在基板上并且将第一电路图案嵌入在第一包封物中。
6.根据权利要求5所述的方法，进一步包括将多个电组件部署在基板上以形成电组件组装。
7.根据权利要求6所述的方法，进一步包括在电组件组装上形成屏蔽层。
8.根据权利要求5所述的方法，进一步包括移除载体以暴露出第一电路图案。
9.根据权利要求8所述的方法，进一步包括：
在第一包封物和第一电路图案上部署第二包封物；以及
在第二包封物上形成第二电路图案。
10.一种半导体器件，包括：
电组件组装；
模制化合物片材，其被部署在电组件组装上；以及
载体，其包括部署在模制化合物片材上的第一电路图案，其中载体被适配为按压模制化合物片材以将第一包封物部署在电组件组装之上和周围并且将第一电路图案嵌入在第一包封物中。
11.根据权利要求10所述的半导体器件，进一步包括：
第二包封物，其被部署在第一包封物和第一电路图案上；以及
第二电路图案，其被形成在第二包封物上。
12.根据权利要求10所述的半导体器件，进一步包括在电组件组装上形成屏蔽层。
13.根据权利要求10所述的半导体器件，其中电组件组装包括：
基板；以及
被部署在基板上的多个电组件。
14.根据权利要求13所述的半导体器件，进一步包括形成在基板上的导电柱。
15.根据权利要求10所述的半导体器件，进一步包括部署在第一电路图案上的半导体封装。
CN202210325234.8A 2021-05-04 2022-03-30 半导体器件和在sip模块的包封物内形成电路图案的方法 Pending CN115295425A (zh)

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US7851894B1 (en) 2008-12-23 2010-12-14 Amkor Technology, Inc. System and method for shielding of package on package (PoP) assemblies
US9355962B2 (en) 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
US8421210B2 (en) 2010-05-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with dual side connection and method of manufacture thereof
US8304913B2 (en) * 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
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