CN115458418A - 用于rdl的基于pspi的图案化方法 - Google Patents

用于rdl的基于pspi的图案化方法 Download PDF

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Publication number
CN115458418A
CN115458418A CN202210256838.1A CN202210256838A CN115458418A CN 115458418 A CN115458418 A CN 115458418A CN 202210256838 A CN202210256838 A CN 202210256838A CN 115458418 A CN115458418 A CN 115458418A
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Prior art keywords
layer
semiconductor
pspi
package
conductive
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C·O·金
J·H·郑
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本公开涉及用于RDL的基于PSPI的图案化方法。通过提供包括屏蔽层的半导体封装并使用激光在屏蔽层中形成槽而形成半导体器件。激光被开启并被暴露到屏蔽层，其中，激光的中心设置在屏蔽层的第一点上。激光在环路中移动，同时激光保留在屏蔽层上并暴露到屏蔽层。当激光的中心设置在屏蔽层的第二点上时，停止激光到屏蔽层的暴露。第一点和第二点之间的距离近似等于激光的半径。

Description

用于RDL的基于PSPI的图案化方法
技术领域
本发明一般涉及半导体器件，并且更特别地涉及使用光敏聚酰亚胺（PSPI）进行RDL图案化的方法和半导体器件。
背景技术
半导体器件通常在现代电子产品中找到。半导体器件执行各种各样的功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光转换成电、以及为电视显示器产生视觉图像。半导体器件在通信、功率转换、网络、计算机、娱乐和消费产品的领域中找到。半导体器件也在军事应用、航空、汽车、工业控制器和办公设备中找到。
半导体制造的一个目标是生产较小的半导体器件。较小的器件通常消耗较少的功率，具有较高的性能，并且可以更高效地生产。此外，较小的半导体器件具有较小的占用区域（footprint），这对于较小的最终产品是期望的。通过前端工艺中的改进，可以实现较小的半导体管芯尺寸，从而产生具有较小、较高密度的有源和无源元器件的半导体管芯。后端工艺可以通过在电互连和封装材料中的改进而产生具有较小占用区域的半导体器件封装。
半导体封装通常形成有重分布层（RDL），所述重分布层（RDL）连接到半导体管芯或其他元器件上的端子并且将端子重分布为不同的占用区域或图案。制造较小器件的一个关键是减小RDL尺寸。随着电子器件变得较小和并入更多功能，这些器件必须在有限区域中容纳高密度的元器件。元器件的较高密度要求较小尺寸的RDL。
激光图案化在技术上能够形成当今高元器件密度所要求的小特征，但是随着特征变得较小，为最小化激光束直径所要求的设备费用正变得非常高。此外，激光图案化产生损坏在图案化层下面的表面的风险，并且还可能会损坏下面的半导体元器件。因此，存在如下需要：用于RDL形成的改进的图案化方法。
附图说明
图1a-1c示出具有由切道分离的多个半导体管芯的半导体晶片；
图2a-2l示出在制造重分布层中使用光敏聚酰亚胺；
图3a-3g示出使用光敏聚酰亚胺重分布层技术形成层叠封装（package-on-package）；
图4示出另一层叠封装实施例；
图5示出任何数量的封装层的接连形成；以及
图6a和6b示出将半导体封装集成到电子器件中。
具体实施方式
在以下描述中，参考附图在一个或多个实施例中描述本发明，在所述附图中，相同的数字表示相同或相似的要素。虽然根据用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员将会理解，本发明旨在覆盖可以包括在由所附权利要求以及由以下公开和附图支持的它们的等同物限定的本发明的精神和范围内的替代、修改和等同物。本文中所使用的术语“半导体管芯”指代单数形式和复数形式的词语两者，且因此可以指代单个半导体器件和多个半导体器件两者。
半导体器件通常使用两种复杂的制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含被电连接以形成功能电路的有源和无源电元器件。有源电元器件，例如晶体管和二极管，具有控制电流流动的能力。无源电元器件，例如电容器、电感器和电阻器，产生为执行电路功能所需的电压和电流之间的关系。
后端制造指代将完成的晶片切割或单片化为个别半导体管芯并封装该半导体管芯以用于结构支撑、电互连和环境隔离。为了单片化半导体管芯，晶片沿着晶片的称为切道或划线的非功能区域被刻划和断开。使用激光切割工具或锯条将晶片单片化。在单片化之后，将个别半导体管芯安装到封装衬底，所述封装衬底包括用于与其他系统元器件互连的引脚或接触焊盘。然后将形成在半导体管芯上的接触焊盘连接到封装内的接触。可以用导电层、凸块、柱形凸块、导电膏或接合线来进行电连接。将封装剂或其他模制材料沉积在封装上以提供物理支撑和电隔离。然后将完成的封装插入到电系统中，并且使半导体器件的功能可用于其他系统元器件。
图1a示出具有基底衬底材料102的半导体晶片100，所述基底衬底材料102例如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或用于结构支撑的其他块体材料。多个半导体管芯或元器件104形成在晶片100上，由无源、管芯间晶片区域或切道106分离。切道106提供切割区域以将半导体晶片100单片化成个别半导体管芯104。在一个实施例中，半导体晶片100具有100-450毫米（mm）的宽度或直径。
图1b示出半导体晶片100的一部分的截面图。每个半导体管芯104都具有背或无源表面108和有源表面110，所述有源表面110包含被实现为根据管芯的电设计和功能而形成在管芯内且电互连的有源器件、无源器件、导电层和电介质层的模拟或数字电路。例如，电路可以包括：一个或多个晶体管、二极管和其他电路元件，形成在有源表面110内以实现模拟电路或数字电路，例如数字信号处理器（DSP）、功率放大器、专用集成电路（ASIC）、存储器或其他信号处理电路。半导体管芯104还可以包含用于RF信号处理的IPD，例如电感器、电容器和电阻器。
使用PVD、CVD、电解电镀、化学电镀工艺或其他合适的金属沉积工艺在有源表面110上形成导电层112。导电层112可以是一层或多层铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）或其他合适的导电材料。导电层112作为电连接到有源表面110上的电路的接触焊盘来操作。
使用蒸发、电解电镀、化学电镀、球滴或丝网印刷工艺在导电层112上沉积导电凸块材料。凸块材料可以是具有可选焊剂溶液的Al、Sn、Ni、Au、Ag、铅（Pb）、铋（Bi）、Cu、焊料、其组合、或其他合适的导电材料。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺将凸块材料接合到导电层112。在一个实施例中，通过将凸块材料加热到其熔点以上来使该材料回流以形成球或凸块114。在一个实施例中，凸块114形成在具有润湿层、阻挡层和粘合层的凸块下金属化层（UBM）上。凸块114还可以被压缩接合或热压接合到导电层112。凸块114表示可以在导电层112上形成的一种类型的互连结构。互连结构还可以使用接合线、导电膏、柱形凸块、微凸块或其他电互连。
在图1c中，使用锯条或激光切割工具118通过切道106将半导体晶片100单片化成个别半导体管芯104。可以检查和电测试个别半导体管芯104以识别单片化后的已知良好管芯（KGD）。
图2a-2l示出使用光敏聚酰亚胺（PSPI）在半导体封装上形成重分布层（RDL）的工艺。图2a和2b示出正形成有半导体管芯104的示例性半导体封装200。封装200通常形成为连接在一起的多个封装的大面板，图2a和2b仅示出多个封装中的单个封装。图2a和2b示出中间形成步骤中的半导体封装200，其中，封装的第一层210已经完成。图2a是仅示出面板的一个单元的部分横截面，而图2b是同一单元的透视图。
衬底212被提供为足够大以一起形成期望数量的封装的面板。衬底212包括与一个或多个导电层216交错的一个或多个绝缘层214。在一个实施例中绝缘层214是具有在顶表面和底表面上图案化的导电层216的核心绝缘板，例如覆铜层压衬底。导电层216还包括：导电通孔，通过绝缘层214电耦合用于垂直互连。
衬底212可以包括彼此上交错的任何数量的导电层216和绝缘层214。焊料掩模或钝化层可以形成在衬底212的任一侧或两侧上。在钝化层中形成开口以暴露导电层216的接触焊盘用于随后的互连。在其他实施例中，任何合适类型的衬底或引线框用于衬底212。通常，第一层210形成在衬底212上作为足够大以同时形成几个到数百个或数千个封装的面板或条带。一旦完成，可以从所述条带单片化第一层210，或在完成所有期望的层之后将封装200单片化成个别封装。
对于第一层210的功能所期望的任何元器件被安装在或设置在衬底212上，并且使用焊料、焊膏、接合线或另一合适的互连结构电连接到导电层216。图2a示出与分立电元器件224一起安装在衬底212上的半导体管芯104。分立电元器件224可以是例如电容器、电阻器或电感器的无源元器件、例如二极管或晶体管的有源元器件、或任何其他期望的电元器件。
多个半导体管芯可以设置在衬底212上。半导体管芯104可以被提供作为较小的子封装的一部分而不是裸管芯。任何期望的电元器件可以安装在衬底212上，例如无源器件、半导体管芯、晶片级芯片尺寸封装（WLCSP）或系统级封装（SiP）模块。除了可以作为形成半导体封装200的一部分而提供的屏蔽之外，所安装的元器件可以具有形成在个别元器件上的EMI屏蔽层。
通过使用例如拾取和放置工艺或机器将半导体管芯设置在衬底上以及然后回流凸块114以将凸块物理和电连接到导电层216的暴露的接触焊盘，来将半导体管芯104安装到衬底212。分立元器件224由类似的焊料凸块或焊膏226连接。焊膏226可以在拾取分立元器件并将分立元器件放置到衬底上之前印刷到衬底212或分立元器件224上。回流焊膏226将分立元器件224物理和电耦合到导电层216的接触焊盘。
在将半导体管芯104、分立元器件224和任何其他期望的电元器件安装到衬底212上之后，通过封装剂或模制化合物228封装这些元器件。使用膏印刷、压缩模制、传递模制、液体封装剂模制、真空层压、旋涂或另一合适的施加器将封装剂228沉积在衬底212、半导体管芯104和分立元器件224上。封装剂228可以是聚合物复合材料，例如具有或不具有填料的聚合物、环氧树脂、或者环氧丙烯酸酯。封装剂228是不导电的，提供结构支撑，并且在环境上保护半导体器件免受外部要素和污染物。
通过封装剂228形成开口以暴露导电层216的接触焊盘。使用任何合适的金属沉积技术用导电材料填充开口以形成导电通孔230。用于导电通孔230的开口可以通过机械钻孔、化学蚀刻、激光钻孔或任何其他合适的工艺来形成。导电材料可以是Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料。导电通孔230提供第一层210和半导体封装200的随后形成的层之间的垂直互连。
在其他实施例中，在沉积封装剂228之前，导电通孔230作为导电柱、焊料凸块、覆铜焊料凸块（CCSB）、PCB单元、模块化互连单元或任何其他合适的互连结构而形成或设置在衬底212上。当在沉积封装剂228之前形成导电通孔230时，如果需要，封装剂可以经历背研磨、激光钻孔或其他合适的工艺以暴露导电通孔。
在制造工艺的任何阶段，在衬底212的底表面上形成凸块248。凸块248与半导体管芯104上的凸块114类似并以与该凸块114类似的方式形成。虽然为第一层210示出一种特定封装类型，但是第一层可以以任何合适的封装类型（例如嵌入式晶片级球栅阵列（eWLB）或其中衬底212的两侧都具有封装的元器件的双侧SiP模块）形成。
为了继续在第一层210上形成附加的封装层，RDL形成在封装剂228上并通过导电通孔230连接到第一层。图2c示出第二封装层250的RDL形成工艺中的第一步骤。PSPI层260形成在第一层210上。PSPI层260包括光敏聚酰亚胺。在一个实施例中，PSPI被旋涂到第一层210面板上并且然后被固化。替选地，PSPI可以使用任何其他合适的方法以液体形式沉积，或者作为预成型片材设置在第一层210上。PSPI层260横跨正形成在面板中的所有封装完全覆盖并物理接触导电通孔230和封装剂228的顶表面。
PSPI层260用作光刻抗蚀剂层。为了使用PSPI层260制造RDL，通过掩模262照射PSPI层，如图2d所示。掩模262具有形成在掩模中的对应于RDL层的所期望图案的图案264。对于正在制造的面板的每个单元，掩模262通常包括形成在掩模中的相同图案，因为正一起制造的所有单元都旨在是相同的。
辐射266通过掩模262照射在PSPI层260上。掩模262阻挡除了形成图案264的地方的辐射266，这导致辐射以与阴影图案270所指示的相同图案撞到PSPI层。阴影图案270示出在辐射266撞到PSPI层260的地方与掩模262阻挡辐射并投射阴影的地方之间的边界。撞到PSPI层260的辐射266在被撞到的区域对PSPI引起化学变化。
然后使用化学显影剂仅在被辐射266化学改变的区域中去除PSPI层260，如图2e所示。化学显影剂通常是液体，该液体被旋涂到PSPI层260上并与PSPI层的暴露于辐射266的部分反应，从而按照图案274去除PSPI。PSPI层260的被掩模262的阴影保护而免受辐射266的区域在显影之后保留。PSPI层260的显影导致图案274与掩模262的图案264几乎相同。PSPI层260在图案274内被完全去除，使得封装剂228和导电通孔230在图案内被暴露。
在图2f中，在具有图案274的PSPI层260上溅射导电材料以形成导电层276。导电层276使用任何合适的金属沉积技术（例如化学气相沉积、物理气相沉积、其他溅射方法、喷涂或电镀）来形成。溅射材料可以是铜、钢、铝、金、其组合或任何其他合适的导电材料。
导电层276完全覆盖PSPI层260。导电层276还延伸到图案274中以物理接触封装剂228和导电通孔230。导电层276是共形层，这意味着在所有暴露表面上沉积均匀厚度的导电材料。导电层276在PSPI层260的顶表面、图案274内的PSPI层的侧表面、以及图案内的封装剂228和导电通孔230的暴露顶表面上形成有大致相同厚度的导电材料。在其他实施例中，图案274完全填充有导电材料。
导电层276通过导电通孔230电连接到衬底212的导电层216。导电层276仅形成在第一层210的顶表面上，因为第一层保留为未单片化的面板。在其他实施例中，第一层210可以在形成导电层276之前被单片化，以便在每个单元的侧表面上形成导电层。
在图2g中，PSPI层260与导电层276的形成在PSPI层上的部分一起被去除。通过在封装200上分配溶剂来去除PSPI层260。PSPI层260被溶解。导电层276的形成在图案274内的封装剂228和导电通孔230上的部分保留粘合到第一层210，但是导电层的粘合到PSPI层260的部分随着PSPI层的溶解而被去除。PSPI层260可以替选地使用任何其他合适的手段来剥离、抬离或去除。
导电层276作为导电图案284保留在第一层210的顶部上作为第二层250的开始。导电图案284非常类似于来自掩模262的图案264和使用掩模在PSPI层260中形成的图案274。导电图案284对应于多个接触焊盘284a、导电迹线284b和作为第二封装层250的RDL操作所需的其他导电结构。接触焊盘284a根据期望来分布，以用于连接到下面的通孔230、用于随后安装半导体元器件以及如果要形成附加层则用于随后互连到上覆层。接触焊盘284a的阵列保留用于倒装芯片或表面安装集成电路的应用。留下接触焊盘284a对用于安装分立无源器件。接触焊盘284a保留在导电通孔230上，以将第二层250连接到第一层210的下面的元器件。导电迹线284b根据需要将接触焊盘284a彼此连接，以实现封装200的期望的电功能。在一些实施例中，留下导电层276的部分以作为EMI屏蔽来操作。
图2h示出安装到接触焊盘284a上的半导体管芯292、eWLB封装294、WLCSP 296和分立电容器298。使用任何合适的工艺，例如用拾取和放置机器，将安装的元器件设置在第一层210上。在安装的元器件292-298的接触焊盘与接触焊盘284a之间回流的焊料凸块或焊膏提供机械耦合和电耦合两者。可以在元器件和第一层210之间沉积模制底部填充物。任何期望的电子元器件都可以作为第二层250的一部分安装到导电图案284上。这些元器件可以是任何分立的无源或有源器件、裸管芯、WLCSP、或单侧或双侧模制的SiP模块。除了作为封装200的一部分形成的屏蔽之外，任何元器件都可选地具有在个别元器件上或内形成的它们自己的屏蔽层。
在图2i中，封装剂300沉积在安装的元器件292-298上以为第二层250提供封装体。封装剂300类似于封装剂228，即，以类似的工艺沉积并由类似的材料形成。封装剂300完全覆盖导电图案284和封装剂228的顶表面（包括安装到导电图案284的所有元器件）。为了制造多于两个封装层，可以形成通过封装剂300的导电通孔，类似于通过封装剂228的导电通孔230。图2c-2i中示出的制造步骤可以无限地重复以产生任何合适数量的封装层。
一旦完成所期望数量的层，就使用锯条、激光切割工具、喷水器或其他合适的工具将封装200的面板单片化以分离所述封装，如图2j所示。单片化去除每个封装200之间的与正被使用的锯口相对应的一定宽度的材料。被去除的材料导致每个封装200具有暴露的侧表面306。侧表面306包括衬底212、封装剂228和封装剂300的共面表面。在一些实施例中，导电图案284横跨切道延伸并且具有与其他表面共面的暴露表面作为侧表面306的一部分。每个封装200通常形成为矩形形状，以具有总共四个侧表面306。在其他实施例中可以制造其他封装形状。
图2k和2l示出通过在封装上形成屏蔽层310而正完成的封装200。屏蔽层310通过在封装200上溅射导电材料而形成。使用任何合适的金属沉积技术（例如化学气相沉积、物理气相沉积、其他溅射方法、喷涂或电镀），形成屏蔽层310。溅射材料可以是铜、钢、铝、金、其组合或任何其他合适的材料。屏蔽层310完全覆盖封装剂300的侧表面306以及顶表面。屏蔽层310作为电磁辐射屏蔽来操作以减少干扰。
封装200包括在具有高元器件密度的小封装中的各种功能。使用基于PSPI的光刻形成导电图案284允许改进图案化分辨率，而没有损坏第一层210的下面的元器件的显著风险。PSPI层260的图案化分辨率和精度相对于现有技术是高的，因此可以制造较小的特征以适应较高密度的元器件。虽然上述PSPI图案化工艺被公开为是作为第二封装层250的一部分在第一封装层210上进行的，但是与上述相同的工艺可以作为第一封装层的一部分进行以在衬底212上形成RDL。任何RDL层都可以使用所示出的基于PSPI的工艺来形成。
如图2k和2l所示的封装200可以被用在电子器件中。凸块248可以回流到PCB或其他衬底的接触焊盘上，以将封装200的功能并入到较大系统中。替选地，封装200可以用作堆叠封装（PoP）顶部封装，如图3a-3g所示。
图3a示出层叠封装底部封装320。底部封装320具有类似于顶部封装200的第一层210，并且还具有形成在第一封装层的顶表面上的接触焊盘322。导电迹线还可以与和接触焊盘322相同的导电层一起形成。接触焊盘322通过导电通孔230连接到下面的半导体元器件。接触焊盘322的布局根据需要被配置以将顶部封装200安装到接触焊盘。使用上述基于PSPI的图案化工艺来形成接触焊盘322和任何必要的导电迹线。
图3b示出顶部封装320的面板330。封装剂228、导电通孔230和接触焊盘322的顶表面被胶带332覆盖。胶带332是使用粘合剂粘到第一层210的粘合性胶带。在其他实施例中，可以将胶带332层压到第一层210上。图3c示出从面板330单片化的底部封装320。胶带332保留覆盖底部封装320的顶表面，并且单片化产生在每个邻近底部封装之间的间隙。侧表面306通过单片化而暴露。
在图3d中，在具有胶带332的封装320上形成屏蔽层336。使用任何合适的金属沉积技术，例如化学气相沉积、物理气相沉积、其他溅射方法、喷涂或电镀，形成屏蔽层336。溅射材料可以是铜、钢、铝、金、其组合或任何其他合适的导电材料。屏蔽层336完全覆盖胶带332以及每个底部封装的侧表面306。
在图3e中去除胶带332。胶带332的去除还去除在封装320顶部上的屏蔽层336，从而暴露接触焊盘322。侧表面306保留由屏蔽层336覆盖，因为胶带332未设置在侧表面上。
在图3f中，来自图2k和2l的顶部封装200被安装到接触焊盘322上以形成PoP 340。图3g示出完成的PoP 340。顶部封装200的凸块248被回流以将顶部封装机械和电连接到底部封装320。顶部封装200中的元器件通过凸块248、接触焊盘322和导电通孔230电耦合到底部封装320中的元器件。底部封装320的屏蔽层336与顶部封装200的屏蔽层310结合以完全屏蔽PoP 340。底部封装320由阻挡EMI从侧面进入的屏蔽层336和由阻挡EMI从顶部进入的屏蔽层310保护。即使底部封装320不具有形成在底部封装的顶表面上的屏蔽层，但顶部封装200的屏蔽层310提供足够的保护。
虽然底部封装320被示出为仅具有单个封装层210，但是底部封装还可以具有第二封装层250，其中，接触焊盘322形成在第二封装层而不是第一封装层上。与顶部封装200一样，底部封装320可以形成有任何合适数量的封装层。
图4示出PoP 350。除了不形成屏蔽层310和336之外，以与上面在图2a-2l和图3a-3g中示出的方式相同的方式形成PoP 350。顶部封装200的制造工艺在图2j中的单片化之后停止。屏蔽层310没有如图2k和2l所示的那样形成。通过在没有胶带332的情况下并且在没有如图3c-3e所示的那样形成屏蔽层336的情况下将图3b中的面板330单片化来完成底部封装320。层叠封装组件可以用屏蔽层310而不是屏蔽层336来制造，反之亦然。
图5示出无限地将附加层堆叠到任何合适数量的层。虽然上述实施例仅示出两层210和250，但是对于顶部封装200和底部封装320两者来说，可以继续无限地形成附加层。使用上述相同的PSPI图案化方法，导电层284形成在需要RDL的每层的顶部上。图案化、元器件安装、模制或部分模制以及然后金属沉积或EMI屏蔽的工艺可以无限地重复，直到在期望数量的中间封装层之后形成顶层360。
图6a和6b示出将上述封装（例如，具有形成在第一层210和第二层250上的屏蔽层310的封装200）并入到电子器件400中。图6a示出作为电子器件400的一部分安装到印刷电路板（PCB）或其他衬底402上的封装200的部分横截面。凸块248形成在衬底212的底部上的导电层216上。导电凸块248可以在制造工艺的任何阶段形成，例如在模制封装剂228之前、在单片化之前、或在形成屏蔽层310之后形成。使凸块248回流到PCB 402的导电层404上，以将封装200物理附着并电连接到PCB。在其他实施例中，使用热压或其他合适的附着和连接方法。在一些实施例中，在封装200和PCB 402之间使用粘合剂或底部填充物层。半导体管芯104通过衬底212和凸块248电耦合到导电层404。
图6b示出具有安装在PCB 402的表面上的多个半导体封装的电子器件400，所述多个半导体封装包括封装200。电子器件400可以具有一种类型的半导体封装，或者多种类型的半导体封装，这取决于应用。电子器件400可以是使用半导体封装来执行一个或多个电功能的独立系统。替选地，电子器件400可以是较大系统的子元器件。例如，电子器件400可以是平板计算机、蜂窝电话、数码相机、通信系统或其他电子器件的一部分。电子器件400还可以是图形卡、网络接口卡或插入到计算机中的另一信号处理卡。半导体封装可以包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立有源或无源器件以及其他半导体管芯或电元器件。
在图6b中，PCB 402提供用于安装在PCB上的半导体封装的结构支撑和电互连的一般衬底。使用蒸发、电解电镀、化学电镀、丝网印刷或其他合适的金属沉积工艺在PCB 402的表面上或在PCB 402的层内形成导电信号迹线404。信号迹线404提供半导体封装、安装的元器件和其他外部系统或元器件之间的电通信。迹线404还根据需要向半导体封装提供电源和地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是用于将半导体管芯机械和电附着到中间衬底的技术。第二级封装涉及将中间衬底机械和电附着到PCB 402。在其他实施例中，半导体器件可以仅具有第一级封装，其中，管芯直接机械和电安装到PCB402。
为了说明的目的，在PCB 402上示出几种类型的第一级封装，包括接合线封装406和倒装芯片408。另外，几种类型的第二级封装，包括球栅阵列（BGA）410、凸块芯片载体（BCC）412、接点栅格阵列（LGA）416、多芯片模块（MCM）418、四方扁平无引线封装（QFN）420、四方扁平封装422和eWLB 424，被示出与封装200一起安装在PCB 402上。导电迹线404将设置在PCB 402上的各种封装和元器件电耦合到封装200，从而将封装200内的元器件的使用给予PCB上的其他元器件。
根据系统要求，配置有第一和第二级封装样式的任何组合的半导体封装的任何组合以及其他电子元器件可以连接到PCB 402。在一些实施例中，电子器件400包括单个附着的半导体封装，而其他实施例要求多个互连的封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预制的元器件并入到电子器件和系统中。由于半导体封装包括复杂的功能，所以可以使用不太贵的元器件和流水线制造工艺来制造电子器件。所得到的器件不太可能失效，并且制造不太贵，从而导致消费者的较低成本。
虽然已经详细地示出本发明的一个或多个实施例，但是本领域技术人员将会理解，在不偏离所附权利要求中阐述的本发明的范围的情况下可以做出对那些实施例的修改和适配。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供第一半导体封装层；
在所述第一半导体封装层上设置光敏聚酰亚胺（PSPI）层；
在PSPI层中形成图案；
在PSPI层上形成导电层；以及
去除PSPI层，以在所述第一半导体封装层上按照所述图案留下所述导电层。
2.根据权利要求1所述的方法，还包括：
单片化所述第一半导体封装层；
在单片化之后在所述第一半导体封装层上设置胶带；以及
在所述第一半导体封装层和胶带上形成屏蔽层。
3.根据权利要求2所述的方法，还包括在去除所述PSPI层之后将第二半导体封装安装到所述导电层，其中，所述第二半导体封装包括形成在所述第二半导体封装的侧表面和顶表面上的屏蔽层。
4.根据权利要求3所述的方法，还包括在形成所述屏蔽层之后并且在安装所述第二半导体封装之前去除所述胶带。
5.根据权利要求1所述的方法，还包括通过以下操作来在所述第一半导体封装层上形成第二半导体封装层：
在PSPI层中形成所述图案作为重分布层（RDL）图案；
在去除PSPI层之后，将第二半导体器件安装到所述导电层；以及
在所述第二半导体器件上沉积第二封装剂。
6.根据权利要求5所述的方法，还包括通过以下操作来在所述第二半导体封装层上形成第三半导体封装层：
使用基于PSPI的光刻在所述第二半导体封装层上形成第二RDL；
将第三半导体器件安装到所述第二RDL；以及
在所述半导体器件上沉积第三封装剂。
7. 一种制造半导体器件的方法，包括：
提供第一半导体封装层；以及
使用光敏聚酰亚胺（PSPI）层以进行光刻，在所述第一半导体封装层上形成重分布层（RDL）。
8.根据权利要求7所述的方法，还包括将半导体封装安装到所述RDL。
9.根据权利要求7所述的方法，还包括通过经过图案化的掩模照射所述PSPI层来图案化所述PSPI层。
10. 根据权利要求9所述的方法，还包括通过以下操作来形成所述RDL：
在图案化之后在所述PSPI层上沉积导电层；以及
去除所述PSPI层以留下所述RDL。
11. 一种半导体器件，包括：
半导体封装层；以及
光敏聚酰亚胺（PSPI）层，所述光敏聚酰亚胺（PSPI）层形成在所述半导体封装层上，其中，重分布层（RDL）图案形成在所述PSPI层中。
12.根据权利要求11所述的半导体器件，还包括导电层，所述导电层形成在所述PSPI层上并且延伸到所述RDL图案中。
13.根据权利要求12所述的半导体器件，其中，所述导电层物理地接触所述RDL图案内的半导体封装层的导电通孔。
14.根据权利要求11所述的半导体器件，还包括设置在所述半导体封装层上的掩模，其中，所述RDL图案形成在所述掩模中。
15.根据权利要求14所述的半导体器件，还包括设置在所述掩模上的辐射源。
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