CN117727719A - 半导体装置和堆叠混合基底的方法 - Google Patents

半导体装置和堆叠混合基底的方法 Download PDF

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Publication number
CN117727719A
CN117727719A CN202310782608.3A CN202310782608A CN117727719A CN 117727719 A CN117727719 A CN 117727719A CN 202310782608 A CN202310782608 A CN 202310782608A CN 117727719 A CN117727719 A CN 117727719A
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Prior art keywords
substrate
rdl
conductive
core substrate
conductive layer
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Inventor
林耀剑
蔡佩燕
高英华
左健
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本公开涉及半导体装置和堆叠混合基底的方法。半导体装置具有：RDL基底；和混合基底，具有多个凸块。混合基底被接合到RDL基底。包封剂被沉积在混合基底和RDL基底周围，其中凸块被嵌入在包封剂内。混合基底具有：核心基底；第一RDL，被形成在核心基底的第一表面上；导电支柱，被形成在第一RDL上；和第二RDL，在核心基底的第二表面上。包封剂的部分被去除以暴露导电支柱。RDL基底具有：载体；和RDL，被形成在载体的表面上。在将混合基底接合到RDL基底之后，载体被去除。替代地，RDL基底具有：核心基底；第一RDL，被形成在核心基底的第一表面上；和第二RDL，被形成在核心基底的第二表面上。

Description

半导体装置和堆叠混合基底的方法
技术领域
本发明一般地涉及半导体装置，并且更特别地涉及半导体装置和堆叠混合基底的方法。
背景技术
半导体装置常常存在于现代电气产品中。半导体装置执行广泛的各种功能，诸如信号处理、高速计算、传送和接收电磁信号、控制电气装置、光电以及创建用于电视显示器的视觉图像。半导体装置存在于通信、功率转换、网络、计算机、娱乐和消费产品的领域中。半导体装置还存在于军事应用、航空、汽车、工业控制器和办公装备中。
半导体装置经常包含半导体管芯或基底，其中电气互连结构(例如，重分布层(RDL))被形成在半导体管芯或基底的一个或多个表面上以执行必要的电气功能。在制造过程期间，半导体装置被形成在晶片或面板。在RDL的形成期间，晶片和面板经受翘曲。更大的扇出装置具有更高的翘曲的风险，并且因此具有更低的产量，导致更高的制造成本。
附图说明
图1a-1c图示具有通过锯切街区(saw street)而分离的多个第一半导体管芯的第一半导体晶片；
图2a-2b图示在载体上形成RDL层的过程；
图3a-3h图示形成混合基底的过程；
图4a-4e图示形成混合基底组件的过程；
图5图示混合基底组件面板的单切；
图6图示混合基底组件的另一实施例；
图7a-7e图示形成混合基底组件的另一过程；
图8a-8c图示将电气部件和屏蔽安放在混合基底组件上；和
图9图示印刷电路板(PCB)，其中不同类型的封装被安放在PCB的表面上。
具体实施方式
在下面的描述中在一个或多个实施例中参照附图描述本发明，其中相同的数字代表相同或类似的元件。尽管按照用于实现本发明的目的的最佳模式描述了本发明，但本领域技术人员将会理解，旨在包括如由下面的公开和附图支持的所附权利要求及其等同物所定义的本发明的精神和范围内可包括的替代物、修改和等同物。附图中示出的特征未必按照比例绘制。具有类似的功能的元件在附图中被分派相同的标号。如在本文中所使用，术语“半导体管芯”既指代词语的单数形式又指代词语的复数形式，并且因此，能够既指代单个半导体装置又指代多个半导体装置。
通常使用两种复杂的制造过程来制造半导体装置：前端制造和后端制造。前端制造涉及半导体晶片的表面上的多个管芯的形成。晶片上的每个管芯包含有源和无源电气部件，所述有源和无源电气部件按照电气方式连接以形成功能电路。有源电气部件(诸如，晶体管和二极管)具有控制电流的流动的能力。无源电气部件(诸如，电容器、电感器和电阻器)创建执行电路功能所需的电压和电流之间的关系。
后端制造指代将完成的晶片切割或单切成个体半导体管芯，并且封装半导体管芯以用于结构支撑、电气互连和环境隔离。为了单切半导体管芯，晶片沿着晶片的非功能区域(称为锯切街区或划线)被刻划并且断开。晶片使用激光切割工具或锯片而被单切。在单切之后，个体半导体管芯被安放在封装基底上，所述封装基底包括用于与其它系统部件互连的管脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。能够利用导电层、凸块、螺柱凸块、导电膏或导线接合来实现电气连接。包封剂或其它模制成型材料被沉积在封装上以提供物理支撑和电气隔离。完成的封装然后被插入到电气系统中，并且半导体装置的功能使得可用于其它系统部件。
图1a示出半导体晶片100，半导体晶片100具有底部基底材料102，诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或用于结构支撑的其它基体材料。多个半导体管芯或电气部件104被形成在晶片100上，通过非有源管芯间晶片区域或锯切街区106而被分离。锯切街区106提供切割区域以将半导体晶片100单切为个体半导体管芯104。在一个实施例中，半导体晶片100具有100-450毫米(mm)的宽度或直径。
图1b示出半导体晶片100的一部分的剖视图。每个半导体管芯104具有后表面或非有源表面108和有源表面110，所述有源表面110包含模拟或数字电路，所述模拟或数字电路被实现为有源装置、无源装置、导电层和介电层，所述有源装置、无源装置、导电层和介电层被形成在管芯内并且根据管芯的电气设计和功能按照电气方式互连。例如，电路可包括形成在有源表面110内的一个或多个晶体管、二极管和其它电路元件以实现模拟电路或数字电路，诸如数字信号处理器(DSP)、专用集成电路(ASIC)、存储器或其它信号处理电路。半导体管芯104还可包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。
使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层112被形成在有源表面110上。导电层112能够是一层或多层的铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)或其它合适的导电材料。导电层112用作按照电气方式连接到有源表面110上的电路的接触焊盘。
使用蒸发、电解镀覆、化学镀覆、焊球滴落9ball drop)或丝网印刷过程，导电凸块材料被沉积在导电层112上。凸块材料能够是具有可选的助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合过程，凸块材料被接合到导电层112。在一个实施例中，通过将凸块材料加热到它的熔点以上来使凸块材料回流以形成球或凸块114。在一个实施例中，凸块114被形成在凸块下金属化(UBM)上，所述UBM具有润湿层、阻挡层和粘合剂层。凸块114还能够被压缩接合或热压缩接合到导电层112。凸块114代表能够被形成在导电层112上的一种类型的互连结构。互连结构还能够使用接合线、导电膏、螺柱凸块、微凸块或其它电气互连。
在图1c中，通过锯切街区106使用锯片或激光切割工具118，半导体晶片100被单切成个体半导体管芯104。个体半导体管芯104能够被检查并且按照电气方式测试以在单切之后识别已知良好管芯或已知良好单元(KGD/KGU)。
图2a示出临时基底或载体120牺牲底部材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其它合适的低成本刚性材料。半导体基底120具有主表面122和124。在一个实施例中，载体120是具有临时接合层的支撑结构以在表面122和/或124上形成电气互连特征。
在图2b中，使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化，绝缘或钝化层130被形成在表面122上。绝缘层130包含一层或多层的二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、阻焊剂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并噁唑(PBO)以及具有类似的绝缘和结构性质的其它材料。绝缘层130包括一种或多种填料131，诸如阻焊剂或模制成型片。使用蚀刻过程或激光直接烧蚀(LDA)，绝缘层130的一部分可被去除，以用于进一步的电气互连。
使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层132被形成在载体120的表面122上。导电层132能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层132是接触焊盘。在一个实施例中，导电层132具有小于1.0μm的厚度。根据半导体管芯和附着到它的其它电气部件的设计和功能，导电层132的各部分能够按照电气方式共用或按照电气方式隔离。绝缘层130在导电层132周围提供隔离。
使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层134被形成在绝缘层130和导电层132上。导电层134能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层134是重分布层(RDL)，并且提供水平和垂直电气互连。根据半导体管芯和附着到它的其它电气部件的设计和功能，导电层134的各部分能够按照电气方式共用或按照电气方式隔离。
使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化，绝缘或钝化层136被形成在绝缘层130和导电层134上。绝缘层136包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、阻焊剂、聚酰亚胺、BCB、PBO以及具有类似的绝缘和结构性质的其它材料。绝缘层136在导电层134周围提供隔离。使用蚀刻过程或LDA，绝缘层136的部分被去除以暴露导电层134从而用于进一步的电气互连。
使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层138被形成在导电层134和绝缘层136上。导电层138能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层138是RDL，并且提供水平和垂直电气互连。根据半导体管芯和附着到它的其它电气部件的设计和功能，导电层138的各部分能够按照电气方式共用或按照电气方式隔离。
使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化，绝缘或钝化层140被形成在绝缘层136和导电层138上。绝缘层140包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、阻焊剂、聚酰亚胺、BCB、PBO以及具有类似的绝缘和结构性质的其它材料。绝缘层140在导电层138周围提供隔离。使用蚀刻过程或LDA，绝缘层140的部分被去除以暴露导电层138从而用于进一步的电气互连。导电层132、134和138以及绝缘层130、136和140的组合构成形成在载体120上的RDL叠层142。
图3a示出半导体晶片或面板基底150，半导体晶片或面板基底150具有底部基底材料152，诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅、具有填料和/或纤维的聚合物(比如，环氧树脂、聚酰亚胺)基质复合材料或用于结构/绝缘支撑的没有绝缘/介电性质(例如，电阻率＞1x1010ohm.cm)的其它基体材料。半导体基底150具有主表面154和156。在一个实施例中，半导体基底150是支撑结构以在表面154和156上形成电气互连特征。
替代地，晶片150能够具有形成在表面154和/或表面156上的半导体装置。有源表面154和/或156将会包含模拟或数字电路，所述模拟或数字电路被实现为有源装置、无源装置、导电层和介电层，所述有源装置、无源装置、导电层和介电层被形成在管芯内并且根据管芯的电气设计和功能按照电气方式互连。例如，电路可包括形成在表面154、156内的一个或多个晶体管、二极管和其它电路元件以实现模拟电路或数字电路，诸如DSP、ASIC、存储器或其它信号处理电路。有源表面154、156还可包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。
多个通孔/孔158被形成为完全穿过基底150。可选的阻焊剂/光致抗蚀剂能够被形成在表面154上。阻焊剂/光致抗蚀剂定义图案以将过孔158蚀刻为完全穿过底部半导体材料152。替代地，通过机械钻孔或激光钻孔，能够形成过孔/孔158。在图3b中，过孔158被填充，或者过孔侧壁被利用导电材料镀覆，并且阻焊剂/光致抗蚀剂被去除，留下导电过孔160。导电过孔160能够是Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。
在图3c中，各种芯/填塞材料能够被形成在导电过孔160中。阻焊剂/光致抗蚀剂能够被形成在表面154上。阻焊剂/光致抗蚀剂定义图案以将过孔蚀刻为穿过以前形成的导电过孔160。例如，过孔被形成为穿过每个导电过孔160a、160b和160c。替代地，过孔158在侧壁被利用金属镀覆，而没有另外的图案化和蚀刻。形成为穿过导电过孔160a的过孔被利用镀覆的磁性材料或膏162填充以提供调谐电感。磁性材料162能够是铁、铁氧体(镍铁氧体、镍锌铁氧体、YIG铁氧体)或其它合适的磁粉末或其组合。磁性材料162能够是镀覆的磁膜，诸如NiFe、CoNiFe或CoZrTa。在一个实施例中，磁性材料162是低温(＜200℃)无压可固化粉末膏，诸如来自Ajinomoto的H701和K250。形成为穿过导电过孔160b和160c的过孔被利用镀覆的Cu或Cu膏164填充以改善热性能。
在图3d中，使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层170被形成在基底150的表面154上。导电层170能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层170是RDL，并且横跨基底150提供水平电气互连并且为导电过孔160提供垂直电气互连。根据半导体管芯和附着到它的其它电气部件的设计和功能，导电层170的各部分能够按照电气方式共用或按照电气方式隔离。
使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化，绝缘或钝化层172被形成在表面154和导电层170上。绝缘层172包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、阻焊剂、聚酰亚胺、BCB、PBO以及具有类似的绝缘和结构性质的其它材料。绝缘层172在导电层170周围提供隔离。使用蚀刻过程或LDA，绝缘层172的部分被去除以暴露导电层170从而用于进一步的电气互连。
使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层174被形成在导电层170和绝缘层172上。导电层174能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层174是RDL，并且横跨基底150提供水平电气互连并且为导电过孔160提供垂直电气互连。根据半导体管芯和附着到它的其它电气部件的设计和功能，导电层174的各部分能够按照电气方式共用或按照电气方式隔离。
在图3e中，使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化，绝缘或钝化层176被形成在绝缘层172和导电层174上。绝缘层176包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、阻焊剂、聚酰亚胺、BCB、PBO以及具有类似的绝缘和结构性质的其它材料。绝缘层176在导电层174周围提供隔离。使用蚀刻过程或LDA，绝缘层176的部分被去除以暴露导电层174从而用于进一步的电气互连。
阻焊剂或光致抗蚀剂层180被形成在绝缘层176上。使用蚀刻过程或LDA，多个开口182被形成在阻焊剂/光致抗蚀剂中以定义图案从而形成导电柱或支柱。开口182被利用导电材料186填充，如图3f中所示。在图3g中，剩余的阻焊剂/光致抗蚀剂180被去除，留下导电柱或导电支柱或导电杆188。导电柱或导电支柱或导电杆188能够是Al、Cu、Sn、Ni、Au、Ag、多层组合或其它合适的导电材料。导电支柱188能够具有小于5.0μm的高度以补偿不同技术(诸如，表面安装和倒装芯片)中的厚度变化。在一个实施例中，导电支柱188可具有形成在暴露的焊盘或金属表面上的Cu有机可焊性保护剂(OSP)或化学镀镍化学镀钯浸金(ENEPIG)或化学镀镍浸金(ENIG)或浸锡或焊料帽饰面(finish)或层189。替代于导电支柱188，能够使用BGA球。
在图3h中，使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层190被形成在表面156上。导电层190能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层190是RDL，并且横跨基底150提供水平和垂直电气互连。根据半导体管芯和附着到它的其它电气部件的设计和功能，导电层190的各部分能够按照电气方式共用或按照电气方式隔离。
使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化，绝缘或钝化层192被形成在表面156和导电层190上。绝缘层192包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、阻焊剂、聚酰亚胺、BCB、PBO以及具有类似的绝缘和结构性质的其它材料。绝缘层192在导电层190周围提供隔离。使用蚀刻过程或LDA，绝缘层192的部分被去除以暴露导电层190从而用于进一步的电气互连。
使用PVD、CVD、电解镀覆、化学镀覆过程或其它合适的金属沉积过程，导电层194被形成在导电层190和绝缘层192上。导电层194能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层194是RDL，并且横跨基底150提供水平和垂直电气互连。根据半导体管芯和附着到它的其它电气部件的设计和功能，导电层194的各部分能够按照电气方式共用或按照电气方式隔离。
使用PVD、CVD、印刷、层压、旋涂、喷涂、烧结或热氧化，绝缘或钝化层196被形成在导电层194和绝缘层192上。绝缘层196包含一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、阻焊剂、聚酰亚胺、BCB、PBO以及具有类似的绝缘和结构性质的其它材料。绝缘层196在导电层194周围提供隔离。使用蚀刻过程或LDA，绝缘层196的部分被去除以暴露导电层194从而用于进一步的电气互连。
使用蒸发、电解镀覆、化学镀覆、焊球滴落(ball drop)或丝网印刷过程，导电凸块材料被沉积在导电层194上。凸块材料能够是具有可选的助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合过程，凸块材料被接合到导电层194。在一个实施例中，通过将凸块材料加热到它的熔点以上来使凸块材料回流以形成球或凸块198。在一个实施例中，凸块198被形成在UBM上，所述UBM具有润湿层、阻挡层和粘合剂层。凸块198还能够被压缩接合或热压缩接合到导电层194。在一个实施例中，为了耐久性以及保持其高度，凸块198是铜芯凸块。凸块198代表能够被形成在导电层194上的一种类型的互连结构。互连结构还能够使用接合线、导电膏、螺柱凸块、微凸块或其它电气互连。
基底150被嵌入在导电层170、174、190和194以及绝缘层172、176、192和196之间，这构成具有嵌入的基底的互连结构。嵌入的基底150与导电层170、174、190和194以及绝缘层172、176、192和196、导电支柱188以及凸块198的组合构成混合基底200。混合基底200可具有与RDL叠层142相同数量的RDL层或更多的RDL层。
在图4a中，混合基底200被安放在来自图2b的形成在载体120上的RDL叠层142上。使凸块198与RDL叠层142的导电层138接触并且回流以按照机械方式和按照电气方式将混合基底200连接到RDL叠层142，被指示为混合基底组件202并且示出在图4b中。底部填充材料203(诸如，环氧树脂)能够被沉积在凸块198以及混合基底200和RDL叠层142的部分周围。
在图4c中，使用膏印刷、压缩模制成型、传递模制成型、液体包封剂模制成型、真空层压、旋涂或其它合适的涂敷器，包封剂或模制成型化合物204被沉积在混合基底组件202上，并且沉积在混合基底组件202周围。包封剂204能够是液体或粒状聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯树脂或具有合适的填料的聚合物。包封剂204是非导电的，提供结构支撑，并且在环境方面保护半导体装置免受外部元素和污染物的影响。特别地，在形成混合基底组件202之后，沉积包封剂204。凸块198被嵌入在底部填充材料203和包封剂204内。
在图4d中，通过化学蚀刻、化学机械抛光(CMP)、机械剥离、机械研磨、热烘烤、紫外(UV)光或湿法脱模，载体120被去除以暴露导电层132并且提供混合基底组件206。混合基底200经受利用研磨器208的研磨以暴露导电支柱188上的饰面189。研磨可发生在载体去除之前或之后。另一Cu OSP或ENEPIG或ENIG或浸锡或焊料帽饰面或层189能够被形成在暴露的焊盘或金属表面上。
图4e示出混合基底组件206的特征的进一步细节。特别地，绝缘层130包括一种或多种填料131，诸如阻焊剂或模制成型片。导电层132能够具有形成在暴露的焊盘或金属表面上的Cu OSP或ENEPIG或ENIG或浸锡或焊料帽饰面或层210。层210能够低于、等于或高于绝缘层130。
图5示出面 212上的混合基底组件206的多个单元。混合基底组件206沿着线214和216被单切成个体混合基底组件。替代地，载体120被单切，并且电气互连结构142被接合到混合基底200作为个体单元。在另一实施例中，为了更好的产量管理和更低的总成本和相等或更好的性能，用于不同线/空间基底的不同层数和不同堆积材料被预先堆叠。
图6示出类似于图4e实施例，其中在研磨之后，绝缘层222被形成在包封剂204和绝缘层176上。作为具有一种或多种填料(诸如，阻焊剂或模制成型片)的聚合物复合物，绝缘层222类似于绝缘层130，具有小于25μm的厚度。绝缘层222和包封剂204的部分被去除以暴露导电层174。替代于导电支柱188，BGA焊料帽220被形成在导电层174上。
图7a示出半导体晶片或面板基底230，半导体晶片或面板基底230具有底部基底材料232，诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅、具有填料和/或纤维的聚合物(比如，环氧树脂、聚酰亚胺)基质复合材料或用于结构/绝缘支撑的没有绝缘/介电性质(例如，电阻率＞1x1010ohm.cm)的其它基体材料。半导体基底230具有主表面234和236。在一个实施例中，半导体基底230是支撑结构以在表面234和236上形成电气互连特征。
替代地，晶片230能够具有形成在表面234和/或表面236上的半导体装置。有源表面234和/或236将会包含模拟或数字电路，所述模拟或数字电路被实现为有源装置、无源装置、导电层和介电层，所述有源装置、无源装置、导电层和介电层被形成在管芯内并且根据管芯的电气设计和功能按照电气方式互连。例如，电路可包括形成在表面234、236内的一个或多个晶体管、二极管和其它电路元件以实现模拟电路或数字电路，诸如DSP、ASIC、存储器或其它信号处理电路。有源表面234、236还可包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。
多个通孔/孔被形成为完全穿过基底230，类似于图3a。可选的阻焊剂/光致抗蚀剂能够被形成在表面234上。阻焊剂/光致抗蚀剂定义图案以将过孔蚀刻为完全穿过底部半导体材料232。替代地，通过机械钻孔或激光钻孔，能够形成过孔/孔。过孔被填充，或者过孔侧壁被利用导电材料镀覆，并且阻焊剂/光致抗蚀剂被去除，留下导电过孔238。导电过孔238能够是Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。
在图7b中，导电层240和244以及绝缘层242和246被形成在基底230的表面234上，类似于图3d-3e。导电层250和254以及绝缘层252和256被形成在表面236上，类似于图3h。导电层254能够具有形成在暴露的焊盘或金属表面上的Cu OSP或ENEPIG或ENIG或浸锡或焊料帽饰面或层258。精压的(coined)焊盘上焊料(SOP)259被沉积在导电层254上。
嵌入的基底230与导电层240、244、250和254以及绝缘层242、246、252和256的组合构成RDL混合基底260。混合基底200可具有与RDL混合基底260相同数量的RDL层或更多的RDL层。
在图7c中，来自图3h的混合基底200被安放在RDL混合基底260上。使凸块198与RDL混合基底260的导电层244接触并且回流以按照机械方式和按照电气方式将混合基底200连接到RDL混合基底260，如图7d中所示。
使用膏印刷、压缩模制成型、传递模制成型、液体包封剂模制成型、真空层压、旋涂或其它合适的涂敷器，包封剂或模制成型化合物264被沉积在混合基底200和RDL混合基底260上，并且沉积在混合基底200和RDL混合基底260周围。包封剂264能够是液体或粒状聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯树脂或具有合适的填料的聚合物。包封剂264是非导电的，提供结构支撑，并且在环境方面保护半导体装置免受外部元素和污染物的影响。特别地，在形成混合基底组件202和RDL混合基底260之后，沉积包封剂264。凸块198被嵌入在包封剂264内。
在图7e中，类似于图4d，混合基底200经受研磨，以暴露导电支柱188上的饰面189。另一Cu OSP或ENEPIG或ENIG或浸锡或焊料帽饰面或层189能够被形成在暴露的焊盘或金属表面上以提供混合基底组件270。
从图4e继续，多个电气部件280a-280d被安放在混合基底组件206上，并且按照电气方式和按照机械方式连接到导电层132和导电支柱188，如图8a中所示。电气部件280a-280d还能够被安装到混合基底组件270。使用拾取和放置操作，电气部件280a-280d每个均被安置在混合基底组件206上。例如，电气部件280b能够类似于来自图1c的半导体管芯104，其中凸块114被定向为朝着混合基底组件206。电气部件280a、280c和280d能够是分立电气装置或IPD，诸如二极管、晶体管、电阻器、电容器和电感器。替代地，电气部件280a-280d能够包括其它半导体管芯、半导体封装、表面安装装置、分立电气装置或IPD。
使电气部件280a-280c与混合基底组件206的导电层132接触。使电气部件280d与导电支柱188接触。利用凸块114，电气部件280b按照电气方式和按照机械方式连接到导电层132。使用焊料或导电膏282和286，电气部件280a和280c分别按照电气方式和按照机械方式连接到导电层132。使用焊料或导电膏288，电气部件280d按照电气方式和按照机械方式连接到导电支柱188。图8b图示按照电气方式和按照机械方式连接到混合基底组件206的电气部件280a-280d。
使用蒸发、电解镀覆、化学镀覆、焊球滴落或丝网印刷过程，导电凸块材料被沉积在导电支柱188上。凸块材料能够是具有可选的助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料能够是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合过程，凸块材料被接合到导电支柱188。在一个实施例中，通过将凸块材料加热到它的熔点以上来使凸块材料回流以形成球或凸块290。在一个实施例中，凸块290被形成在UBM上，所述UBM具有润湿层、阻挡层和粘合剂层。凸块290还能够被压缩接合或热压缩接合到导电支柱188。在一个实施例中，为了耐久性以及保持其高度，凸块290是铜芯凸块。凸块290代表能够被形成在导电支柱188上的一种类型的互连结构。互连结构还能够使用接合线、导电膏、螺柱凸块、微凸块或其它电气互连。
混合基底组件206内或附着到混合基底组件206的电气部件可包含容易受到EMI、RFI、谐波失真和装置间干扰影响或产生EMI、RFI、谐波失真和装置间干扰的IPD。例如，半导体管芯104或电气部件280a-280d内所包含的IPD提供高频应用所需的电气特性，诸如谐振器、高通滤波器、低通滤波器、带通滤波器、对称Hi-Q谐振变压器和调谐电容器。在另一实施例中，半导体管芯104或电气部件280a-280d包含按照高频切换的数字电路，这能够干扰其它IPD的操作。
为了解决EMI、RFI、谐波失真和装置间干扰，屏蔽框架296被安置在混合基底组件206上，如图8b中所示。屏蔽框架296能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。替代地，屏蔽框架296能够是羰基铁、不锈钢、镍银、低碳钢、硅铁刚、箔、导电树脂、炭黑、铝薄片以及能够减少或抑制EMI、RFI和其它装置间干扰的影响的其它金属和复合物。在图8c中，使屏蔽框架296与混合基底组件206接触，并且利用导电膏298通过导电层132接地。
替代地，框架296能够是具有热界面材料的热沉或散热器。热沉能够是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它合适的导热材料。热沉296耗散由混合基底组件206产生的热量。
图9图示电气装置400，电气装置400具有芯片载体基底或PCB 402，其中多个半导体封装被安放在PCB 402的表面上，所述多个半导体封装包括混合基底组件206和270。根据应用，电气装置400能够具有一种类型的半导体封装或多种类型的半导体封装。
电气装置400能够是使用半导体封装来执行一个或多个电气功能的独立系统。替代地，电气装置400能够是更大系统的子部件。例如，电气装置400能够是平板计算机、蜂窝电话、数字照相机、通信系统或其它电气装置的一部分。替代地，电气装置400能够是图形卡、网络接口卡或能够被插入到计算机中的其它信号处理卡。半导体封装能够包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立装置或者其它半导体管芯或电气部件。为了使产品被市场接受，小型化和重量减少是必要的。半导体装置之间的距离可被降低以实现更高的密度。
在图9中，PCB 402为安放在PCB上的半导体封装的结构支撑和电气互连提供一般基底。使用蒸发、电解镀覆、化学镀覆、丝网印刷或其它合适的金属沉积过程，导电信号轨迹404被形成在PCB 402的表面上或形成在PCB 402的层内。信号轨迹404提供每个半导体封装、安装的部件和其它外部系统部件之间的电气通信。轨迹404还为每个半导体封装提供电源和地连接。
在一些实施例中，半导体装置具有两个封装级别。第一级封装是用于按照机械方式和按照电气方式将半导体管芯附着到中间基底的技术。第二级封装涉及按照机械方式和按照电气方式将中间基底附着到PCB。在其它实施例中，半导体装置可具有第一级封装，其中管芯被按照机械方式和按照电气方式直接安放在PCB上。为了说明的目的，若干种类型的第一级封装(包括接合线封装406和倒装芯片408)被示出在PCB 402上。另外，若干种类型的第二级封装(包括球栅阵列(BGA)410、凸块芯片载体(BCC)412、栅格阵列(LGA)416、多芯片模块(MCM)或SIP模块418、矩形平面无引线封装(QFN)420、矩形平面封装422、嵌入式晶片级球栅阵列(eWLB)424和晶片级芯片规模封装(WLCSP)426)被示出为安放在PCB 402上。在一个实施例中，eWLB 424是扇出晶片级封装(Fo-WLP)，并且WLCSP 426是扇入晶片级封装(Fi-WLP)。根据系统要求，配置有第一和第二级封装风格的任何组合的半导体封装的任何组合以及其它电气部件能够连接到PCB 402。在一些实施例中，电气装置400包括单个附着的半导体封装，而其它实施例需要多个互连的封装。通过在单个基底上组合一个或多个半导体封装，制造商能够将预制部件包括在电气装置和系统中。因为半导体封装包括复杂的功能，所以能够使用不太昂贵的部件和流水制造过程来制造电气装置。所得到的装置不太可能失效并且不太昂贵地制造，导致更低的消费者的成本。
尽管本发明的一个或多个实施例已被详细地图示，但本领域技术人员将会理解，可在不脱离如下面的权利要求中所阐述的本发明的范围的情况下对那些实施例做出修改和适配。

Claims (15)

1.一种半导体装置，包括：
重分布层(RDL)基底；
混合基底，包括多个凸块，其中所述混合基底被接合到所述RDL基底；和
包封剂，被沉积在所述混合基底和RDL基底周围，其中所述凸块被嵌入在所述包封剂内。
2.如权利要求1所述的半导体装置，其中所述混合基底包括：
核心基底；
第一RDL，被形成在所述核心基底的第一表面上；和
多个导电支柱，被形成在所述第一RDL上。
3.如权利要求2所述的半导体装置，其中所述混合基底还包括形成在与所述核心基底的所述第一表面相对的所述核心基底的第二表面上的第二RDL。
4.如权利要求1所述的半导体装置，其中所述RDL基底包括：
核心基底；
第一RDL，被形成在所述核心基底的第一表面上；和
第二RDL，被形成在与所述核心基底的所述第一表面相对的所述核心基底的第二表面上。
5.如权利要求1所述的半导体装置，还包括：
电气部件，被安放在所述混合基底上；和
屏蔽层，被安放在所述电气部件上。
6.一种半导体装置，包括：
第一基底；
第二基底，包括多个第一凸块，其中所述第二基底被接合到所述第一基底；和
包封剂，被沉积在所述第一基底和第二基底周围，其中所述第一凸块被嵌入在所述包封剂内。
7.如权利要求6所述的半导体装置，其中所述第二基底包括：
核心基底；
第一RDL，被形成在所述核心基底的第一表面上；和
多个导电支柱，被形成在所述第一RDL上。
8.如权利要求7所述的半导体装置，其中所述第二基底还包括形成在与所述核心基底的所述第一表面相对的所述核心基底的第二表面上的第二RDL。
9.如权利要求6所述的半导体装置，其中所述第一基底包括：
核心基底；
第一RDL，被形成在所述核心基底的第一表面上；和
第二RDL，被形成在与所述核心基底的所述第一表面相对的所述核心基底的第二表面上。
10.如权利要求6所述的半导体装置，还包括：
电气部件，被安放在所述第二基底上；和
屏蔽层，被安放在所述电气部件上。
11.一种制作半导体装置的方法，包括：
提供第一基底；
提供第二基底，所述第二基底包括多个第一凸块；
将所述第二基底接合到所述第一基底；并且
将包封剂沉积在所述第一基底和第二基底周围，其中所述第一凸块被嵌入在所述包封剂内。
12.如权利要求11所述的方法，其中提供所述第二基底包括：
提供核心基底；
在所述核心基底的第一表面上形成第一RDL；并且
在所述第一RDL上形成多个导电支柱。
13.如权利要求12所述的方法，其中提供所述第二基底还包括：
在与所述核心基底的所述第一表面相对的所述核心基底的第二表面上形成第二RDL；并且
去除所述包封剂的一部分以暴露所述导电支柱。
14.如权利要求12所述的方法，还包括：
将电气部件安放在所述导电支柱中的第一导电支柱上；并且
在所述导电支柱中的第二导电支柱上形成第二凸块。
15.如权利要求11所述的方法，其中提供所述第一基底包括：
提供核心基底；
在所述核心基底的第一表面上形成第一RDL；并且
在与所述核心基底的所述第一表面相对的所述核心基底的第二表面上形成第二RDL。
CN202310782608.3A 2022-09-19 2023-06-29 半导体装置和堆叠混合基底的方法 Pending CN117727719A (zh)

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