TWI787805B - 電子模組及其製法與電子封裝件 - Google Patents
電子模組及其製法與電子封裝件 Download PDFInfo
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Abstract
一種電子模組,其係於電子元件之側面與非作用面上依序形成第一金屬層、一絕緣層、及第二金屬層,供作為電容結構,其中,該電容結構係外露出該電子元件之作用面,以藉由將該電容結構直接形成於該電子元件上,使該電容結構與該電子元件之間的距離最小化,因而能達到抑制阻抗的最佳效果。
Description
本發明係有關一種半導體晶片,尤指一種具電容結構之電子模組及其製法與電子封裝件。
隨著現今高速運算應用的終端產品(如自動駕駛、超級電腦或行動裝置等產品)蓬勃發展,該些產品之內部電子元件亦碰到技術上的瓶頸與挑戰。例如,半導體晶片接置於基板上,當該基板之金屬走線(trace)之迴路電流連接到該半導體晶片時,會產生高頻電源阻抗,因而會產生噪聲,故該半導體晶片容易在臨界位置上因干擾而產生錯誤的訊號,進而產生錯誤的動作。
因此,業界遂於該基板之周圍之不同位置上設置去耦電容(Decoupling Capacitor,簡稱Decap),以抑制高頻電源阻抗的發生。
圖1A係習知電子裝置1之剖面示意圖。如圖1A所示,該電子裝置1係包含一半導體封裝件1a,其係於一封裝基板11與半導體晶片10之間設置一矽中介板(Through Silicon interposer,簡稱TSI)13,該矽中介板13具有導電矽穿孔(Through-silicon via,簡稱TSV)130及形成於該導電矽穿孔130上之線路重佈結構(Redistribution layer,簡稱RDL)131,令該矽中介板13以其中介側13b之導
電矽穿孔130藉由複數導電元件16電性結合具較大間距之封裝基板11之銲墊110,並以底膠15包覆該些導電元件16,而具較小間距之半導體晶片10之電極墊100係藉由複數銲錫凸塊101電性結合該矽中介板13之置晶側13a之線路重佈結構131,再以底膠14包覆該些銲錫凸塊101。最後,形成一封裝膠體12於該封裝基板11上,以令該封裝膠體12包覆該半導體晶片10與該矽中介板13。
該電子裝置1復包含一電路板1b,以於該半導體封裝件1a之封裝基板11下側形成複數銲球17,以結合該電路板1b。
於習知電子裝置1中,若將未配置去耦電容結構之情況所產生的阻抗值定義為1x,則當將至少一去耦電容元件18a放置於該電子裝置1中之不同位置上時,越靠近該半導體晶片10,所產生之阻抗抑制之效果越好,如下表一所示:
因此,基於上述原理,業界遂將去耦電容(Decap)結構一體製作於該矽中介板13內。如圖1B所示,該矽中介板13於製作導電矽穿孔130時,一併製作複數間隔排列且未貫穿該矽中介板13之導電開孔132,以令該些導電開孔132作為去耦電容18b,使該去耦電容18b藉由該線路重佈結構131電性導通該半導體晶片10,故該去耦電容18b可非常靠近該半導體晶片10,以達到抑制阻抗之效果(阻抗值如表一所示之0.058x)。
然而,於該矽中介板13中,該些導電開孔132需配合該導電矽穿孔130製作,因而需於孔洞中進行填充介電材、電鍍金屬材等製程,故會產生製程時間冗長、製作成本提高、製作難度大增、製作良率降低等問題,因而完全不符合降低該電子裝置1之成本之需求。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子模組,係包括:電子元件,係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,且該作用面係具有複數電極墊;以及電容結構,係形成於該電子元件上且外露出該作用面,其中,該電容結構係包含有一設於該電子元件上且電性連接該複數電極墊之第一金屬層、一設於該第一金屬層上之絕緣層、及設於該絕緣層上並電性耦合該第一金屬層之第二金屬層,且該第一金屬層未接觸該第二金屬層。
本發明復提供一種電子模組之製法,係包括:於一承載件上設置電子元件,其中,該電子元件係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,且該作用面係具有複數電極墊,以令該電子元件以該作用面結合至該承載件上;於該電子元件上依序形成第一金屬層、絕緣層及第二金屬層,且該第一金屬層未接觸該第二金屬層,以令該第一金屬層、絕緣層及第二金屬層作為電容結構;以及移除該承載件。
前述之電子模組及其製法中,該電容結構係形成於該電子元件之非作用面及/或該側面上。
前述之電子模組及其製法中,該電容結構係為去耦電容型式。
前述之電子模組及其製法中,該電子元件之內部係配置有至少一電性連接該電極墊之導線,以令該第一金屬層電性連接該導線。例如,該導線外露於該電子元件之側面及/或該非作用面。
前述之電子模組及其製法中,該電子元件係具有單一組電源傳輸結構,使該電容結構電性連接該電源傳輸結構。
前述之電子模組及其製法中,該電子元件係具有多組電源傳輸結構,使該電容結構電性連接該多組電源傳輸結構。例如,該第一金屬層係包含相互間隔(分開而不相連)之複數電性連接部,以令該複數電性連接部分別電性連接不同組之該電源傳輸結構。進一步,該非作用面係於各該電性連接部之間形成有分隔區域,以令該第一金屬層未遮蓋該分隔區域,使該絕緣層形成於該分隔區域上而接觸該非作用面。
本發明另提供一種電子封裝件,係包括:承載結構,係具有線路層;以及前述之電子模組,係設於該承載結構上,且該電容結構係電性連接該線路層。
前述之電子封裝件中,復包括電性連接該電子元件之佈線結構。例如,該佈線結構係具有相對之第一表面與第二表面,以令該電子模組配置於該第一表面上,且於該第二表面上配置至少一第二電子元件。或者,該承載結構之線路層與該佈線結構之間係藉由複數導電柱相互電性連接。
前述之電子封裝件中,該承載結構上係形成有複數電性連接該線路層之導電柱。例如,復包括包覆該複數導電柱、電子元件與該電容結構之包覆層。
前述之電子封裝件中,復包括包覆該電子元件與該電容結構之包覆層。
由上可知,本發明之電子模組及其製法與電子封裝件中,主要藉由將該電容結構直接形成於該電子元件上,以令該電容結構鄰接該電子元件,故相較於習知技術,本發明之電子模組不僅能使去耦電容(即該電容結構)與半導體晶片(即該電子元件)之間的距離最小化,因而能達到抑制阻抗的最佳效果,且能符合降低製作成本之需求。
1:電子裝置
1b,2b:電路板
1a:半導體封裝件
10:半導體晶片
100,210,300,300b,300c:電極墊
101:銲錫凸塊
11:封裝基板
110:銲墊
12:封裝膠體
13:矽中介板
13a:置晶側
13b:中介側
130:導電矽穿孔
131:線路重佈結構
132:導電開孔
14,15:底膠
16,29:導電元件
17:銲球
18a:去耦電容元件
18b:去耦電容
2:電子封裝件
20:承載結構
20a:第一側
20b:第二側
200:第一介電層
201:第一線路層
21:第一電子元件
21a,30a:作用面
21b,30b:非作用面
21c,30c:側面
210a,300a:接點
211,301,301b,301c:導線
212:導電體
22,32:電容結構
220,32b:絕緣層
221,32a:第一金屬層
222,32c:第二金屬層
23:導電柱
24:第二電子元件
25:包覆層
26:佈線結構
26a:第一表面
26b:第二表面
260:第二介電層
261:第二線路層
27:導電凸塊
28:封裝層
3,3a:電子模組
30,31:電子元件
321,322:電性連接部
4:晶圓
8,9:承載件
90:板體
91:結合層
A:分隔區域
L,S:切割路徑
圖1A係為習知電子裝置之剖面示意圖。
圖1B係為圖1A之矽中介板之另一態樣之剖面示意圖。
圖2A至圖2E係為本發明之電子封裝件之製法之剖視示意圖。
圖3A至圖3F係為本發明之電子模組之製法之剖視示意圖。
圖3E-1至圖3F-1係為圖3E至圖3F之另一方式之剖視示意圖。
圖3E-2係為圖3E-1之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述
之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2A至圖2E係為本發明之具有電容結構22之電子封裝件2之製法的剖面示意圖。
如圖2A所示,將一承載結構20設於一承載件9上,且該承載結構20係具有相對之第一側20a與第二側20b,且該承載結構20之第一側20a上設置有至少一第一電子元件21及複數導電柱23(如以銅之金屬材或銲錫材製作)。
於本實施例中,該承載結構20係例如為具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構之封裝基板、具導電矽穿孔(Through-silicon via,簡稱TSV)之矽中介板(Through Silicon interposer,簡稱TSI)或其它板型,其包含至少一第一介電層200及至少一結合該第一介電層200之第一線路層201,如至少一扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL)。例如,形成該第一線路層201之材質係為銅,且形成該第一介電層200之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)之介電材。應可理解地,該承載結構20亦可為其它承載晶片之基材,如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等,並不限於上述。
再者,該承載結構20之第二側20a係藉由複數導電元件29設於該承載件9上。例如,該承載件9係包含如半導體材、介電材、陶瓷材、玻璃或金屬材之板體90,但不限於此,且該承載件9之尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrate),並可藉由如離型膜或膠材之結合層91,其以塗佈或貼合方式形成於該板體90上,使該承載結構20壓合於該結合層91上,且令該些導電元件29嵌埋於該結合層91中。
又,該第一電子元件21係為主動元件、被動元件或其組合者,其中,該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於
本實施例中,於本實施例中,該第一電子元件21係為半導體晶片,其具有相對之作用面21a與非作用面21b及鄰接該作用面21a與非作用面21b之側面21c,該第一電子元件21係以其非作用面21b設於該承載結構20之第一側20a上,而該作用面21a具有複數電極墊210(其可位於如圖2A所示之作用面21a之中間處)及複數接點210a(其可位於如圖2A所示之作用面21a之外圍處),其中,該第一電子元件21之內部係配置有至少一電性連接該電極墊210之導線211及複數電性連接該接點210a之積體電路(圖未示),且該導線211外露於該第一電子元件21之側面21c。例如,於該電極墊210及該接點210a上可依需求形成有如柱狀、針狀或其它凸塊狀之導電體212,並於該作用面21a上形成有一絕緣保護膜(圖略),以令該導電體212外露於該絕緣保護膜。
另外,該第一電子元件21之非作用面21b與側面21c上係形成有一電性連接該第一電子元件21之電容結構22,如去耦電容(Decap),其包含一設於該第一電子元件21(非作用面與側面)上且電性連接該導線211之第一金屬層221、一設於該第一金屬層221上之絕緣層220、及設於該絕緣層220上並電性耦合該第一金屬層221之第二金屬層222,以令該第一電子元件21藉由該電容結構22設於該承載結構20之第一側20a上,且該第二金屬層222係電性連接該第一線路層201以作為該電容結構22之接地埠。例如,形成該第一金屬層221與第二金屬層222之材質係為銅,且形成該絕緣層220之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等之介電材。
如圖2B所示,形成一包覆層25於該承載結構20之第一側20a上,以令該包覆層25包覆該第一電子元件21、電容結構22與該些導電柱23。接著,形成一佈線結構26於該包覆層25上,以令該佈線結構26電性連接該些導電柱23與該第一電子元件21。
於本實施例中,形成該包覆層25之材質係為聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)等絕緣材,但並不限於上述。例如,可採用壓合(lamination)或模壓(molding)等方式將該包覆層25形成於該承載結構20之第一側20a上。
再者,可依需求進行整平製程,以令該包覆層25之上表面齊平該導電柱23之端面與該導電體212之頂面,使該導電柱23之端面與該導電體212之頂面外露出該包覆層25。例如,可藉由研磨方式進行該整平製程,以移除該導電柱23之部分材質、該導電體212之部分材質與該包覆層25之部分材質。
又,該佈線結構26係具有相對之第一表面26a與第二表面26b,以令該佈線結構26以其第一表面26a結合該包覆層25,使該第一電子元件21與該導電柱23配置於該第一表面26a上。
另外,該佈線結構26係具有至少一第二介電層260及設於該第二介電層260上之第二線路層261(如RDL),以令該佈線結構26之第二線路層261電性連接該些導電柱23與該第一電子元件21上之導電體212。例如,形成該第二線路層261之材質係為銅,且形成該第二介電層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)之介電材。
如圖2C所示,設置至少一第二電子元件24於該佈線結構26之第二表面26b上,再以一封裝層28包覆該第二電子元件24。
於本實施例中,該第二電子元件24係為主動元件、被動元件或其二者組合,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。例如,該第二電子元件24係以覆晶方式藉由複數如銲錫凸塊、銅凸塊或其它等之導電凸塊27電性連接該佈線結構26之第二線路層261;然而,有關該第二電子元件24連接該佈線結構26之方式繁多,如打線封裝方式,並不限於上述。
再者,該封裝層28可同時包覆該第二電子元件24與該些導電凸塊27。或者,亦可先形成底膠(圖略)於該第二電子元件24與該佈線結構26之第二表面26b之間以包覆該些導電凸塊27,再形成該封裝層28以包覆該底膠與該第二電子元件24。
又,該封裝層28係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound),其可用壓合(lamination)或模壓(molding)之方式形成於該佈線結構26上。應可理解地,形成該封裝層28之材質可相同或不相同該包覆層25之材質。
另外,該封裝層28可依需求包覆該第二電子元件24之背面(圖未示)或外露該第二電子元件24之背面(如圖2C所示)。
如圖2D所示,移除該承載件9及其上之結合層91,以外露出該複數導電元件29。
如圖2E所示,沿如圖2D所示之切割路徑S進行切單製程,以獲取複數電子封裝件2,使該電子封裝件2可藉由該些導電元件29接置於一電路板2b上。
因此,本發明之電子封裝件2主要採用金屬-絕緣層-金屬二極體(Metal-insulator-metal diode,簡稱MIM diode)技術,將該電容結構22形成於該第一電子元件21上,以令該電容結構22鄰接該第一電子元件21,使去耦電容(Decap)最靠近半導體晶片,故相較於習知技術,依據前述表一之原理,本發明之電子封裝件2將該電容結構22與該第一電子元件21嵌埋於該包覆層25中之同一處,使兩者之間的距離最小化,因而能達到抑制阻抗之最佳效果(阻抗值小於0.058x,約0.01x~0.04x),進一步能消弭阻抗所產生之噪聲。
圖3A至圖3F係為本發明之具有電容結構22之第一電子元件21之相關電子模組3之製法的剖面示意圖。
如圖3A至圖3B所示,將一晶圓4進行切單製程,以獲取複數電子元件30。接著,將複數電子元件30間隔排設於一整版面承載件8上。
於本實施例中,該電子元件30係如第一電子元件21之構造,其具有相對之作用面30a與非作用面30b,該作用面30a具有複數電極墊300及複數接點300a,且該電子元件30之內部係配置有複數電性連接該電極墊300之導線301,並以該作用面30a結合至該承載件8上。應可理解地,可於該電極墊300與該接點300a上依需求形成如圖2A所示之導電體212,並以絕緣保護膜(圖略)包覆該導電體212,以令該電子元件30以該絕緣保護膜結合於該承載件8上。
再者,於切單該晶圓4後,該導線301將外露於該電子元件30之側面30c。應可理解地,該導線301亦可外露於該電子元件30之非作用面30b。
如圖3C至圖3E所示,於該電子元件30之非作用面30b與側面30c上依序形成第一金屬層32a、絕緣層32b及第二金屬層32c,且該第一金屬層32a未接觸該第二金屬層32c,以令該第一金屬層32a、絕緣層32b及第二金屬層32c作為電容結構32,如去耦電容(Decap),使該電容結構32包覆該電子元件30。
於本實施例中,該第一金屬層32a係採用電鍍、沉積或其它方式塗佈於該電子元件30之全部或部分之非作用面30b及/或全部或部分之側面30c上,且該絕緣層32b係塗佈於該第一金屬層32a之全部表面上,而該第二金屬層32c係採用電鍍、沉積或其它方式塗佈於該第一金屬層32a之全部表面上。
再者,該第一金屬層32a係接觸該導線301,以藉由該導線301電性連接該電極墊300,且該第一金屬層32a未電性連接該些接點300a。例如,該電容結構32係對應該電子元件30之單一組電源傳輸結構(即該些電極墊300),因而該第一金屬層32a僅為單一電性連接部,且該第二金屬層32c係作為該電容結構32之接地埠。
或者,如圖3E-1所示,該電容結構32亦可對應該電子元件31之多組電源傳輸結構。例如,該電子元件31係具有兩組電源傳輸結構,且該第一金屬層32a係包含複數相互分開而不相連之電性連接部321,322,如圖3E-2所示,以令該複數電性連接部321,322分別電性連接不同組之電源傳輸結構(即不同之導線301b,301c或不同之電極墊300b,300c),而該第二金屬層32c係作為該電容結構32之接地埠。具體地,該非作用面30b係於該電性連接部321,322之間形成有分隔區域A,以令該第一金屬層32a未遮蓋該分隔區域A,使該絕緣層32b形成於該分隔區域A上而接觸該非作用面30b。
如圖3F所示,接續圖3E之製程,以沿如圖3E所示之切割路徑L進行切單製程,再移除該承載件8,俾獲取複數電子模組3,且該電容結構32未形成於該電子元件30,31之作用面30a上。
於本實施例中,將該電子模組3應用於圖2E所示之電子封裝件2中,該電子元件30僅具有一組電源傳輸結構(即該些電極墊300),故該電子元件30能提供一個第二電子元件24所需之電源,而其它第二電子元件24需連接其它電源。
再者,若接續圖3E-1之製程,可獲取如圖3F-1所示之電子模組3a,且將該電子模組3a應用於圖2E所示之電子封裝件2中,該電子元件31具有兩組電源傳輸結構(即該些電極墊300b,300c),故該電子元件30能提供兩個第二電子元件24所需之電源。
應可理解地,基於該電子元件30,31之電源傳輸結構之組數,該第一金屬層32a之電性連接部321,322之數量可依需求設計,並不限於上述。
因此,本發明之電子模組3,3a主要採用金屬-絕緣層-金屬二極體(Metal-insulator-metal diode,簡稱MIM diode)技術,將該電容結構32形成於該電子元件30,31上,以簡化製程,故相較於習知技術之矽板鑽孔作業,本發明
之電子模組3,3a之製作簡單、製程時間短、生產良率高及製作成本低,因而能符合降低該電子封裝件2及其後續產品應用之成本之需求。
本發明係提供一種電子模組3,3a,係包括:一電子元件30,31以及一電容結構32。
所述之電子元件30,31係具有相對之作用面30a與非作用面30b及鄰接該作用面30a與非作用面30b之側面30c,且該作用面30a係具有複數電極墊300,300b,300c。
所述之電容結構32係形成於該電子元件30,31上且外露出該作用面30a,其中,該電容結構32係包含有一設於該電子元件30,31上且電性連接該複數電極墊300,300b,300c之第一金屬層32a、一設於該第一金屬層32a上之絕緣層32b、及設於該絕緣層32b上並電性耦合該第一金屬層32a之第二金屬層32c,且該第一金屬層32a未接觸該第二金屬層32c。
於一實施例中,該電容結構32係形成於該電子元件30,31之非作用面30a及/或該側面30c上。
於一實施例中,該電容結構32係為去耦電容型式。
於一實施例中,該電子元件30,31之內部係配置有至少一電性連接該電極墊300,300b,300c之導線301,301b,301c,以令該第一金屬層32a電性連接該導線301,301b,301c。例如,該導線301,301b,301c外露於該電子元件30,31之側面30c及/或該非作用面30b。
於一實施例中,該電子元件30係具有單一組電源傳輸結構(即相連之電極墊300與導線301),使該電容結構32電性連接該電源傳輸結構。
於一實施例中,該電子元件31係具有多組電源傳輸結構(即相連之電極墊300b與導線301b,以及相連之電極墊300c與導線301c),使該電容結構32電性連接該多組電源傳輸結構。例如,該第一金屬層32a係包含複數相互分開
而不相連之電性連接部321,322,以令該複數電性連接部321,322分別電性連接不同組之該電源傳輸結構。進一步,該非作用面30b係於各該電性連接部321,322之間形成有分隔區域A,以令該第一金屬層32a未遮蓋該分隔區域A,使該絕緣層32b形成於該分隔區域A上而接觸該非作用面30b。
於一實施例中,該電子模組3,3a可應用於一電子封裝件2中,該電子封裝件2係將該電子模組3,3a設於一具有第一線路層201之承載結構20上,且該電子模組3,3a係包含有該電子元件30,31(或第一電子元件21)及該電容結構22,32,且該電容結構22,32係電性連接該第一線路層201。
所述之電子模組3,3a之電子元件30,31(或第一電子元件21)之電極墊300,210係電性連接一佈線結構26。
於一實施例中,該佈線結構26係具有相對之第一表面26a與第二表面26b,以令該電子模組3,3a配置於該第一表面26a上,且於該第二表面26b上配置至少一第二電子元件24。或者,該承載結構20之第一線路層201與該佈線結構26之間係藉由複數導電柱23相互電性連接。
於一實施例中,該承載結構20上係形成有複數電性連接該第一線路層201之導電柱23。
於一實施例中,所述之電子封裝件2復包括一包覆該複數導電柱23、該電子元件30,31(或第一電子元件21)與該電容結構22,32之包覆層25。
綜上所述,本發明之電子模組及其製法與電子封裝件,主要藉由於該電子元件上直接形成多層複合式電容結構,以令該電容結構鄰接該電子元件,故本發明之電子模組不僅能使去耦電容與半導體晶片之間的距離最小化,因而能達到抑制阻抗的最佳效果,且能符合降低製作成本之需求。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對
上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
3:電子模組
30:電子元件
30a:作用面
30b:非作用面
30c:側面
300:電極墊
300a:接點
301:導線
32:電容結構
32a:第一金屬層
32b:絕緣層
32c:第二金屬層
Claims (24)
- 一種電子模組,係包括:電子元件,係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,且該作用面係具有複數電極墊,其中,該電子元件之內部係配置有至少一電性連接該電極墊之導線,且該導線外露於該電子元件之側面及/或該非作用面;以及電容結構,係形成於該電子元件上且外露出該作用面,其中,該電容結構係包含有一設於該電子元件上且電性連接該複數電極墊之第一金屬層、一設於該第一金屬層上之絕緣層、及設於該絕緣層上並電性耦合該第一金屬層之第二金屬層,且該第一金屬層未接觸該第二金屬層。
- 如請求項1所述之電子模組,其中,該電容結構係形成於該電子元件之非作用面及/或該側面上。
- 如請求項1所述之電子模組,其中,該電容結構係為去耦電容型式。
- 如請求項1所述之電子模組,其中,該第一金屬層電性連接該導線。
- 如請求項1所述之電子模組,其中,該電子元件係具有單一組電源傳輸結構,使該電容結構電性連接該電源傳輸結構。
- 如請求項1所述之電子模組,其中,該電子元件係具有多組電源傳輸結構,使該電容結構電性連接該多組電源傳輸結構。
- 如請求項6所述之電子模組,其中,該第一金屬層係包含相互間隔之複數電性連接部,以令該複數電性連接部分別電性連接不同組之該電源傳輸結構。
- 如請求項7所述之電子模組,其中,該非作用面係於各該電性連接部之間形成有分隔區域,以令該第一金屬層未遮蓋該分隔區域,使該絕緣層形成於該分隔區域上而接觸該非作用面。
- 一種電子封裝件,係包括:承載結構,係具有線路層;以及如請求項1至8之其中一者所述之電子模組,係設於該承載結構上,且該電容結構係電性連接該線路層。
- 如請求項9所述之電子封裝件,復包括電性連接該電子元件之佈線結構。
- 如請求項10所述之電子封裝件,其中,該佈線結構係具有相對之第一表面與第二表面,以令該電子模組配置於該第一表面上,且於該第二表面上配置至少一第二電子元件。
- 如請求項10所述之電子封裝件,其中,該承載結構之線路層與該佈線結構之間係藉由複數導電柱相互電性連接。
- 如請求項9所述之電子封裝件,其中,該承載結構上係形成有複數電性連接該線路層之導電柱。
- 如請求項13所述之電子封裝件,復包括包覆該複數導電柱、電子元件與該電容結構之包覆層。
- 如請求項9所述之電子封裝件,復包括包覆該電子元件與該電容結構之包覆層。
- 一種電子模組之製法,係包括:於一承載件上設置電子元件,其中,該電子元件係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,且該作用面係具有複數電極墊,以令該電子元件以該作用面結合至該承載件上,該電子元件之內部係配置有至少一電性連接該電極墊之導線,以令該導線外露於該電子元件之側面及/或該非作用面;於該電子元件上依序形成第一金屬層、絕緣層及第二金屬層,且該第一金屬層未接觸該第二金屬層,以令該第一金屬層、絕緣層及第二金屬層作為電容結構;以及移除該承載件。
- 如請求項16所述之電子模組之製法,其中,該電容結構係形成於該電子元件之非作用面及/或該側面上。
- 如請求項16所述之電子模組之製法,其中,該電容結構未形成於該電子元件之作用面上。
- 如請求項16所述之電子模組之製法,其中,該電容結構係為去耦電容型式。
- 如請求項16所述之電子模組之製法,其中,該第一金屬層電性連接該導線。
- 如請求項16所述之電子模組之製法,其中,該電子元件係具有單一組電源傳輸結構,使該電容結構電性連接該電源傳輸結構。
- 如請求項16所述之電子模組之製法,其中,該電子元件係具有多組電源傳輸結構,使該電容結構電性連接該多組電源傳輸結構。
- 如請求項22所述之電子模組之製法,其中,該第一金屬層係包含相互間隔之複數電性連接部,以令該複數電性連接部分別電性連接不同組之該電源傳輸結構。
- 如請求項23所述之電子模組之製法,其中,該非作用面係於各該電性連接部之間形成有分隔區域,以令該第一金屬層未遮蓋該分隔區域,使該絕緣層形成於該分隔區域上而接觸該非作用面。
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