201001659 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝基板及其製法，尤指一種嵌 埋有半導體元件之封裝基板及其製法。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a package substrate in which a semiconductor component is embedded and a method of fabricating the same. [Prior Art]
Ik著半導體封裝技術的演進，除了傳統打線式（讲丨 bonding)半導體封裝技術以外，目前半導體裝置 (Semiconductor device)已開發出不同的封裝型態，例如 直接在一封裝基板（packaging substrate)中嵌埋並電性 整合一具有積體電路之半導體晶片，此種 減整體體積並提昇電性功能。 衣了、％ 請參閱第1A至1E圖，係為習知嵌埋有半導體 封裝基板之製法；如第1A圖所示，提供—半導¥體晶曰片片^ 及具有開口 100之承載板10，該半導體晶片u具有作用 面11a，且該作用面lla具有複數電極墊m，萨由 合材料Μ形成於該承載板1〇之開口 1〇〇與半”晶片。 11之間’而將該半導體晶片11固定於開口 100中；如第 1B圖所示’於該半導體晶片11之作用面lla、結合材料 12|?(載板10上形成導電層13，再於導電層m形成 阻層=並於對應該些電極塾ln之位置形成開口區 所示，於該開口區140中之導電層ί3上 電寸大於電極墊lu之凸塊Η，以利於後續製Ik is advancing the semiconductor packaging technology. In addition to the traditional wire-bonding semiconductor packaging technology, semiconductor devices have been developed in different package types, such as directly embedded in a packaging substrate. Buried and electrically integrated a semiconductor wafer with an integrated circuit, which reduces the overall volume and enhances electrical functions. Clothing, % Please refer to Figures 1A to 1E for the conventional method of embedding a semiconductor package substrate; as shown in Figure 1A, a semi-conductive wafer sheet and a carrier plate having an opening 100 are provided. 10, the semiconductor wafer u has an active surface 11a, and the active surface 11a has a plurality of electrode pads m, and the material Μ is formed between the opening 1 〇〇 of the carrier plate 1 and the half "wafer. 11" The semiconductor wafer 11 is fixed in the opening 100; as shown in FIG. 1B, 'the working surface 11a of the semiconductor wafer 11, the bonding material 12|? (the conductive layer 13 is formed on the carrier 10, and the resist layer is formed on the conductive layer m). And forming an open area corresponding to the position of the electrode 塾ln, wherein the conductive layer ί3 in the open area 140 is larger than the bump 电极 of the electrode pad to facilitate subsequent processing.
所覆罢之f接對位，如第1D圖所示，移除該阻層14及其 〜^電層13 ’以顯露該凸塊15及半導體晶月U 110786 5 201001659 γ乍用面na’·如第1E圖所示，於凸塊】 :=二：成增層結構16,該增層結二= 、及形成於:;二設广層 ⑽之導電盲孔163,且連接凸塊15及線路層 性接觸WM，並於該增層結構16 具有複數開孔170以對應顯露電性接觸整Γ 然而’上述封裝結構之箩 兩— 與半導體晶片U之間填入結二材’而錯由在開口 100 n ^ σ材枓以固定半導髀曰y 的門7 ::合材料12尚未固化前存在有流溢出間隙外 T，而增加製程的困難度。此外，亦面 曰、卜 二與不同材料間的結合，而造成不平 問二 如翹曲、脫層或爆板等現象。 的門碭，例 因此’如何避免習知技術中不平衡廡 料而造成流溢等問題，實 '〜A使用結合材 【發明内容】 S已成目則亟欲解決的課題。 鑒於上述習知技術之缺失’本發明之一 種肷埋有半導體元件㈣ ^仏- 料的流溢。 /、衣去，以避免結合材 =明之另—目的係提供—種嵌埋 封農基板及其製法’以避免產生不平衡應力。件之 本發明之再一目的係提供一 導體元件之封農基板及其製法。^積之讀有半 為達上述目的及其他目的’本發明揭露一種嵌埋有半 110786 201001559 .板丰係包括:介電層，係具有相對之第 ，有相對之作田、，半導體晶片，係設於介電層中，且具 -# 、 面及非作用面，該作用面對應介電声之M 、 表面並具有斿盔+枚袖^ 电嘴之弟二 且-第線路層’係設於介電層中， 面;;，面背平；第二線路層，係設於介電層之第二声 且具有位於介電層中之複數導 、 各該電極塾；以及導電通孔，係設=連接 接第-及第二線路層。 丨電層中，以電性連 依上述之結構，該介電層係可由第一、一 電層所組成；該第一線^ _ 弟一及弟三介 成;該第二線二及第二金屬層所組 組成。弟，線路層係可由金屬層、導電層及辅助金屬層所 設於復可包括第1焊㈣ 一開孔，以顯露第一線路層，俾第=可具有複數第 上述之結構中，該封裝基板復可包=電轉觸塾: 设於介電層之第二表面及第二線路層上，且可:方：層，:系 二開孔，以顯露第二線路層，俾-複數第 本發明復提供-種嵌埋有半導電性接觸塾。 製法，係包括：提供-具有相對之第_之封農基板之 層，該第二表面上設有金屬層，且該介:表面之介電 路層及半導體晶片，該第-線路層與該^設有第一線 該半導體晶片具有相對之作用面及非表面齊平，而 應該第二表面且具有複數電 ，該作用面對 蛩於5亥金屬層及該第二表 110786 7 201001659 面上形成有複數介電層開孔，以顯露各該電極墊，並形成 .貫穿金屬層、介電層、及第一線路層之通孔；以及於該第 二表面上形成第二線路層，並於介電層開孔中形成導電盲 J 孔，以電性連接電極墊及第二線路層，且於通孔中形成導 電通孔，以電性連接第一及第二線路層。 上述之製法中，該介電層之製法係可包括：提供一至 少一表面設有離型膜之承載板，且該離型膜上設有第一線 路層；於該第一線路層及離型膜上依序結合第一及第二介 電層，且該第二介電層具有開口以顯露第一介電層；將半 導體晶片結合於開口中之第一介電層上；提供一第三介電 層，其一表面設有金屬層，而另一表面結合於第二介電層 及半導體晶片之作用面上，以使第一、第二及第三介電層 形成介電層，且金屬層設於該第二表面上，而該第一線路 層及半導體晶片設於介電層中；以及移除該離型膜及承載 板，以顯露該第一表面及第一線路層。 上述之製法中，該第一線路層之製法係可包括：於該 i離型膜上形成第一金屬層；於該第一金屬層上形成第一阻 層，並形成第一開口區，以顯露第一金屬層；於該第一開 口區中之第一金屬層上形成第二金屬層；以及移除該第 一阻層及其所覆蓋之第一金屬層，以形成第一線路層。 上述之製法中，該第二線路層之製法係可包括：於該 金屬層上、介電層開孔中、第一表面上、第一線路層上及 通孔中形成導電層；於該金屬層上之導電層上形成第二 阻層，並形成複數第二開口區以顯露金屬層、通孔及介電 8 110786 201001659 層開孔；於導電屛卜 -形成導電盲孔^電性連接電=層’並於介電層開孔中 通孔，以電性連接M 电11 土，且於通孔中形成導電 .之導電層=二層;移除該第二阻層及其覆蓋 屬層，以形成第：線路：夕除位於金屬層上之部份辅助金 層上之輔助移除該第-表面及第-線路 電性連接導電盲孔及導電通孔。s 線路層 二表面及第-線路層 ϊ路層，俾供作為第-電性接觸墊部= 顯露部份第二線路層 :有第—開孔，以 平t、作為第一電性接觸墊。 因此，本發明之嵌埋有半導體 法，係將半導體晶片嵌埋入且古“封裝基板及其製 面之介電層内，相對應之第—及第二表 料，Μ χ〆知技術，本發明無需使用結合材 二==材料造成的流溢問題;另外，嵌埋4 ::於”電層中，可減少不同介面間之結 生不平衡應力。 」避先產 -該nr'r層嵌埋入介電層之第-表面内，並 ^ 卜表面齊平，相較於習 介電層上，本發明可達到縮小體積之目的。路5又於 【實施方式】 、下藉由特定的具體實施例說明本 式，熟悉此技藝之人士可由本說明書所揭示之 110786 9 201001659 瞭解本發明之其他優點及功效。 . 請參閱第2A至2〇圖，係為本發明嵌埋有半導體件 之封裝基板之製法。 ’ 如第2A圖所示，首先，提供一承載板2〇，其表面設 有離型膜201，且離型膜201上設有第一金屬層21&。 如第2B圖所示，於該第一金屬層21a上形成第一阻 層22a，且該第一阻層22a經圖案化製程而形成第一開口 區220a以顯露部份第一金屬層21a;所述之第一金屬層 :21a主要作為後述電鑛金屬所需之電流傳導路徑，其例如 為金屬、合金、沉積數層金屬層等材質；該第—阻層 係為例如乾膜或液態光阻等，其利用印刷、旋塗或貼S合等 方式形成於第一金屬層21a上，再藉由曝光、顯影等方式 加以圖案化，以使該第一阻層22a形成第一開口區22〇心 、如第2C圖所示，藉由該第一金屬層化作為電流傳 導路徑，以於該第一開口區220a中之第一金屬層21a上 電鍍形成第二金屬層21b。 如第2D圖所示，移除該第一阻層22&及盆所覆宴之 第一金屬層2la，以形成由第一金屬層…及第二金^ ib所組成之第一線路層21;所述之第—線路層21之二 =依實際操作之經驗，由於銅為成熟之電鑛材料且成本 乂氐，因此，以電鍍銅較佳，但非以此為限。 上二圖所示，於該第一線路層21及離型膜201 、宜置係為預浸材料（prepreg)之第一及楚一八恭 層23a, 23b，且該第二介電声23b且右龟 丨电層Z扣具有開口 230b，以顯露 110786 10 201001659 该第一介電層23a。 - 如弟2F圖所示，想极一 ia- ^ 知供一丰¥體晶片24,係具有相對 • 〇ΛΊ ± 用面24b，該作用面24a具有複數電 極墊241，且半導體曰μ ^ Μ 曰曰片24之非作用面24b結合於該開 口 230b中之筮—π 2V，日f λ 电θ 23a上；再提供一第三介電層 23c ’且其中一表面設有 於該第二介電層咖及二層曰21。，而另-表面疊置設 电層23b及丰導體晶片24之作用面24a上。 一入：2G圖所不’進行熱壓合’以使該第-、第二及 二23a，23b，23c結合形成具有相對之第一及第 層23之第I2之介電層23,而使金屬層21。設於介電 &中。表面232上’且半導體晶片24嵌埋於介電層 藉由壓合第一、第—铱一 弟一及第二介電層23a，23b，23c，以 .曰曰24無需使用結合材料而直接固定於介電層 題。，相較於習知技術’本發明沒有結合材料流溢的問 另外，該半導體晶片24僅與介電層23接觸，而未與 八载板20接觸，俾使該半導a 2〇結合之作用士 +導體曰曰片24無需考置與承載板 六，、L之作用力，而只需考量與介電層23結合之作用 產生二同介面間結合之影響，而避免不平衡應力所 魅t 2H圖所示’藉由移除該離型膜2Q1而分離該承 〇及介電層23,以顯露該介電層23之第一表面231 弟線路層21’且該第一線路層21嵌埋於該介電層23 110786 11 201001659 ^第表面231内，並與該第一表面231齊平；再於 .屬層21c及介電；μ夕楚_本^。 月十’再於該金 開孔，以對;H弟;^ 232上形成複數介電層 ； 對應頭露各該電極墊241。 藉由第線路層21後埋於介電層23$筮± 内之設計，以使第-線路層21表面與 面曰231齊平，相較於習知技術之線路層設於介電層上1 明頒降低本發明之整體結構高度。 s " :第21圖所示’貫穿該金屬層21。、第一線路層。 及"電層23以形成通孔230b。 θ 如第2J及2J’圖所示’於該金屬層…上 開孔230a之孔壁上、介電層23之第一表面23ι上^層 線路層2i上及通孔雇之孔壁上形成 ㈣屬層21C上之導電層25上形成第二阻層心^ 弟-阻層22b中形成複數第二開口區2咖以顯露通孔 」30b、介電層開孔230a及部份金屬層21〇。 f 接著，以電鑛於該導電層25上形成輔助金屬層21心 ，於該介電層開孔230a中形成導電盲孔261，以電性連接 =電極墊241，且於該通孔230b中形成導電通孔，以 电性連接該第一線路層21;該導電通孔262係為實心（如 第2J圖所示），或中空（如第2J，圖所示）；於本實施例 中，以第2J圖所示之結構作後續說明。 如第2K及2L圖所示’移除該第二阻層2訃及其覆蓋 之導電層25及金屬層2lc，·在移除第二阻層挪所覆罢 之金屬層21C之同時，-併薄化位於其他金屬層仏上: 110786 12 201001659 輔助金屬層21d，以形成由金屬層2ι .，臟組成之第二線路層27 =助 '·表面231及第一線路心上之輔助金屬層21d。於弟一 如第2M及2N圖所示，於 '之第-矣而μ犯 沐浴層、介電層23 之=:==::=’以移除該介電層23 其所覆蓋之導電層25.最曰 之輔助金屬層加及 該第二線路層27電1:二再移除第三阻層22。，以使 =層〜性連接電極#241及第一 ί 如弟20及2〇,圖所示，於該介命厚9q々~ 及第-線路層21上形成第=焊;層：之弟-表面231 面232及第二線路層27上形：=28:，而於該第二表 —防焊層28a中形成第—開孔，方焊層j8b ’ ^於第 路層21，俾供作為第^ 以顯露部份第一線 中…：i 接觸塾2n;於另-實施態樣 ：亦可於弟二防焊層28b中形成第二開孔2 路部：第二線路層27，俾供作為第二電性接觸墊27卜”、 I包括.ΓΓ復提供一種嵌埋有半導體元件之封裝基板，係 二介電，23,係具有相對之第一表面231及第二表 相對之作用導體晶片仏係埋設於介電層23巾，且具有 介電声23之面及非作用面24b，該作用面243對應該 線路二/ 232並具有複數電極塾241，·第- 赢平·\係嵌埋於介電層23中，且與該第一表面如 上日弟二線路層27,係設於介電123之第二表面232 性連接ί有位於介電層23中之複數導電盲孔洲，以電 接各該電極墊2化以及導電通孔咖，係設於介電 110786 13 201001659 層23中，以電性連接第一及第二線路層2ι，27。 • 依上述之結構，該介電層23係由第一、第二及第三 :介電層23a，23b，23cm組成；該第一線路層21:由第: .^第二金屬層叫仙所組成；該第二線路層27係由金 屬層21c、導電層25及輔助金屬層2idm組成。 ^依上述之結構，該封裝基板復包括第一防焊層28a， 係設於該介電層23之第—表面231及第-線路層21上， 且=-防焊層28a具有複數第一開孔，以顯露部 ;伤弟一線路層2卜俾供作為第一電性接觸墊⑴。 迟之、、'。構中，該封裝基板復包括設於 之第二表面232及第二線路芦27上之笛 啄峪層以上之弟二防嬋層28b， 保叙用；若第二線路層27需外接其他電子元件， 防：層28b則需增設複數第二開孔_，以顯露 弟—、、表路層27,俾供作為第二電性接觸塾27卜 制法综^所Γ本發明嵌埋有半導體元件之縣基板及其 (:二=半導體晶片設於介電層中，而無需使用結 。材科，不僅有效達到避免結合材料的流溢之目的，且達 到避免不平衡應力之目的；另 — 層設於介電層中且盥介 》月猎由將第一線路 積之目的。,电層表面背平，以有效達到縮小體 义而上^^施例係用以例示性說日林發明之原理及其功 ^不、^用於^制本發明。任何熟習此項技藝之人士均可 改。因明之精神及範訂，對上述實施例進行修 改因此本發明之權利俘婼 ^ 和保叹靶圍，應如後述之申請專利範 110786 14 201001659 圍所列。 【圖式簡單説明】 第1A至1E圖係顯示習知嵌埋有半導體晶片之封裝基 板之製法的剖視示意圖；以及 第2A至20圖係為本發明嵌埋有半導體晶片之封裝基 板之製法的剖視示意圖；其中，第2Γ圖係為第2J圖之 另一實施態樣，第20’圖係為第20圖之另一實施態樣。 【主要元件符號說明】 10, 20 承載板 100,230b 開口 11, 24 半導體晶片 1 la, 24a 作用面 111,241 電極墊 12 結合材料 13, 25 導電層 14 阻層 140 開口區 15 凸塊 16 增層結構 161,23 介電層 162 線路層 1 63, 261 導電盲孔 164 電性接觸墊 17 防焊層 15 110786 201001659 170 開孔 201 離型膜 21 參 第一線路層 211 第一電性接觸墊 '21a 第一金屬層 21b 第二金屬層 21c 金屬層 21d 輔助金屬層 22a 第一阻層 220a 第一開口區 22b 第二阻層 220b 第二開口區 22c 第三阻層 230a 介電層開孔 230b 通孔 23a 第一介電層 1 23b 第二介電層 23c 第三介電層 231 第一表面 232 第二表面 24b 非作用面 262 導電通孔 27 第二線路層 271 第二電性接觸墊The covered f is aligned, as shown in FIG. 1D, the resist layer 14 and its electrical layer 13' are removed to reveal the bump 15 and the semiconductor crystal moon U 110786 5 201001659 γ乍 surface na' · As shown in FIG. 1E, in the bumps: := two: into the build-up structure 16, the build-up junction two =, and formed in:; two set of conductive holes 163 of the wide layer (10), and the connection bumps 15 And the layer layer contacts the WM, and the layered structure 16 has a plurality of openings 170 corresponding to the exposed electrical contact. However, the two of the above package structures are filled with the junction between the semiconductor wafer and the semiconductor wafer U. It is difficult to increase the process by the overflow of the gap T outside the gate 7 of the opening 100 n ^ σ material to fix the semi-conducting y y :: the material 12 is not yet solidified. In addition, it is also the combination of 曰, 卜 and different materials, which causes unevenness such as warping, delamination or blasting. The threshold, for example, is how to avoid problems such as overflow in the prior art, and the use of bonded materials is practical. In view of the above-mentioned drawbacks of the prior art, one of the present invention is buried with a semiconductor element (four). /, clothing to avoid bonding materials = Mingzhi - the purpose is to provide a kind of embedded sealing substrate and its manufacturing method 'to avoid unbalanced stress. A further object of the present invention is to provide a sealed substrate for a conductor element and a method of making same. There are half of the readings for the above purposes and other purposes. The present invention discloses an embedded semi-110786 201001559. The board system includes: a dielectric layer, which has a relative phase, a relative field, a semiconductor wafer, and a system. It is disposed in the dielectric layer and has -#, surface and non-active surface. The active surface corresponds to the M of the dielectric sound, and the surface has the 斿 helmet + the sleeve ^ the second of the electric mouth and the - the second layer In the dielectric layer, the surface is flat; the second circuit layer is disposed in the second sound of the dielectric layer and has a plurality of conductive electrodes in the dielectric layer, each of the electrodes; and a conductive via. The system is connected to the first and second circuit layers. In the electric layer, electrically connected to the above structure, the dielectric layer may be composed of a first and an electric layer; the first line ^ _ brother and the third three; the second line two and The composition of the two metal layers. The circuit layer may be provided by a metal layer, a conductive layer and an auxiliary metal layer, including a first solder (four), an opening, to expose the first circuit layer, and the second layer may have a plurality of the above structures, the package Substrate reusable package=Electrical switch: It is disposed on the second surface of the dielectric layer and the second circuit layer, and can be: square: layer, two holes are opened to reveal the second circuit layer, 俾-plural Inventive re-providing - a semi-conductive contact crucible is embedded. The method includes: providing a layer having a relatively opposite substrate, wherein the second surface is provided with a metal layer, and the dielectric layer of the surface and the semiconductor wafer, the first circuit layer and the Providing a first line, the semiconductor wafer has a relatively active surface and a non-surface flush, and should have a second surface and have a plurality of electricity, the effect facing the 5 ohm metal layer and the second surface 110786 7 201001659 Forming a plurality of dielectric layer openings to expose each of the electrode pads, and forming a through hole penetrating through the metal layer, the dielectric layer, and the first circuit layer; and forming a second circuit layer on the second surface, and A conductive blind J hole is formed in the opening of the dielectric layer to electrically connect the electrode pad and the second circuit layer, and a conductive via hole is formed in the through hole to electrically connect the first and second circuit layers. In the above method, the method for manufacturing the dielectric layer may include: providing a carrier plate having at least one surface provided with a release film, and the release film is provided with a first circuit layer; The first and second dielectric layers are sequentially bonded to the film, and the second dielectric layer has an opening to expose the first dielectric layer; the semiconductor wafer is bonded to the first dielectric layer in the opening; a three-dielectric layer, one surface of which is provided with a metal layer, and the other surface is bonded to the second dielectric layer and the active surface of the semiconductor wafer, so that the first, second and third dielectric layers form a dielectric layer. And the metal layer is disposed on the second surface, and the first circuit layer and the semiconductor wafer are disposed in the dielectric layer; and the release film and the carrier plate are removed to expose the first surface and the first circuit layer. In the above method, the first circuit layer can be formed by: forming a first metal layer on the i-type film; forming a first resist layer on the first metal layer, and forming a first opening region, Forming a first metal layer; forming a second metal layer on the first metal layer in the first opening region; and removing the first resist layer and the first metal layer covered thereby to form a first wiring layer. In the above method, the second circuit layer manufacturing method may include: forming a conductive layer on the metal layer, in the opening of the dielectric layer, on the first surface, on the first circuit layer, and in the via hole; Forming a second resist layer on the conductive layer on the layer, and forming a plurality of second open regions to expose the metal layer, the via hole and the dielectric layer 8 110786 201001659 layer opening; and forming a conductive blind hole ^ electrically connected to the conductive layer = layer 'and through holes in the opening of the dielectric layer to electrically connect the M electric 11 soil, and form a conductive layer in the through hole = the second layer; remove the second resist layer and its cover layer And forming a first: line: removing the auxiliary surface of the metal layer to assist the removal of the first surface and the first line electrically connecting the conductive blind hole and the conductive via. s circuit layer two surface and first-line layer road layer, 俾 supply as the first electrical contact pad part = reveal part of the second circuit layer: there is a first opening, to flat t, as the first electrical contact pad . Therefore, the embedded semiconductor method of the present invention embeds a semiconductor wafer into the dielectric layer of the package substrate and its surface, corresponding to the first and second materials, and the known technology. The invention does not need to use the overflow problem caused by the bonding material 2 == material; in addition, the embedded 4: in the "electric layer" can reduce the unbalanced stress between different interfaces. The first nr'r layer is embedded in the first surface of the dielectric layer, and the surface is flush. Compared with the conventional dielectric layer, the present invention can achieve the purpose of reducing the volume. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Referring to Figures 2A to 2, it is a method of fabricating a package substrate in which a semiconductor device is embedded. As shown in Fig. 2A, first, a carrier sheet 2 is provided, the surface of which is provided with a release film 201, and the release film 201 is provided with a first metal layer 21 & As shown in FIG. 2B, a first resist layer 22a is formed on the first metal layer 21a, and the first resist layer 22a is patterned to form a first open region 220a to expose a portion of the first metal layer 21a; The first metal layer: 21a is mainly used as a current conduction path required for an electric ore metal to be described later, and is, for example, a metal, an alloy, or a deposited metal layer; the first resist layer is, for example, a dry film or a liquid light. Blocking or the like, which is formed on the first metal layer 21a by printing, spin coating or S bonding, and then patterned by exposure, development, etc., so that the first resist layer 22a forms the first opening region 22 As shown in FIG. 2C, the first metal layer is formed as a current conduction path to form a second metal layer 21b on the first metal layer 21a in the first opening region 220a. As shown in FIG. 2D, the first resist layer 22& and the first metal layer 2la of the pot are removed to form the first circuit layer 21 composed of the first metal layer and the second metal ib. The second layer of the circuit layer 21 = according to the actual operation experience, since copper is a mature electric ore material and the cost is low, it is preferable to use electroplated copper, but not limited thereto. As shown in the above two figures, the first circuit layer 21 and the release film 201 are preferably the first prepreg and the second layer 23a, 23b, and the second dielectric sound 23b. And the right turtle layer Z buckle has an opening 230b to expose the first dielectric layer 23a of 110786 10 201001659. - As shown in Fig. 2F, I want to have a ii-^ knowing the supply of the wafer 24, which has a relative 〇ΛΊ± surface 24b, the active surface 24a has a plurality of electrode pads 241, and the semiconductor 曰μ ^ Μ The non-active surface 24b of the cymbal 24 is bonded to the 230-π 2V, the day f λ θ 23a in the opening 230b; a third dielectric layer 23c' is further provided and one of the surfaces is disposed on the second dielectric The electric layer coffee and the second floor are 21. The other surface is stacked on the active surface 23b and the active surface 24a of the abundance conductor wafer 24. One entry: the 2G diagram does not 'hot press fit' to combine the first, second and second 23a, 23b, 23c to form the dielectric layer 23 having the first and the second layer 23 of the first layer 23, Metal layer 21. Located in Dielectric & On the surface 232' and the semiconductor wafer 24 is embedded in the dielectric layer by pressing the first, first and second dielectric layers 23a, 23b, 23c, so that the bonding material is not directly used. Fixed to the dielectric layer. In contrast to the prior art, the present invention does not have a material overflow. In addition, the semiconductor wafer 24 is only in contact with the dielectric layer 23, and is not in contact with the eight carrier 20, so that the semiconducting a 2 〇 is combined. The conductor + conductor cymbal 24 does not need to be tested and the force of the carrier plate six, L, but only consider the combination of the dielectric layer 23 to produce the effect of the combination between the two interfaces, and avoid the unbalanced stress 2H shows that the carrier and dielectric layer 23 are separated by removing the release film 2Q1 to expose the first surface 231 of the dielectric layer 23 and the first circuit layer 21 is embedded. Buried in the dielectric layer 23 110786 11 201001659 ^ in the surface 231, and flush with the first surface 231; and then the layer 21c and dielectric; μ Xi Chu _ this ^. The tenth month is further opened in the gold, to form a plurality of dielectric layers on the H; 232; the corresponding electrode pads 241 are exposed. The surface of the first circuit layer 21 is flush with the surface layer 231 by the design of the first circuit layer 21 and buried in the dielectric layer 23, which is disposed on the dielectric layer compared with the conventional circuit layer. 1 The invention reduces the overall structural height of the present invention. s " : shown in Fig. 21 'through the metal layer 21. , the first circuit layer. And " electrical layer 23 to form vias 230b. θ is formed on the hole wall of the opening 230a of the metal layer, on the first surface 23 of the dielectric layer 23, on the circuit layer 2i, and on the hole wall of the through hole as shown in the 2J and 2J'. (4) forming a second resist layer on the conductive layer 25 on the genus layer 21C. The second open region 2 is formed in the resist layer 22b to expose the via hole 30b, the dielectric layer opening 230a and the partial metal layer 21 Hey. f, the auxiliary metal layer 21 is formed on the conductive layer 25 by electric ore, and a conductive blind hole 261 is formed in the dielectric layer opening 230a to electrically connect the = electrode pad 241, and in the through hole 230b Forming conductive vias to electrically connect the first circuit layer 21; the conductive vias 262 are solid (as shown in FIG. 2J), or hollow (as shown in FIG. 2J); in this embodiment The structure shown in Fig. 2J will be described later. As shown in FIGS. 2K and 2L, 'the second resist layer 2 and its covered conductive layer 25 and metal layer 2lc are removed, and while the second resist layer is removed, the metal layer 21C is removed. And thinning on the other metal layer :: 110786 12 201001659 Auxiliary metal layer 21d to form a second circuit layer 27 composed of a metal layer 2, dirty, a surface 231 and an auxiliary metal layer on the first line core 21d. As shown in the 2M and 2N diagrams, Yu Di's first layer of the bath layer and the dielectric layer 23 =:==::=' to remove the conductive layer covered by the dielectric layer 23. Layer 25. The last auxiliary metal layer is applied to the second circuit layer 27. The third resist layer 22 is removed. In order to make the = layer-to-sex connection electrode #241 and the first ί, such as 20 and 2, as shown in the figure, the first welding is formed on the dielectric layer 9q々~ and the first-line layer 21; - surface 231 surface 232 and second circuit layer 27 are shaped: = 28:, and the first surface - the solder mask layer 28a is formed with a first opening, the square solder layer j8b ' ^ at the second layer 21, As the second part, the first line is exposed...:i contact 塾2n; in another embodiment: the second opening 2 can also be formed in the second solder mask 28b: the second circuit layer 27, The second electrical contact pad 27 is provided as a second electrical contact pad. The package includes a semiconductor substrate embedded with a semiconductor component, and has a dielectric layer opposite to the first surface 231 and the second surface. The active conductor chip is embedded in the dielectric layer 23 and has a surface of the dielectric sound 23 and an inactive surface 24b. The active surface 243 corresponds to the line 2/232 and has a plurality of electrodes 241, · - win - The system is embedded in the dielectric layer 23, and is connected to the first surface of the second surface layer 27, and is connected to the second surface of the dielectric 123. The plurality of conductive blinds are located in the dielectric layer 23. The first and second circuit layers 2, 27 are electrically connected to each of the electrode pads 2 and the conductive vias, and are electrically connected to the first and second circuit layers 2, 27 according to the above structure. The dielectric layer 23 is composed of first, second and third dielectric layers 23a, 23b, 23cm; the first circuit layer 21 is composed of: a second metal layer called a fairy; the second The circuit layer 27 is composed of a metal layer 21c, a conductive layer 25 and an auxiliary metal layer 2idm. According to the above structure, the package substrate further includes a first solder resist layer 28a disposed on the first surface 231 of the dielectric layer 23. And on the first-line layer 21, and the -- solder resist layer 28a has a plurality of first openings to expose the portion; the wounded first circuit layer 2 is provided as the first electrical contact pad (1). In the structure, the package substrate includes a second layer 232 and a second layer of the second layer 232 and the second line of the reed layer 27b, which are used for the protection; if the second circuit layer 27 needs to be externally connected to other electrons Component, prevention: layer 28b needs to add a plurality of second openings _ to reveal the brother-,, surface layer 27, 俾 for the second electrical contact 塾 27 method According to the invention, the county substrate in which the semiconductor element is embedded and the semiconductor chip are disposed in the dielectric layer without using a junction. The material is not only effective for avoiding the overflow of the bonding material, but also avoiding The purpose of unbalanced stress; the other layer is set in the dielectric layer and the shovel is used for the purpose of the first line. The surface of the electric layer is flattened to effectively reduce the body and the upper part. The invention is exemplified by the principles of the invention and its functions, and can be modified by anyone skilled in the art. The above embodiments are modified in light of the spirit and scope of the present invention. Therefore, the right captives of the present invention and the sling target should be as described in the patent application No. 110786 14 201001659, which will be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are schematic cross-sectional views showing a conventional method of manufacturing a package substrate in which a semiconductor wafer is embedded; and FIGS. 2A to 20 are a method of manufacturing a package substrate in which a semiconductor wafer is embedded in the present invention. FIG. 2 is a cross-sectional view of the second embodiment of FIG. 2, and FIG. 20' is another embodiment of FIG. [Main component symbol description] 10, 20 carrier plate 100, 230b opening 11, 24 semiconductor wafer 1 la, 24a active surface 111, 241 electrode pad 12 bonding material 13, 25 conductive layer 14 resist layer 140 open region 15 bump 16 buildup structure 161 , 23 dielectric layer 162 circuit layer 1 63, 261 conductive blind hole 164 electrical contact pad 17 solder mask 15 110786 201001659 170 opening 201 release film 21 reference first circuit layer 211 first electrical contact pad '21a a metal layer 21b second metal layer 21c metal layer 21d auxiliary metal layer 22a first resistive layer 220a first open region 22b second resistive layer 220b second open region 22c third resistive layer 230a dielectric layer opening 230b via 23a First dielectric layer 1 23b second dielectric layer 23c third dielectric layer 231 first surface 232 second surface 24b non-active surface 262 conductive via 27 second wiring layer 271 second electrical contact pad
201001659 28a 第 一防焊層 280a 第 一開孔 28b • 第 二防焊層 280b 第 二開孑L201001659 28a First solder mask 280a first opening 28b • second solder mask 280b second opening L