CN103903990A - Preparation method for electronic component package - Google Patents
Preparation method for electronic component package Download PDFInfo
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- CN103903990A CN103903990A CN201210585109.7A CN201210585109A CN103903990A CN 103903990 A CN103903990 A CN 103903990A CN 201210585109 A CN201210585109 A CN 201210585109A CN 103903990 A CN103903990 A CN 103903990A
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- dielectric layer
- layer
- electronic building
- building brick
- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
A preparation method for an electronic component package comprises the following steps: providing a bearing plate, wherein a first metal layer is formed on one surface of the bearing plate; forming a first dielectric layer on the first metal layer; forming a second metal layer on the first dielectric layer and patterning the second metal layer to expose the first dielectric layer; forming at least one opening penetrating through the first dielectric layer in the first dielectric layer to expose part of the first metal layer; arranging at least one electronic component in the opening; forming a second dielectric layer on the first dielectric layer and the electronic component; forming a plurality of blind holes penetrating through the second dielectric layer and exposing the electronic component in the second dielectric layer; forming a circuit layer electrically connected with the electrical component on the second dielectric layer and in the blind holes; and removing the bearing plate. By adopting the method of the invention, the overall thickness of the electronic component package can be reduced, and the cost of the preparation process can be lowered.
Description
Technical field
The present invention relates to a kind of method for making of electronic building brick encapsulation, espespecially a kind of method for making of the electronic building brick encapsulation that reduces electronic building brick package thickness.
Background technology
During science and technology is just promptly flourish, electronic product development trend is towards compact direction by product, then continually develop and can catch up with the manufacturing technology of the electronic building brick encapsulation of scientific and technological trend step now, and use in order to make electronic building brick encapsulation do more effective space, still constantly improve the process technique of electronic building brick encapsulation.
Refer to Figure 1A to Fig. 1 H, it is the cross-sectional schematic of the method for making of existing electronic building brick encapsulation.
As shown in Figure 1A, provide a core board 10, and be formed with conductive metal layer 10a on this core board 10, and this conductive metal layer 10a to be formed at two surfaces of this core board 10 upper, and this core board 10 has relative first surface 101 and second surface 102.
As shown in Figure 1B, in this core board 10, be provided with the through hole 103 that runs through this first surface 101 and this second surface 102.
As shown in Figure 1 C, this conductive metal layer of patterning 10a to form the first line layer 11, and forms conductive through hole 104 in this through hole 103.
As shown in Fig. 1 D, utilize laser burn mode to be formed with to run through the opening 105 of this first surface 101 and this second surface 102 in these core board 10 central authorities.
As shown in Fig. 1 E, one electronic building brick 12 is arranged in this opening 105, and on this first surface 101, form the first dielectric layer 13, and on this first dielectric layer 13, also form the first metal layer 13a, in addition, on this second surface 102, form again the second dielectric layer 14, and on this second dielectric layer 14, also form the second metal level 14a.
As shown in Fig. 1 F, be formed with and multiplely run through this first dielectric layer 13 with this first metal layer 13a and expose this electronic building brick 12 and the first blind hole 15 of this first line layer 11 of part, then, then be formed with multiple the second blind holes 16 that run through this second dielectric layer 14 and this second metal level 14a and expose this first line layer 11 of part.
As shown in Figure 1 G, this the first metal layer of patterning 13a, to form the second line layer 17, and form the first conductive blind hole 151 and the second conductive blind hole 161 in this first blind hole 15 and the second blind hole 16, this first conductive blind hole 151 of part is electrically connected this electronic building brick 12.
As shown in Fig. 1 H; on this first dielectric layer 13, the second dielectric layer 14 and the second line layer 17, form insulating protective layer 18; and be formed with the insulating protective layer perforate 181 of this second line layer 17 of multiple exposed parts, in addition, on the exposed surface of this second line layer 17, form surface-treated layer 19.
But aforementioned existing method for making only can form the electronic building brick encapsulation of the layer reinforced structure of tool symmetry and 4 sandwich circuit layers, therefore, overall structure thickness is thicker.
Therefore, how overcoming the problem of prior art, make product be tending towards thinning, is an important topic in fact.
Summary of the invention
For solving the problem of above-mentioned prior art, main purpose of the present invention is to disclose a kind of method for making of electronic building brick encapsulation, can reduce the integral thickness of this electronic building brick encapsulation, and then reduces processing procedure cost.
The method for making of electronic building brick encapsulation of the present invention, comprising: a loading plate is provided, is formed with the first metal layer in surface thereof; On this first metal layer, form the first dielectric layer; On this first dielectric layer, form the second metal level, and this second metal level of patterning, to expose this first dielectric layer; In this first dielectric layer, be formed with at least one opening that runs through this first dielectric layer, with this first metal layer of exposed parts; At least one electronic building brick is set in this opening; On this first dielectric layer with on this electronic building brick, form the second dielectric layer; In this second dielectric layer, be formed with multiple blind holes that run through this second dielectric layer and expose this electronic building brick; On this second dielectric layer with described blind hole, form the line layer that is electrically connected this electronic building brick; And remove this loading plate.
The present invention also provides a kind of method for making of electronic building brick encapsulation, comprising: a loading plate is provided, is formed with the first metal layer in surface thereof; On this first metal layer, form the first dielectric layer; On this first dielectric layer, form the second metal level, and this second metal level of patterning, to expose this first dielectric layer; In this first dielectric layer, be formed with at least one opening that runs through this first dielectric layer, with this first metal layer of exposed parts; At least one electronic building brick is set in this opening; On this first dielectric layer and this electronic building brick, form the second dielectric layer; Remove this loading plate; In this second dielectric layer, form multiple the first blind holes that run through this second dielectric layer and expose this electronic building brick; And form the first line layer that is electrically connected this electronic building brick on this second dielectric layer with described the first blind hole, and this first metal layer of patterning is to form the second line layer.
From the above mentioned, because the present invention can reduce this electronic building brick and encapsulate the number of plies of overall line layer, for instance, the number of plies of line layer is odd number layer as one deck or three layers, therefore, form tool symmetric layer reinforced structure line layer by technology of the present invention by improving the number of plies that prior art encapsulates overall line layer at this electronic building brick, so the number of plies of line layer of the present invention is less, thickness attenuation for this electronic building brick encapsulation of entirety, and then reduce production costs.
Accompanying drawing explanation
Figure 1A to Fig. 1 H is the cross-sectional schematic of the method for making of existing electronic building brick encapsulation.
Fig. 2 A to Fig. 2 M is the generalized section of the first embodiment of the method for making of electronic building brick encapsulation of the present invention.
Fig. 3 A to Fig. 3 O is the generalized section of the second embodiment of the method for making of electronic building brick encapsulation of the present invention.
Fig. 4 A to Fig. 4 M is the generalized section of the 3rd embodiment of the method for making of electronic building brick encapsulation of the present invention.
Fig. 5 A to Fig. 5 M is the generalized section of the 4th embodiment of the method for making of electronic building brick encapsulation of the present invention.
Fig. 6 A is the schematic diagram of the different embodiment of the electronic building brick of electronic building brick encapsulation of the present invention from Fig. 6 B.
Primary clustering symbol description
10 core boards
10a conductive metal layer
101 first surfaces
102 second surfaces
103,531 through holes
104,333 conductive through holes
105 openings
11,44,54 first line layers
12,22,32,42,52 electronic building bricks
13 first dielectric layers
13a, 20a, 30a, 40a, 50a the first metal layer
14,23,33,43,53 second dielectric layers
14a, 21a, 31a, 41a, 51a the second metal level
15,430 first blind holes
151,431 first conductive blind holes
16,412 second blind holes
161,413 second conductive blind holes
17,45,55 second line layers
18,25,35 insulating protective layers
181,251,351 insulating protective layer perforates
19,26,36 surface-treated layers
20,30,40,50 loading plates
201,301,401,501 base materials
202,302,402,502 base material dielectric layers
21,31,41,51 first dielectric layers
211,311,411,511 openings
23a, 33a, 43a, 53a the 3rd metal level
230,330,530 blind holes
231,332,532 conductive blind holes
24,34 line layers
30b electric connection pad
331 through holes
41b tertiary circuit layer
46,56 first insulating protective layers
461,561 first insulating protective layer perforates
47,57 second insulating protective layers
471,571 second insulating protective layer perforates
48,58 first surface processing layers
49,59 second surface processing layers
533 conductive through holes
60 monolithic ceramic capacitors
601,611 electronic padses
61 chips.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those of ordinary skill in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, structure that the appended accompanying drawing of this specification illustrates, ratio, size etc., all contents in order to coordinate specification to disclose only, for those skilled in the art's understanding and reading, not in order to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, in this specification, quote as " on ", the term such as " side ", " ", " two " and " top ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, changing under technology contents, when being also considered as the enforceable category of the present invention without essence.
The first embodiment
As Fig. 2 A to Fig. 2 M those shown, it is the generalized section of the first embodiment of the method for making of electronic building brick encapsulation of the present invention.
As shown in Figure 2 A, provide a loading plate 20, it comprises stacked base material 201 and base material dielectric layer 202, and relative two surfaces of this base material 201 can have metal level (not icon).
As shown in Figure 2 B, on this base material dielectric layer 202, form the first metal layer 20a.
As shown in Figure 2 C, on this first metal layer 20a, form the first dielectric layer 21, and on this first dielectric layer 21, also form the second metal level 21a.
As shown in Figure 2 D, in this first dielectric layer 21, form and at least always wear the opening 211 of this first dielectric layer 21 and the second metal level 21a, with this first metal layer of exposed parts 20a, and the mode that forms this opening 211 is laser burn.
As shown in Figure 2 E, at least one electronic building brick 22 is set in this opening 211, wherein, this electronic building brick 22 is driving component or passive component, and this passive component can be monolithic ceramic capacitor (Multi-layer Ceramic Capacitor is called for short MLCC), but not as limit.
As shown in Figure 2 F, remove this second metal level 21a, and the mode that removes this second metal level 21a can be etching, but not as limit, make the end face of this first dielectric layer 21 expose and flush with the end face of this electronic building brick 22.
As shown in Figure 2 G, on this first dielectric layer 21 with on this electronic building brick 22, form the second dielectric layer 23, then form the 3rd metal level 23a on this second dielectric layer 23.
As shown in Fig. 2 H, in this second dielectric layer 23, be formed with multiple blind holes 230 that run through this second dielectric layer 23 and the 3rd metal level 23a, to expose the end face of this electronic building brick 22, in addition, the mode that forms this blind hole 230 can be laser burn, but not as limit.
As shown in Fig. 2 I, on the end face of this electronic building brick 22 with this blind hole 230, form the conductive blind hole 231 that is electrically connected this electronic building brick 22.
As shown in Fig. 2 J, the 3rd metal level 23a on this second dielectric layer 23 of patterning, to form line layer 24.
As shown in Fig. 2 K, on this second dielectric layer 23 and this line layer 24, form insulating protective layer 25, and be formed with the insulating protective layer perforate 251 of this line layer 24 of multiple exposed parts.
As shown in Fig. 2 L, on this line layer 24 exposing, form surface-treated layer 26.
As shown in Fig. 2 M, finally remove this loading plate 20.
The second embodiment
As Fig. 3 A to Fig. 3 O those shown, it is the generalized section of the second embodiment of the method for making of electronic building brick of the present invention encapsulation.
As shown in Figure 3A, provide a loading plate 30, it comprises stacked base material 301 and base material dielectric layer 302, and relative two surfaces of this base material 301 can have metal level (not icon).
As shown in Figure 3 B, on this base material dielectric layer 302, form the first metal layer 30a.
As shown in Figure 3 C, on this first metal layer 30a, form multiple electric connection pad 30b.
As shown in Figure 3 D, on this first metal layer 30a and described electric connection pad 30b, form the first dielectric layer 31, and form the second metal level 31a on this first dielectric layer 31.
As shown in Fig. 3 E, form the opening 311 of at least always wearing this first dielectric layer 31 and the second metal level 31a, with this electric connection pad of exposed parts 30b, in addition, the mode that forms this opening 311 can be laser burn, but not as limit.
As shown in Fig. 3 F, at least one electronic building brick 32 is set in this opening 311, and this electronic building brick 32 is located on this electric connection pad 30b.
As shown in Fig. 3 G, remove this second metal level 31a, and the mode that removes this second metal level 31a can be etching, but not as limit.
As shown in Fig. 3 H, on this first dielectric layer 31 and this electronic building brick 32, form the second dielectric layer 33, then form the 3rd metal level 33a on this second dielectric layer 33.
As shown in Fig. 3 I, form multiple blind holes 330 that run through this second dielectric layer 33 and the 3rd metal level 33a, to expose the end face of this electronic building brick 32, in addition, the mode that forms this blind hole 330 can be laser burn, but not as limit, then, form multiple at least one through holes 331 that run through this first dielectric layer 31, the second dielectric layer 33 and the 3rd metal level 33a, and this through hole 331 is to should electric connection pad 30b, to expose the end face of this electric connection pad 30b.
As shown in Fig. 3 J, on the end face of this electronic building brick 32 and this electric connection pad of part 30b and in this blind hole 330 and this through hole 331, form metal material, to form the conductive blind hole 332 that is electrically connected this electronic building brick 32 on this second dielectric layer 33 with described blind hole 330, and form the conductive through hole 333 that is electrically connected this electric connection pad 30b on this first dielectric layer 31 and this second dielectric layer 33 and in this through hole 331.
As shown in Fig. 3 K, the 3rd metal level 33a on this second dielectric layer 33 of patterning, to form line layer 34, and this second dielectric layer 33 of exposed parts.
As shown in Fig. 3 L, on this second dielectric layer 33 and this line layer 34, form insulating protective layer 35, and form the insulating protective layer perforate 351 of this line layer 34 of multiple exposed parts.
As shown in Fig. 3 M, on this line layer 34 exposing, form surface-treated layer 36.
As shown in Fig. 3 N, then remove this loading plate 30.
As shown in Fig. 3 O, finally remove the first metal layer 30a on this loading plate 30, and the mode that removes this first metal layer 30a can be etching, but not as limit.
The 3rd embodiment
As Fig. 4 A to Fig. 4 M those shown, it is the generalized section of the 3rd embodiment of the method for making of electronic building brick of the present invention encapsulation.
As shown in Figure 4 A, provide a loading plate 40, it comprises stacked base material 401 and base material dielectric layer 402, and relative two surfaces of this base material 401 can have metal level (not icon).
As shown in Figure 4 B, on this base material dielectric layer 402, form the first metal layer 40a.
As shown in Figure 4 C, on this first metal layer 40a, form the first dielectric layer 41, and on this first dielectric layer 41, form the second metal level 41a.
As shown in Figure 4 D, this second metal level of patterning 41a, to expose the first dielectric layer 41, and this second metal level 41a after patterning forms tertiary circuit layer 41b.
As shown in Figure 4 E, form the opening 411 of at least always wearing this first dielectric layer 41, with this first metal layer of exposed parts 40a, in addition, the mode that forms this opening 411 can be laser burn, but not as limit.
As shown in Fig. 4 F, at least one electronic building brick 42 is set in this opening 411, and this electronic building brick 42 is located on this first metal layer 40a, in addition, this electronic building brick 42 is driving component or passive component, and this passive component can be monolithic ceramic capacitor (Multi-layer CeramicCapacitor is called for short MLCC), but not as limit.
As shown in Figure 4 G, on this first dielectric layer 41, electronic building brick 42 and tertiary circuit layer 41b, form the second dielectric layer 43, then form the 3rd metal level 43a on this second dielectric layer 43.
As shown in Fig. 4 H, remove this loading plate 40.
As shown in Fig. 4 I, form multiple the first blind holes 430 that run through this second dielectric layer 43 and the 3rd metal level 43a, and expose the end face and this tertiary circuit layer of part 41b of this electronic building brick 42, in addition, the mode that forms this first blind hole 430 can be laser burn, but not as limit.
Then, form multiple the second blind holes 412 that run through this first dielectric layer 41 and the first metal layer 40a, and this tertiary circuit layer of exposed parts 41b.
As shown in Fig. 4 J, on the end face of this electronic building brick 42 and this tertiary circuit layer of part 41b and form metal material in this first blind hole 430 and the second blind hole 412, on this second dielectric layer 43 with this first blind hole 430, form the first conductive blind hole 431 that is electrically connected this electronic building brick 42, and form the second conductive blind hole 413 that is electrically connected this tertiary circuit layer 41b in this first dielectric layer 41 and this second blind hole 412.
As shown in Figure 4 K, the 3rd metal level 43a on this second dielectric layer 43 of patterning, to form the first line layer 44, and this second dielectric layer 43 of exposed parts, and this first line layer 44 is also electrically connected this tertiary circuit layer 41b.
In addition, the first metal layer 40a on this first dielectric layer 41 of patterning, to form the second line layer 45, and this first dielectric layer 41 of exposed parts.
As shown in Fig. 4 L; on this second dielectric layer 43 and this first line layer 44, form the first insulating protective layer 46; and be formed with the first insulating protective layer perforate 461 of this first line layer 44 of multiple exposed parts; in addition; on this first dielectric layer 41 and this second line layer 45, form the second insulating protective layer 47, and be formed with the second insulating protective layer perforate 471 of this second line layer 45 of multiple exposed parts.
As shown in Fig. 4 M, on this first line layer 44 exposing, form first surface processing layer 48, separately on this second line layer 45 exposing, form again second surface processing layer 49.
The 4th embodiment
As Fig. 5 A to Fig. 5 M those shown, it is the generalized section of the 4th embodiment of the method for making of electronic building brick of the present invention encapsulation.
As shown in Figure 5A, provide a loading plate 50, it comprises stacked base material 501 and base material dielectric layer 502, and relative two surfaces of this base material 501 can have metal level (not icon).
As shown in Figure 5 B, on this base material dielectric layer 502, form the first metal layer 50a.
As shown in Figure 5 C, on this first metal layer 50a, form the first dielectric layer 51, and on this first dielectric layer 51, form the second metal level 51a.
As shown in Figure 5 D, form the opening 511 of at least always wearing this first dielectric layer 51 and this second metal level 51a, with this first metal layer of exposed parts 50a, in addition, the mode that forms this opening 511 can be laser burn, but not as limit.
As shown in Fig. 5 E, at least one electronic building brick 52 is set in this opening 511, and this electronic building brick 52 is located on this first metal layer 50a.
As shown in Fig. 5 F, remove this second metal level 51a, and the mode that removes this second metal level 51a can be etching, but not as limit, and expose the end face of this first dielectric layer 51.
As shown in Fig. 5 G, on this first dielectric layer 51 and electronic building brick 52, form the second dielectric layer 53, then form the 3rd metal level 53a on this second dielectric layer 53.
As shown in Fig. 5 H, remove this loading plate 50.
As shown in Fig. 5 I, form multiple blind holes 530 that run through this second dielectric layer 53 and the 3rd metal level 53a, and expose the end face of this electronic building brick 52, in addition, the mode that forms this blind hole 530 can be laser burn, but not as limit.
In addition, form multiple through holes 531 that run through this first dielectric layer 51, the second dielectric layer 53, the second metal level 51a and the 3rd metal level 53a.
As shown in Fig. 5 J, in the end face of this electronic building brick 52 and this blind hole 530, form metal material with the sidewall of this through hole 531, to form and be electrically connected the conductive blind hole 532 of this electronic building brick 52 on this second dielectric layer 53 with described blind hole 530, and on this first dielectric layer 51 and this second dielectric layer 53 and form conductive through hole 533 in this through hole 531.
As shown in Fig. 5 K, the 3rd metal level 53a on this second dielectric layer 53 of patterning, to form the first line layer 54, and this second dielectric layer 53 of exposed parts.
As shown in Fig. 5 L; on this second dielectric layer 53 and this first line layer 54, form the first insulating protective layer 56; and form the first insulating protective layer perforate 561 of this first line layer 54 of multiple exposed parts; in addition; on this first dielectric layer 51 and this second line layer 55, form the second insulating protective layer 57, and form the second insulating protective layer perforate 571 of this second line layer 55 of multiple exposed parts.
As shown in Fig. 5 M, on this first line layer 54 exposing, form first surface processing layer 58, separately on this second line layer 55 exposing, form again second surface processing layer 59.
In addition, the schematic diagram of the different embodiment of the electronic building brick of electronic building brick encapsulation of the present invention is as shown in Fig. 6 A and Fig. 6 B, the first embodiment monolithic ceramic capacitor (MLCC) 60 as shown in Figure 6A, and on the sidewall of this monolithic ceramic capacitor 60, there is electronic pads 601; The second embodiment chip 61 as shown in Figure 6B, and on the surface of this chip 61, there are multiple electronic padses 611.
In sum, because the method for making of electronic building brick encapsulation of the present invention can form the electronic building brick encapsulation that is provided with electronic building brick with double-deck circuit or odd-level circuit, therefore the thinner thickness of overall electronic building brick encapsulation of the present invention, and processing procedure of the present invention has elasticity, in addition, method for making of the present invention is also comparatively simple, and then can reduce production costs.
Above-mentioned these embodiment are illustrative effect of the present invention only, but not for limiting the present invention, any those skilled in the art all can, under spirit of the present invention and category, modify and change above-mentioned these embodiment.In addition, the quantity of the assembly in above-mentioned these embodiment is only illustrative, also non-for limiting the present invention.Therefore the scope of the present invention, should be as listed in claims.
Claims (13)
1. a method for making for electronic building brick encapsulation, it comprises:
One loading plate is provided, in surface thereof, is formed with the first metal layer;
On this first metal layer, form the first dielectric layer;
On this first dielectric layer, form the second metal level, and this second metal level of patterning, to expose this first dielectric layer;
In this first dielectric layer, be formed with at least one opening that runs through this first dielectric layer, with this first metal layer of exposed parts;
At least one electronic building brick is set in this opening;
On this first dielectric layer with on this electronic building brick, form the second dielectric layer;
In this second dielectric layer, be formed with multiple blind holes that run through this second dielectric layer and expose this electronic building brick;
On this second dielectric layer with described blind hole, form the line layer that is electrically connected this electronic building brick; And
Remove this loading plate.
2. the method for making of electronic building brick encapsulation according to claim 1, is characterized in that, is also included in and arranges after this electronic building brick, removes this second metal level.
3. the method for making of electronic building brick encapsulation according to claim 1, it is characterized in that, forming after this second dielectric layer, also be included in and on this second dielectric layer, form the 3rd metal level, this blind hole also runs through the 3rd metal level, and in this blind hole, form metal material and patterning the 3rd metal level, to form this line layer.
4. the method for making of electronic building brick encapsulation according to claim 1, it is characterized in that, forming before this first dielectric layer, be also included in and on this first metal layer, form multiple electric connection pads, and on this first metal layer and electric connection pad, form this first dielectric layer.
5. the method for making of electronic building brick encapsulation according to claim 4, is characterized in that, this electronic building brick is located on this electric connection pad.
6. the method for making of electronic building brick according to claim 1 encapsulation, is characterized in that, form this blind hole and also comprise forming and multiplely run through this first dielectric layer and this second dielectric layer and to through hole that should electric connection pad, and this line layer is also formed in this through hole.
7. a method for making for electronic building brick encapsulation, it comprises:
One loading plate is provided, in surface thereof, is formed with the first metal layer;
On this first metal layer, form the first dielectric layer;
On this first dielectric layer, form the second metal level, and this second metal level of patterning, to expose this first dielectric layer;
In this first dielectric layer, be formed with at least one opening that runs through this first dielectric layer, with this first metal layer of exposed parts;
At least one electronic building brick is set in this opening;
On this first dielectric layer and this electronic building brick, form the second dielectric layer;
Remove this loading plate;
In this second dielectric layer, form multiple the first blind holes that run through this second dielectric layer and expose this electronic building brick; And
On this second dielectric layer with described the first blind hole, form the first line layer that is electrically connected this electronic building brick, and this first metal layer of patterning is to form the second line layer.
8. the method for making of electronic building brick encapsulation according to claim 7, is characterized in that, is also included in and arranges after this electronic building brick, removes this second metal level.
9. the method for making of electronic building brick encapsulation according to claim 7, is characterized in that, the second metal level of this after patterning is to form tertiary circuit layer, and this second dielectric layer is also formed on this tertiary circuit layer.
10. the method for making of electronic building brick encapsulation according to claim 9, is characterized in that, this first blind hole is this tertiary circuit layer of exposed parts also, and this first line layer is also electrically connected this tertiary circuit layer.
The method for making of 11. electronic building brick encapsulation according to claim 7, it is characterized in that, forming after this second dielectric layer, also be included in and on this second dielectric layer, form the 3rd metal level, this first blind hole also runs through the 3rd metal level, and in this first blind hole, form metal material and patterning the 3rd metal level, to form this first line layer.
The method for making of 12. electronic building bricks according to claim 7 encapsulation, is characterized in that, this method for making also comprises and forms the conductive through hole that runs through this first dielectric layer and the second dielectric layer and be electrically connected this first line layer and the second line layer.
The method for making of 13. electronic building brick encapsulation according to claim 9, after removing this loading plate, also form multiple the second blind holes that run through this first dielectric layer and the first metal layer and expose this tertiary circuit layer, and this second line layer is also formed in this second blind hole.
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