CN111261526A - Packaging structure and preparation method thereof - Google Patents
Packaging structure and preparation method thereof Download PDFInfo
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- CN111261526A CN111261526A CN202010060213.9A CN202010060213A CN111261526A CN 111261526 A CN111261526 A CN 111261526A CN 202010060213 A CN202010060213 A CN 202010060213A CN 111261526 A CN111261526 A CN 111261526A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 208
- 239000002184 metal Substances 0.000 claims abstract description 208
- 238000002161 passivation Methods 0.000 claims abstract description 167
- 238000004519 manufacturing process Methods 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 336
- 238000000034 method Methods 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 20
- 229920005989 resin Polymers 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 239000012790 adhesive layer Substances 0.000 claims description 10
- 238000003825 pressing Methods 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 12
- 229920001451 polypropylene glycol Polymers 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 5
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920003192 poly(bis maleimide) Polymers 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- -1 diode Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68313—Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application provides a packaging structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a metal plate, and forming a first passivation layer on the back surface of the metal plate; etching the metal plate to form a metal wire; forming a second passivation layer on one side of the first passivation layer, where the metal wire is arranged, and the second passivation layer covers the metal wire; respectively forming metal columns connected with the metal routing lines in the first passivation layer and the second passivation layer, wherein the first passivation layer, the second passivation layer, the metal routing lines and the metal columns jointly form a rewiring layer; and forming a containing cavity on the redistribution layer, and packaging an electronic device in the containing cavity, wherein the top surface and the bottom surface of the electronic device are respectively positioned at two sides of the metal routing. The preparation method of the packaging structure is used for improving the integration level of the packaging structure and reducing the production cost of the packaging structure.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to a packaging structure and a preparation method thereof.
Background
The rapid development of electronic products requires that the packaging structure is continuously evolving towards smaller area and thinner thickness. The existing chip embedded type packaging structure is limited by the existing preparation method, and the product integration level is low and the production cost is high.
Disclosure of Invention
The application provides a packaging structure and a preparation method thereof, which are used for improving the integration level of the packaging structure and reducing the production cost of the packaging structure.
The preparation method of the packaging structure comprises the following steps:
providing a metal plate, and forming a first passivation layer on the back surface of the metal plate;
etching the metal plate to form a metal wire;
forming a second passivation layer on one side of the first passivation layer, where the metal wire is arranged, and the second passivation layer covers the metal wire;
respectively forming metal columns connected with the metal routing lines in the first passivation layer and the second passivation layer, wherein the first passivation layer, the second passivation layer, the metal routing lines and the metal columns jointly form a rewiring layer;
and forming a containing cavity on the redistribution layer, and packaging an electronic device in the containing cavity, wherein the top surface and the bottom surface of the electronic device are respectively positioned at two sides of the metal routing.
The preparation method comprises forming the metal wire, forming metal posts on two opposite surfaces of the metal wire to form a metal circuit in the redistribution layer, the metal posts are arranged on the two surfaces of the metal wire, so that the flexible design of the metal circuit is realized, different metal circuits are formed according to different electronic devices, the metal circuit is flexible in formation, a redistribution layer is formed by the first passivation layer, the second passivation layer, the metal routing and the metal column, then packaging an electronic device in the redistribution layer, wherein the top surface and the bottom surface of the electronic device are respectively positioned at two sides of the metal routing, namely, the circuit layer (metal wiring) is arranged on the side of the chip (electronic device), and the chip (electronic device) penetrates through the two sides of the circuit layer, so that the manufacturing process is beneficial to the miniaturization of the packaging structure. It can be understood that the first passivation layer and the second passivation layer are packaging bodies for packaging the electronic device, the electronic device is packaged in the packaging bodies, the metal routing lines and the metal columns are metal lines formed in the packaging bodies, the metal lines are arranged around the electronic device, the pads of the electronic device exposed out of the packaging bodies are connected with the metal lines designed through composition, and the purpose of rewiring can be achieved, so that a rewiring layer does not need to be formed on the surface of the packaging bodies. That is to say, this application does benefit to the thickness space of rewiring layer and arranges circuit layer and encapsulation chip simultaneously, can effectively reduce packaging structure's thickness, has still reduced the preparation step simultaneously, and preparation method is simple, has improved packaging structure's integrated level and cost competitiveness. And moreover, the electronic device is packaged after the metal circuit in the packaging body is formed, if the metal circuit in the packaging body is poor in processing, the electronic device can be removed in advance, the loss of the electronic device caused by the formation of the wiring poor in processing after the electronic device is packaged is avoided, the loss of the electronic device is effectively reduced, and the preparation yield and the reliability of the packaging structure are improved.
It is to be understood that, for electronic devices with thicker packages and electronic devices with more bonding pads, the manufacturing method of the present application has better effects of reducing thickness and cost and improving the manufacturing yield of the package structure. For example, for an electronic device with many pads, more external traces need to be fabricated during the packaging process, however, the thickness of the electronic device is significantly increased by too many external trace layers, and the integration level of the packaging structure is reduced. Meanwhile, too many external wiring layers can also cause the probability of poor external wiring in the manufacturing process, and the reject ratio of the packaging structure is increased. Through the preparation method, the external wiring is formed in the packaging body for packaging the electronic device, the external wiring can be changed into the internal wiring, namely, the circuit layer and the packaging chip are arranged in the thickness space of the packaging body at the same time, the thickness of the packaging structure is greatly reduced, and meanwhile, after the internal wiring is manufactured, the quality of the internal wiring can be detected, and then the electronic device can be packaged in the packaging body, so that the electronic device can be packaged in the packaging body with excellent internal wiring, the integration level of the packaging structure is improved, and the production cost is reduced while the preparation yield and the reliability are improved.
In one embodiment, a distance from the first surface to a surface of the metal trace facing away from the first passivation layer is less than a distance from the first surface to the top surface. In other words, the thickness of the electronic device is slightly smaller than that of the redistribution layer, so that the thickness of the packaging structure is small enough, the integration level of the packaging structure is not only effectively improved, but also the heat dissipation of the electronic device packaged in the redistribution layer is facilitated, and the electrical performance of the packaging structure is effectively improved.
In one embodiment, the distance from the top surface to the second surface of the redistribution layer is 20 μm to 80 μm. In other words, the thickness of the redistribution layer is only 20-80 μm thicker than that of the electronic device, in other words, the whole thickness of the packaging structure is very thin, the integration level of the packaging structure is greatly improved, and the thickness of the packaging material packaged on the top surface of the electronic device is very thin, so that the heat dissipation of the electronic device is effectively ensured, and the electrical performance of the packaging structure is effectively improved.
In one embodiment, the forming of the metal pillar connected to the metal trace in the first passivation layer and the second passivation layer respectively includes: forming openings in the first passivation layer and the second passivation layer respectively, wherein the metal routing is exposed out of the openings; forming the metal pillar in the opening. The metal column and the metal routing line formed in the opening form a metal line in the redistribution layer by controlling the position of the opening formed in the first passivation layer and the second passivation layer, and the opening can be reasonably arranged according to the electronic device so that the formed metal line is matched with the electronic device.
In one embodiment, the openings are formed in the first passivation layer and the second passivation layer, respectively, by a laser drilling process. The openings are formed on the first passivation layer and the second passivation layer in a laser hole forming mode, so that the openings are more convenient and quicker, and the precision of the openings can be ensured, thereby ensuring the precision of metal columns formed in the openings and further ensuring the electrical property of the packaging structure.
In one embodiment, the opening formed in the first passivation layer and the opening formed in the second passivation layer are disposed opposite to each other and/or offset from each other. In this embodiment, a part of the opening formed in the first passivation layer and a part of the opening formed in the second passivation layer are disposed opposite to each other, and a part of the opening formed in the first passivation layer and a part of the opening formed in the second passivation layer are disposed in a staggered manner, so as to ensure that the metal pillar and the metal trace formed in the first passivation layer and the second passivation layer form a redistribution metal circuit.
In one embodiment, the metal pillar is formed in the opening by an electroplating process. Of course, in other embodiments, the metal pillar may also be formed in the opening by an electroless plating process or other processes.
In one embodiment, the material of the first passivation layer is resin, and the first passivation layer is formed on the back surface of the metal plate through a pressing process. The resin is, for example, epoxy resin, bismaleimide triazine resin, or polypropylene glycol (PPG), and the first passivation layer is made to adhere to the back surface of the metal plate more closely by a pressing process.
In one embodiment, the second passivation layer is made of resin, and the second passivation layer is formed on the side of the first passivation layer where the metal trace is disposed through a pressing process. The resin is, for example, epoxy resin, bismaleimide triazine resin, polypropylene glycol (PPG), or the like, and the second passivation layer in this embodiment is made of the same material as the first passivation layer. And the second passivation layer is enabled to fill the gap between the metal wires through a pressing process, so that the metal wires are better coated.
In one embodiment, the electronic device includes one of a chip, a resistor-capacitor, and a diode. In this embodiment, the electronic device is a chip. Of course, in other embodiments, the electronic device may also be a resistor-capacitor, a diode, or other kind of electronic device.
In one embodiment, a sacrificial trace is further formed in the process of etching the metal plate, a first sacrificial column is formed on the first passivation layer while the metal column is formed, and a second sacrificial column is formed in the second passivation layer, the first sacrificial column and the second sacrificial column are connected to two sides of the sacrificial trace, the first sacrificial column and the second sacrificial column jointly form a material to be removed, the material to be removed is in a closed-loop architecture, and the process of forming the accommodating cavity in the redistribution layer is to etch the material to be removed to form the accommodating cavity. The sacrificial wiring is formed when the metal wiring is formed, the first sacrificial column and the second sacrificial column are formed when the metal column is formed, so that materials to be removed are formed, the position of the containing cavity is convenient to locate, the materials to be removed are directly removed through etching during the containing cavity, the containing cavity can be formed, the containing cavity is convenient to rapidly form, and the production efficiency is effectively improved.
In one embodiment, the process of encapsulating the electronic device in the accommodating cavity includes forming an adhesive layer on the first surface of the redistribution layer, installing the electronic device in the accommodating cavity, connecting a pad of the electronic device to the adhesive layer, and filling an encapsulating material in the accommodating cavity to encapsulate the electronic device. The electronic device is temporarily fixed in the accommodating cavity through the adhesive layer, so that the electronic device cannot deflect in the packaging process, and the adhesive layer is torn down after the electronic device is packaged, so that the bonding pad of the electronic device is exposed out of the first surface of the redistribution layer, and the bonding pad of the electronic device is connected with other lines conveniently.
In one embodiment, the manufacturing method further includes forming a first wire layer on the first surface of the redistribution layer, forming a second wire layer on the second surface of the redistribution layer, the first wire layer and the second wire layer being in communication through the redistribution layer, and the pad of the electronic device exposed on the first surface being connected to the second wire layer through the first wire layer. It will be appreciated that the first wire layer and the second wire layer are electrically connected by metal traces in the redistribution layer, thereby enabling pads of the electronic device to communicate through the first wire layer to the second wire layer.
In one embodiment, the preparation method further comprises forming solder masks on the surfaces of the first wire layer and the second wire layer, respectively. The solder mask layer is used for protecting the first wire layer and the second wire layer so as to prevent the first wire layer and the second wire layer from being exposed in the air and oxidized, influence the electrical property of the first wire layer and the second wire layer and prevent the first wire layer and the second wire layer from being in a condition that welding parts are not required to be welded with other structures and the welding parts are accidentally welded.
The packaging structure is manufactured and formed through the manufacturing method, and the packaging structure is installed on a circuit board of the mobile electronic equipment.
According to the manufacturing method, the first passivation layer, the second passivation layer, the metal wiring layer and the metal column jointly form the redistribution layer, then the electronic device is packaged in the redistribution layer, the top surface and the bottom surface of the electronic device are respectively located on two sides of the metal wiring layer, namely the circuit layer (metal wiring) is arranged on the side edge of the chip (electronic device), and the chip (electronic device) penetrates through two sides of the circuit layer, so that the manufacturing process is beneficial to miniaturization of a packaging structure. It can be understood that the first passivation layer and the second passivation layer are packaging bodies for packaging the electronic device, the electronic device is packaged in the packaging bodies, the metal routing lines and the metal columns are metal lines formed in the packaging bodies, the metal lines are arranged around the electronic device, the pads of the electronic device exposed out of the packaging bodies are connected with the metal lines designed through composition, and the purpose of rewiring can be achieved, so that a rewiring layer does not need to be formed on the surface of the packaging bodies. That is to say, this application does benefit to the thickness space of rewiring layer and arranges circuit layer and encapsulation chip simultaneously, can effectively reduce packaging structure's thickness, has still reduced the preparation step simultaneously, and preparation method is simple, has improved packaging structure's integrated level and cost competitiveness. And moreover, the electronic device is packaged after the metal circuit in the packaging body is formed, if the metal circuit in the packaging body is poor in processing, the electronic device can be removed in advance, the loss of the electronic device caused by the formation of the wiring poor in processing after the electronic device is packaged is avoided, the loss of the electronic device is effectively reduced, and the preparation yield and the reliability of the packaging structure are improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the background art of the present application, the drawings required to be used in the embodiments or the background art of the present application will be described below.
Fig. 1 is a schematic structural diagram of an electronic device to which an encapsulation structure prepared by a method for manufacturing an encapsulation structure according to an embodiment of the present application is applied.
Fig. 2 is a schematic flow chart of a method for manufacturing a package structure according to an embodiment of the present disclosure.
Fig. 3-4 are schematic process diagrams illustrating a method for manufacturing the package structure provided in fig. 2.
Fig. 5 is a schematic top view of a portion of the metal trace shown in fig. 4.
Fig. 6-13 are schematic process diagrams illustrating a method for manufacturing the package structure provided in fig. 2.
Fig. 14 is a schematic process diagram of another embodiment of a method for manufacturing the package structure provided in fig. 2.
Detailed Description
The embodiments of the present application will be described below with reference to the drawings.
According to the preparation method of the packaging structure provided by the embodiment of the application, the packaging structure prepared by the preparation method can be applied to electronic equipment with the packaging structure, such as mobile electronic equipment, a tablet computer, an electronic book reader, a notebook computer, vehicle-mounted equipment or wearable equipment. Referring to fig. 1, a mobile electronic device is an example of a mobile phone, and a mobile phone 100 includes a housing 10, a circuit board 20 and a package structure 30, wherein the package structure 30 is connected to the circuit board 20 and disposed in the housing 10 together with the circuit board 20. Specifically, the circuit board 20 may be a motherboard of the mobile phone 100, and the package structure 30 is electrically connected to the motherboard. The packaging structure 30 prepared by the preparation method is small in thickness and has a good heat dissipation effect. Therefore, the heat dissipation performance and the stability of the electronic equipment with the packaging structure 30 provided by the application are obviously improved, and the requirement of light-weight design is met.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a method for manufacturing the package structure 30 according to an embodiment of the present disclosure. The manufacturing method of the package structure 30 includes the following steps S110 to S160.
S110: a metal plate 31 is provided and a first passivation layer 32 is formed on the back side of the metal plate 31.
Specifically, referring to fig. 3, the metal plate 31 of the present embodiment is made of copper. The material of the first passivation layer 32 is an insulating resin material, such as epoxy resin, bismaleimide triazine resin, or Polypropylene glycol (PPG). The first passivation layer 32 is formed on the rear surface of the metal plate 31 through a press-fitting process. The first passivation layer 32 is more closely attached to the back surface of the metal plate 31 by a pressing process. Of course, in other embodiments, the material of the metal plate 31 may also include a conductive material such as aluminum metal. The first passivation layer 32 may also be formed on the back surface of the metal plate 31 by other means.
S120: the metal plate 31 is etched to form metal traces 31 a.
Specifically, referring to fig. 4 and 5, the metal plate 31 is etched from the front surface toward the back surface of the metal plate 31 to form a metal trace 31a on the first passivation layer 32. The metal trace 31a may be formed by a patterning process, for example, by patterning the metal plate 31 by an etching process, so as to form the metal trace 31 a. The specific pattern of the metal traces 31a is set according to the requirements of the packaged electronic device. The metal trace 31a in fig. 4 has two trace portions a1 connected by a trace a2 on the side thereof facing away from the first passivation layer 32, and a trace a2 facing away from the first passivation layer 32 connecting the two trace portions a1 is only used for showing a state where the two trace portions a1 are connected, and its top view is shown in fig. 5. In this embodiment, the sacrificial trace 31b is further formed in the process of etching the metal plate 31, the sacrificial trace 31b is used for facilitating formation of the accommodating cavity in the subsequent process, and the sacrificial trace 31b and the metal trace 31a are formed simultaneously, so that the process is simplified, the production efficiency of the product is improved, and the product cost competitiveness is further improved.
S130: a second passivation layer 33 is formed on the side of the first passivation layer 32 where the metal trace 31a is disposed, and the second passivation layer 33 covers the metal trace 31 a.
Specifically, referring to fig. 6, the second passivation layer 33 is formed on the side of the first passivation layer 32 where the metal trace 31a is disposed through a pressing process, and the second passivation layer 33 fills up the gap of the metal trace 31a and is pressed against the first passivation layer 32, so that the first passivation layer 32 and the second passivation layer 33 jointly cover the metal trace 31 a. The second passivation layer 33 covers the sacrificial trace 31b when being laminated on the side of the first passivation layer 32 where the metal trace 31a is disposed. It is understood that the first passivation layer 32 and the second passivation layer 33 form a package body covering the metal traces 31a and the sacrificial traces 31b by pressing. In this embodiment, the material of the second passivation layer 33 is an insulating resin material, such as epoxy resin, bismaleimide triazine resin, or Polypropylene glycol (PPG). The second passivation layer 33 in this embodiment is the same material as the first passivation layer 32. The second passivation layer 33 fills up the gap between the metal trace 31a and the sacrificial trace 31b through the pressing process, so that the metal trace 31a and the sacrificial trace 31b can be better covered. Of course, in other embodiments, the second passivation layer 33 and the first passivation layer 32 may be different materials. The manner of forming the second passivation layer 33 on the side of the first passivation layer 32 where the metal trace 31a is disposed is not limited to the lamination process.
S140: metal pillars 34 connected to the metal traces 31a are formed in the first passivation layer 32 and the second passivation layer 33, respectively, and the first passivation layer 32, the second passivation layer 33, the metal traces 31a, and the metal pillars 34 together constitute a redistribution layer 30 a.
Specifically, referring to fig. 7-8, first, openings are formed in the first passivation layer 32 and the second passivation layer 33, respectively, and the metal traces 31a are exposed through the openings. For convenience of understanding, the opening formed on the first passivation layer 32 is a first opening 321, and the opening formed on the second passivation layer 33 is a second opening 331. In this embodiment, there are a plurality of first openings 321 formed in the first passivation layer 32, a plurality of second openings 331 formed in the second passivation layer 33, a portion of the first openings 321 formed in the first passivation layer 32 and a portion of the second openings 331 formed in the second passivation layer 33 are disposed opposite to each other, and another portion of the first openings 321 formed in the first passivation layer 32 and the second openings 331 formed in the second passivation layer 33 are disposed in a staggered manner, so as to ensure that the metal pillars 34 and the metal traces 31a formed in the first passivation layer 32 and the second passivation layer 33 form metal lines matched with the electronic device. The first opening 321 and the second opening 331 are respectively formed at the positions of the first passivation layer 32 and the second passivation layer 33, which are needed to be arranged by the electronic device, and the positions of the first opening 321 formed in the first passivation layer 32 and the second opening 331 formed in the second passivation layer 33 are controlled, so that the metal pillar 34 and the metal trace 31a which are formed subsequently in the first opening 321 and the second opening 331 form a metal line matched with the electronic device in the redistribution layer 30 a. Of course, in other embodiments, the first opening 321 formed in the first passivation layer 32 and the second opening 331 formed in the second passivation layer 33 are disposed oppositely or offset according to requirements.
In this embodiment, the first opening 321 formed in the first passivation layer 32 and the second opening 331 formed in the second passivation layer 33 are formed by a laser drilling process. The first opening 321 and the second opening 331 are formed on the first passivation layer 32 and the second passivation layer 33 respectively in a laser hole opening manner, so that the first opening 321 and the second opening 331 are more convenient and faster, and the accuracy of the first opening 321 and the second opening 331 can be ensured, thereby ensuring the accuracy of the metal pillar 34 formed in the first opening 321 and the second opening 331, and further ensuring the electrical performance of the package structure 30. Of course, in other embodiments, the openings may be formed on the first passivation layer 32 and the second passivation layer 33 by other opening methods.
While the first opening 321 and the second opening 331 are respectively formed on the first passivation layer 32 and the second passivation layer 33, notches are formed on the first passivation layer 32 and the second passivation layer 33, the notch formed on the first passivation layer 32 is a first notch 322, the notch formed on the second passivation layer 33 is a second notch 332, and the first notch 322 and the second notch 332 are oppositely disposed to respectively expose two sides of the sacrificial trace 31 b.
Then, metal pillars 34 are formed in the first opening 321 and the second opening 331, respectively, and the first passivation layer 32, the second passivation layer 33, the metal trace 31a, and the metal pillars 34 together constitute a redistribution layer 30 a. It is understood that the metal pillar 34 and the metal trace 31a constitute a metal line in the redistribution layer 30 a. The first passivation layer 32 and the second passivation layer 33 constitute a package for packaging the metal line, that is, the metal line is disposed in the package formed by the first passivation layer 32 and the second passivation layer 33, and the metal pillar 34 formed on the first passivation layer 32 exposes the first surface 301 of the redistribution layer 30a, the first surface 301 of the redistribution layer 30a is a surface of the first passivation layer 32 facing away from the metal trace 31a, the metal pillar 34 formed on the second passivation layer 33 exposes the second surface 302 of the redistribution layer 30a, and the second surface 302 of the redistribution layer 30a is a surface of the second passivation layer 33 facing away from the metal trace 31 a. In this embodiment, the metal pillar 34 is made of copper, and the metal pillar 34 is formed in the first opening 321 and the second opening 331 by an electroplating process. Of course, in other embodiments, the material of the metal pillar 34 may also include a conductive material such as aluminum metal. The metal pillar 34 may also be formed in the first and second openings 321 and 331 by an electroless plating process or other processes.
The first sacrificial column 351 is formed on the first passivation layer 32 while the metal column 34 is formed in the first opening 321 and the second opening 331, and the second sacrificial column 352 is formed in the second passivation layer 33, the first sacrificial column 351 and the second sacrificial column 352 are connected to two sides of the sacrificial trace 31b, and the three components together form a material to be removed, and the material to be removed is in a closed-loop structure. Specifically, the material to be removed includes the first sacrificial post 351, the second sacrificial post 352, the sacrificial trace 31b, and a portion of the first passivation layer 32 and the second passivation layer 33 surrounded by the three, and the closed-loop structure is a rectangular parallelepiped. In this embodiment, the first sacrificial post 351 and the second sacrificial post 352 are made of the same material as the metal post 34, and are formed by the same process as the metal post 34. Treat through the formation and get rid of the material to be convenient for the location holds the position in chamber, when follow-up formation holds the chamber, directly get rid of through the etching and wait to get rid of the material and can form and hold the chamber, be convenient for more hold the quick formation in chamber, effectively improve production efficiency. Of course, in other embodiments, the closed-loop architecture may be any shape including cylindrical or rectangular parallelepiped. The process of forming the first sacrificial post 351 and the second sacrificial post 352 may be different from the process of forming the metal post 34.
S150: a containing cavity 36 is formed on the redistribution layer 30a, and the electronic device 37 is packaged in the containing cavity 36, wherein the top surface 371 and the bottom surface 372 of the electronic device 37 are respectively located at two sides of the metal trace 31 a.
Specifically, referring to fig. 9-11, first, the material to be removed is etched to form the accommodating cavity 36, and the accommodating cavity 36 penetrates through the first surface 301 and the second surface 302 of the redistribution layer 30 a. By etching the first sacrificial column 351, the second sacrificial column 352 and the sacrificial trace 31b, a part of the first passivation layer 32 and the second passivation layer 33 which are surrounded by the first sacrificial column 351, the second sacrificial column 352 and the sacrificial trace 31b can be removed at the same time, so that the use of an etchant is greatly reduced, and the production cost is reduced. Then, an adhesive layer 38 is formed on the first surface 301 of the redistribution layer 30a, the electronic device 37 is mounted in the accommodating cavity 36, the pad 373 of the electronic device 37 is connected to the adhesive layer 38, the pad 373 is disposed on the bottom surface 372 of the electronic device 37, the accommodating cavity 36 is filled with the packaging material 39 to package the electronic device 37, the top surface 371 and the bottom surface 372 of the electronic device 37 are respectively located on two sides of the metal trace 31a, that is, the circuit layer (the metal trace 31a) is disposed on a side of the chip (the electronic device 37), and the chip (the electronic device 37) penetrates through two sides of the circuit layer.
In this embodiment, the electronic device 37 is a chip, such as a CPU chip, a radio frequency driving chip, or a chip of another processor. The encapsulating material 39 filled in the accommodating cavity 36 is an insulating resin material, such as epoxy resin, bismaleimide triazine resin, or polypropylene glycol (PPG). Electronic device 37 is temporarily held in receiving cavity 36 by adhesive layer 38 so that electronic device 37 does not deflect during packaging, and adhesive layer 38 is removed after electronic device 37 is packaged, so that pads 373 of electronic device 37 are exposed from first surface 301 of redistribution layer 30a, so that pads 373 of electronic device 37 are connected to other wires. Of course, in other embodiments, electronic device 37 may also be a resistor-capacitor, diode, capacitor, inductor, resistor, or other type of electronic device 37.
In this embodiment, as shown in fig. 11, after the electronic device 37 is packaged in the accommodating cavity 36, a distance h1 from the first surface 301 to a surface of the metal trace 31a facing away from the first passivation layer 32 is smaller than a distance h2 from the first surface 301 to the top surface 371 of the electronic device 37. In other words, the thickness of the electronic device 37 is slightly smaller than that of the redistribution layer 30a, so that the thickness of the package structure 30 is small enough, the integration level of the package structure 30 is not only effectively improved, but also the heat dissipation of the electronic device 37 packaged in the redistribution layer 30a is facilitated, and the electrical performance of the package structure 30 is effectively improved.
In the present embodiment, the distance h3 from the top surface 371 of the electronic device 37 to the second surface 302 of the rewiring layer 30a is 20 μm to 80 μm. That is to say, the thickness of the redistribution layer 30a is only 20 μm to 80 μm thicker than the thickness of the electronic device 37, in other words, the overall thickness of the package structure 30 is very thin, the integration level of the package structure 30 is greatly improved, and the thickness of the packaging material 39 packaged on the top surface 371 of the electronic device 37 is also very thin, so that the heat dissipation of the electronic device 37 is effectively ensured, and the electrical performance of the package structure 30 is effectively improved.
S160: first wire layer 40 is formed on first surface 301 of rewiring layer 30a, and second wire layer 41 is formed on second surface 302 of rewiring layer 30 a.
Specifically, referring to fig. 12, after electronic device 37 is packaged, first wire layer 40 is formed on first surface 301 of redistribution layer 30a, second wire layer 41 is formed on second surface 302 of redistribution layer 30a, and first wire layer 40 and second wire layer 41 may be formed through a patterning process. For example, the first wire layer 40 and the second wire layer 41 may be formed by forming a metal thin film layer on the first surface 301 and the second surface 302 by a Physical Vapor Deposition (PVD) process, a sputtering process, or an electroplating process, and then patterning the metal thin film layer by a patterning process such as etching, thereby forming the first wire layer 40 and the second wire layer 41. The material of the first wire layer 40 and the second wire layer 41 is copper. The first wire layer 40 is connected to the pads 373 of the electronic devices 37 and the metal posts 34 exposed at the first surface 301, and the second wire layer 41 is connected to the metal posts 34 exposed at the second surface 302, so that the first wire layer 40 and the second wire layer 41 are connected by the rewiring layer 30a, so that the pads 373 of the electronic devices 37 exposed at the first surface 301 are connected to the second wire layer 41 through the first wire layer 40. It will be appreciated that first wire layer 40 and second wire layer 41 are electrically connected by metal traces in rewiring layer 30a, thereby enabling pad 373 of electronic device 37 to be routed through first wire layer 40 to second wire layer 41. Of course, in other embodiments, the material of the first wire layer 40 and the second wire layer 41 is a conductive material such as aluminum.
As shown in fig. 13, after the first wire layer 40 and the second wire layer 41 are formed, solder masks are formed on the surfaces of the first wire layer 40 and the second wire layer 41, respectively. Specifically, solder masks are formed on the surfaces of the first wire layer 40 and the second wire layer 41 facing away from the rewiring layer 30a, respectively. The solder mask layer can be a solder mask green oil layer, or different layers with protection functions such as plastic package or resin layers. To ensure that the package structure 30 can be electrically connected to other components. The anti-welding layer is provided with a window. The solder mask is used for protecting the first wire layer 40 and the second wire layer 41, so as to prevent the first wire layer 40 and the second wire layer 41 from being exposed to air and oxidized, influence the electrical performance of the first wire layer 40 and the second wire layer 41, and prevent the first wire layer 40 and the second wire layer 41 from being accidentally soldered without being soldered with other structures.
For convenience of understanding, the solder mask layer disposed on the first wire layer 40 is referred to as a first solder mask layer 42, when the first solder mask layer 42 is disposed on the first wire layer 40, the first solder mask layer 42 is formed on the first wire layer 40 by injection molding or evaporation, and a plurality of first windows 421 are formed on the first solder mask layer 42 to expose a portion of the first wire layer 40, where the first wire layer 40 has a first connection end 40a exposed out of each first window 421. The first connection 40a is provided for connection to other circuits. Solder balls may also be disposed at the first connection end 40a to connect the package structure 30 with a motherboard of an electronic device through the solder balls. The solder mask layer disposed on the second wire layer 41 is referred to as a second solder mask layer 43, and when the second solder mask layer 43 is disposed on the second wire layer 41, the second solder mask layer 43 is formed on the second wire layer 41 by injection molding or vapor deposition, and a plurality of second windows 431 are formed on the second solder mask layer 43 to expose a portion of the second wire layer 41, where the second wire layer 41 has a second connection terminal 41a exposed through each of the second windows 431. The second connection 41a provided can be used for connecting to other circuits.
In this embodiment, the metal trace 31a is only one layer. Of course, in other embodiments, referring to fig. 14, the metal trace 31a is multi-layered, and the specific steps of the preparation are to form a metal pillar 34 connected to the metal trace 31a in each of the first passivation layer 32 and the second passivation layer 33, form a metal plate on the second passivation layer 33, etch the metal plate to form another metal trace 31a, then press another second passivation layer 33 on the side of the second passivation layer 33 where the another metal trace 31a is disposed, then form a metal pillar 34 connected to the metal trace 31a in another second passivation layer 33, and repeat this step to form the multi-layered metal trace 31 a. The first passivation layer 32, the multilayer second passivation layer 33, the multilayer metal trace 31a, and the multilayer metal pillar 34 collectively constitute a rewiring layer 30 a. Specifically, the number of layers of the metal trace 31a and the connection manner of the metal trace 31a are set according to the electronic device 37 disposed in the redistribution layer 30a, and generally, the electronic device 37 with a large number of pads needs to have more layers of metal traces 31a and connection manners of the metal trace 31a, which are more complicated. Meanwhile, a sacrificial trace, a first sacrificial column and a second sacrificial column are formed while the metal trace 31a and the metal column 34 are formed, so that the sacrificial trace, the first sacrificial column and the second sacrificial column together form a material to be removed, and the material to be removed is in a closed-loop structure, so that a containing cavity is formed.
The preparation method of the application comprises the steps of firstly forming the metal wire 31a, then forming the metal columns 34 on two opposite surfaces of the metal wire 31a to form the metal circuit in the rewiring layer 30a, realizing flexible design of the metal circuit by arranging the metal columns 34 at the positions of the two surfaces of the metal wire 31a to support different metal circuits formed according to different electronic devices 37, wherein the metal circuit is flexible in structure, the rewiring layer 30a is formed by the first passivation layer 32, the second passivation layer 33, the metal wire 31a and the metal columns 34 together, then packaging the electronic device 37 in the rewiring layer 30a, wherein the top surface 371 and the bottom surface 372 of the electronic device 37 are respectively positioned on two sides of the metal wire 31a, namely the circuit layer (the metal wire 31a) is arranged on the side of the chip (the electronic device 37), and the chip (the electronic device 37) penetrates through the two sides of the circuit layer, such a fabrication process facilitates miniaturization of the package structure 30. It can be understood that the first passivation layer 32 and the second passivation layer 33 are package bodies for packaging the electronic device 37, the electronic device 37 is packaged in the package bodies, the metal traces 31a and the metal pillars 34 are metal lines formed in the package bodies, the metal lines are disposed around the electronic device 37, and the pads 373 of the electronic device 37 exposed out of the package bodies are connected with the metal lines designed by patterning, so that the purpose of rerouting can be achieved, and the rerouting layer 30a does not need to be formed on the surface of the package bodies. That is to say, the method and the device are beneficial to simultaneously arranging the circuit layer and the packaged chip in the thickness space of the rewiring layer, can effectively reduce the thickness of the packaging structure 30, simultaneously reduce the preparation steps, are simple in preparation method, and improve the integration level and the cost competitiveness of the packaging structure 30. Moreover, the electronic device 37 is packaged after the metal circuit inside the package body is formed, and if the metal circuit inside the package body is poor in process, the electronic device 37 can be removed in advance, so that the loss of the electronic device 37 caused by poor-process routing formed after the electronic device 37 is packaged is avoided, the loss of the electronic device 37 is effectively reduced, and the preparation yield and reliability of the packaging structure 30 are improved.
It should be appreciated that the manufacturing method of the present application has better effects of reducing thickness and cost and improving the manufacturing yield of the package structure 30 for packaging the electronic device 37 with a larger thickness and the electronic device 37 with a larger number of pads 373. For example, for the electronic device 37 with more pads 373, more external traces need to be fabricated during the packaging process, however, too many external trace layers significantly increase the thickness of the electronic device 37, and reduce the integration level of the package structure 30. Meanwhile, too many external wiring layers can also cause poor external wiring probability in the manufacturing process, and the reject ratio of the packaging structure 30 is increased. Through the preparation method of the application, the external wiring is formed in the packaging body for packaging the electronic device 37, the external wiring can be changed into the internal wiring, namely, the circuit layer and the electronic device 37 are simultaneously arranged in the thickness space of the packaging body, the thickness of the packaging structure 30 is greatly reduced, meanwhile, after the internal wiring is manufactured, the quality of the internal wiring can be detected, then, the electronic device 37 can be packaged in the packaging body with excellent internal wiring, the integration level of the packaging structure 30 is improved, and the production cost is reduced while the preparation yield and the reliability are improved.
The above embodiments and embodiments of the present invention are only examples and embodiments, and the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (13)
1. A preparation method of a packaging structure is characterized by comprising the following steps:
providing a metal plate, and forming a first passivation layer on the back surface of the metal plate;
etching the metal plate to form a metal wire;
forming a second passivation layer on one side of the first passivation layer, where the metal wire is arranged, and the second passivation layer covers the metal wire;
respectively forming metal columns connected with the metal routing lines in the first passivation layer and the second passivation layer, wherein the first passivation layer, the second passivation layer, the metal routing lines and the metal columns jointly form a rewiring layer;
and forming a containing cavity on the redistribution layer, and packaging an electronic device in the containing cavity, wherein the top surface and the bottom surface of the electronic device are respectively positioned at two sides of the metal routing.
2. The method according to claim 1, wherein a distance from the first surface to a surface of the metal trace facing away from the first passivation layer is smaller than a distance from the first surface to the top surface.
3. The method of manufacturing according to claim 2, wherein a distance from the top surface to the second surface of the redistribution layer is 20 μm to 80 μm.
4. The method for manufacturing according to any one of claims 1 to 3, wherein the forming of the metal pillar connected to the metal trace in the first passivation layer and the second passivation layer respectively comprises:
forming openings in the first passivation layer and the second passivation layer respectively, wherein the metal routing is exposed out of the openings;
forming the metal pillar in the opening.
5. The method of claim 4, wherein the opening is formed in the first passivation layer and the second passivation layer by a laser drilling process.
6. The method according to claim 5, wherein the opening formed in the first passivation layer and the opening formed in the second passivation layer are disposed opposite to each other and/or are misaligned.
7. The method of manufacturing according to claim 6, wherein the metal pillar is formed in the opening by an electroplating process.
8. The manufacturing method according to claim 7, wherein the material of the first passivation layer is resin, and the first passivation layer is formed on the back surface of the metal plate by a pressing process.
9. The manufacturing method according to any one of claims 5 to 8, wherein a sacrificial trace is further formed during etching the metal plate, a first sacrificial column is formed in the first passivation layer while the metal column is formed, and a second sacrificial column is formed in the second passivation layer, the first sacrificial column and the second sacrificial column are connected to two sides of the sacrificial trace, the three together form a material to be removed, the material to be removed is in a closed-loop structure, and the process of forming the accommodating cavity in the redistribution layer is to etch the material to be removed to form the accommodating cavity.
10. The manufacturing method according to claim 9, wherein the process of encapsulating the electronic device in the accommodating cavity includes forming an adhesive layer on the first surface of the redistribution layer, mounting the electronic device in the accommodating cavity, connecting a pad of the electronic device to the adhesive layer, and filling an encapsulating material in the accommodating cavity to encapsulate the electronic device.
11. The manufacturing method according to claim 10, further comprising forming a first wire layer on a first surface of the rewiring layer, forming a second wire layer on a second surface of the rewiring layer, the first wire layer and the second wire layer being in communication through the rewiring layer, and a pad of the electronic device exposed on the first surface being in communication with the second wire layer through the first wire layer.
12. The method of manufacturing according to claim 11, further comprising forming solder masks on the surfaces of the first wire layer and the second wire layer, respectively.
13. A package structure fabricated by the method of any one of claims 1-12, the package structure being mounted on a circuit board of a mobile electronic device.
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| PCT/CN2020/122407 WO2021143242A1 (en) | 2020-01-19 | 2020-10-21 | Packaging structure and preparation method therefor |
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