CN110459483A - A kind of manufacturing method and semiconductor laminated packaging method of capacitance component - Google Patents
A kind of manufacturing method and semiconductor laminated packaging method of capacitance component Download PDFInfo
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- CN110459483A CN110459483A CN201910619221.XA CN201910619221A CN110459483A CN 110459483 A CN110459483 A CN 110459483A CN 201910619221 A CN201910619221 A CN 201910619221A CN 110459483 A CN110459483 A CN 110459483A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 3
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical group [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of manufacturing methods of capacitance component and semiconductor laminated packaging method, carry out integration packaging using individual capacitance component module, not only can reduce the size of encapsulation, while improving the flexibility of encapsulation, reduce costs；The capacitance component both includes capacitance structure, also includes through-hole structure, and preparation process is simple, can use conductive layer and forms two kinds of structures, and the depth only etched is different, causes the electrically connecting position of through-hole different.
Description
Technical field
The present invention relates to semiconductor packages field, the manufacturing method of specially a kind of capacitance component and semiconductor laminated
Packaging method.
Background technique
With the continuous improvement of integrated level, integrated antenna package uses package on package mode, i.e. POP structure.This kind envelope
Dress is a kind of 3 D stereo encapsulation, can control the stacking or lateral arrangement of chip, flexibly to meet the needs of small size.For
Some integrated antenna packages with specific function, generally require integrated capacitance device, are often by capacitor in the prior art
Device is combined encapsulation as an individual chips, or embedded capacitor arrangement is formed in wiring layer, this two kinds encapsulation
Although solving the specific function of integrated circuit, the reduction for its size is unfavorable, and also results in packaging body
The warpage by stress.
Summary of the invention
Based on solving the above problems, the present invention provides a kind of manufacturing methods of capacitance component comprising following steps:
1) deposition forms patterned conductive layer on substrate；
2) dielectric layer is covered on the conductive layer over the substrate；
3) low-K material layer is formed on the dielectric layer, and is formed first in the low-K material layer by etching for the first time and opened
Mouthful and the second opening, wherein the first opening and the second opening correspond respectively to the patterned conductive layer, and described the
The dielectric layer is exposed in the bottom of one opening and the second opening；
4) second of etching is implemented to etch away the dielectric layer of the second open bottom to the second opening therein, is opened with forming third
Mouthful, wherein third opening exposes the conductive layer；
5) in first opening and third opening filling conductive materials to form on first through-hole on through-hole and second,
In, through-hole is separated with the conductive layer by the dielectric layer on described first, through-hole and conductive layer electricity on described second
Connection；
6) it is open from the back side of the substrate and carries out conductive materials and filled to form the first lower through-hole and the second lower through-hole,
Wherein, through-hole corresponds on first lower through-hole and described first, through-hole one on second lower through-hole and described second
One is corresponding, and first and second lower through-hole is electrically connected with the conductive layer；
According to an embodiment of the invention, wherein, which is silicon substrate.
According to an embodiment of the invention, the low-K material layer is silica or silicon nitride.
According to an embodiment of the invention, the dielectric layer is hafnium, such as ZrO2, Al2O3, Si3N4, HfO2, Y2O3,
SiO2, Ta2O5, La2O3, TiO2。
According to an embodiment of the invention, the conductive layer is aluminium, copper, titanium, titanium nitride, tantalum, any one in tantalum nitride
Or multiple combinations.
The present invention also provides a kind of semiconductor laminated packaging methods comprising following steps:
1) the first chip of fixed placement and multiple capacitance components on temporary carrier, the multiple capacitance component are above-mentioned capacitor
Component；
2) first chip and multiple capacitance components are sealed using the first plastic packaging layer, wherein the top of the multiple capacitance component
Face is flushed from the top surface of the first plastic packaging layer, and through-hole reveals from the top of the first plastic packaging layer on described first and second
Out；
3) the second redistributing layer is formed on the first plastic packaging layer, through-hole is electrically connected to described on described first and second
Two redistributing layers；
4) the second chip is electrically connected by soldered ball on second redistributing layer, and utilizes the second plastic packaging layer sealing described second
Chip；
5) remove the temporary carrier, form the first redistributing layer in the lower section of the first plastic packaging layer, first chip and
First and second lower through-holes of the multiple capacitance component are electrically connected to first redistributing layer.
According to an embodiment of the invention, further including forming external connection terminals in the lower section of first redistributing layer.
Advantages of the present invention is as follows: carrying out integration packaging using individual capacitance component module, not only can reduce encapsulation
Size, while improving the flexibility of encapsulation, reduce costs；The capacitance component both includes capacitance structure, also includes through-hole
Structure, and preparation process is simple, can use conductive layer and forms two kinds of structures, the depth only etched is different, leads to through-hole
Electrically connecting position it is different.
Detailed description of the invention
Fig. 1 is the cross-sectional view of capacitance component of the invention；
Fig. 2 is semiconductor laminated encapsulating structure of the invention；
Fig. 3-8 is the schematic diagram of capacitance component manufacturing method of the invention；
Fig. 9-13 is the schematic diagram of semiconductor laminated packaging method of the invention.
Specific embodiment
Referring to Fig. 1, the present invention provides a kind of capacitance components 100, and the capacitance component 100 is including substrate 10 and its in substrate
Capacitor arrangement and through-hole structure on 10.Capacitor arrangement includes through-hole 17, dielectric layer 12, conductive layer 11 and first on first
Lower through-hole 19, the through-hole structure include through-hole 18, conductive layer 11 and the second lower through-hole 20 on second, wherein first He
Second lower through-hole 19,20 is set in the substrate 10, and is formed in identical step by identical technique.The conduction
Layer 11 is deposited on the substrate 10, and has multiple discrete conductive patterns, multiple discrete conductive pattern respectively with institute
State the corresponding simultaneously physical connection of the first and second lower through-holes 19,20.The dielectric layer 12 covers the substrate 10 and conductive layer 11, and
Only the bottom of through-hole 18 has opening on described second, which exposes the conductive layer 11.Low-K material layer 13 is formed in
On the dielectric layer 12, and through-hole 17,18 is formed in the low-K material layer 13 on described first and second, leads on described first
The dielectric layer 12 is physically contacted in the bottom in hole 17, and the conductive layer 11 is physically contacted in the bottom of through-hole 18 on described second.Institute
Top crown of the through-hole 17 as capacitor arrangement on first is stated, and first lower through-hole 19 and the conductive layer 12 are used as capacitor
The bottom crown of device structure.
The manufacturing method of above-mentioned capacitance structure is referring to Fig. 3-8, and referring first to Fig. 3, deposition forms patterning on substrate 10
Conductive layer 11, wherein the substrate 10 is silicon substrate, the conductive layer 11 be aluminium, copper, titanium, titanium nitride, tantalum, in tantalum nitride
Any one or more combination.
Referring to fig. 4, dielectric layer 12 is covered on the substrate 10 and on the conductive layer 11, the dielectric layer 12 is high K
Material, such as ZrO2, Al2O3, Si3N4, HfO2, Y2O3, SiO2, Ta2O5, La2O3, TiO2。
Referring to Fig. 5, low-K material layer 13 is formed on the dielectric layer 12, and by etching for the first time in the low-K material
The first opening 14 and the second opening 15 are formed in layer 13, wherein first opening 14 and the second opening 15 correspond to the pattern
The conductive layer 11 of change, and the dielectric layer 12 is exposed in the bottom of first opening 14 and the second opening 15.Wherein, the low K material
The bed of material 13 is silica or silicon nitride.
Referring to Fig. 6, second of etching is implemented to etch away the dielectric of 15 bottom of the second opening to the second opening 15 therein
Layer, to form third opening 16, wherein third opening 16 exposes the conductive layer 11.
Referring to Fig. 7, conductive materials are filled to form through-hole 17 on first in first opening 14 and third opening 16
With second on through-hole 18, wherein through-hole 17 and the conductive layer 11 are separated by the dielectric layer 11 on described first, described the
Through-hole 18 is electrically connected with the conductive layer 11 on two.
Referring to Fig. 8, opening is carried out from the back side of the substrate 10 and forms the 4th opening and the 5th opening, and to the described 4th
Opening and the 5th opening carry out conductive materials filling to form the first lower through-hole 19 and the second lower through-hole 20, wherein described first
Through-hole 17 corresponds on lower through-hole 19 and described first, and through-hole 18 1 is a pair of on second lower through-hole 20 and described second
It answers, and first and second lower through-hole is electrically connected with the conductive layer 11.
In integrated antenna package, the capacitance component is conducive to encapsulation.Referring specifically to Fig. 2, which includes having
First redistributing layer 28 of first surface and second surface is provided with the first chip 22 and extremely on first redistributing layer 28
First and second lower through-holes 19 of a few above-mentioned capacitance component 100, first chip 22 and the capacitance component 100,
20 are electrically connected to first redistributing layer 28.First plastic packaging layer 23 seals first chip 22, capacitance component 100, described
The top surface of capacitance component 100 is flushed from the top surface of the first plastic packaging layer 23, and on described first and second through-hole 17,18 from
Expose at the top of the first plastic packaging layer 23.Second redistributing layer 24 is formed on the first plastic packaging layer 23, and described first
With second on through-hole 17,18 be electrically connected to second redistributing layer 24.Pass through soldered ball 26 on second redistributing layer 24
It is electrically connected the second chip 25, and seals second chip 25 using the second plastic packaging layer 27.In addition, also having in the second surface
There are the outer connection terminal 29 for being electrically connected first redistributing layer 28, such as soldered ball etc..
The manufacturing method of above-mentioned encapsulating structure is referring to Fig. 9-13, referring first to Fig. 9, fixed placement on temporary carrier 21
One chip 22 and multiple capacitance components 100, wherein the capacitance component 100 is set to around first chip 22.
Referring to Figure 10, first chip 22 and multiple capacitance components 100 are sealed using the first plastic packaging layer 23, wherein institute
The top surface for stating capacitance component 100 is flushed from the top surface of the first plastic packaging layer 23, and through-hole 17,18 on described first and second
Expose from the top of the first plastic packaging layer 23.
Referring to Figure 11, the second redistributing layer 24 is formed on the first plastic packaging layer 23, is led on described first and second
Hole 17,18 is electrically connected to second redistributing layer 24.Pass through the electrical connection of soldered ball 26 second on second redistributing layer 24
Chip 25, and second chip 25 is sealed using the second plastic packaging layer 27.
Referring to Figure 12, the temporary carrier 21 is removed.
Referring to Figure 13, the first redistributing layer 28,22 He of the first chip are formed in the lower section of the first plastic packaging layer 23
First and second lower through-holes 19,20 of the capacitance component 100 are electrically connected to first redistributing layer 28.Finally, described
The lower section of first redistributing layer 28 forms external connection terminals 29.
Finally, it should be noted that obviously, the above embodiment is merely an example for clearly illustrating the present invention, and simultaneously
The non-restriction to embodiment.For those of ordinary skill in the art, it can also do on the basis of the above description
Other various forms of variations or variation out.There is no necessity and possibility to exhaust all the enbodiments.And thus drawn
The obvious changes or variations that Shen goes out are still in the protection scope of this invention.
Claims (7)
1. a kind of manufacturing method of capacitance component comprising following steps:
1) deposition forms patterned conductive layer on substrate；
2) dielectric layer is covered on the conductive layer over the substrate；
3) low-K material layer is formed on the dielectric layer, and is formed first in the low-K material layer by etching for the first time and opened
Mouthful and the second opening, wherein the first opening and the second opening correspond respectively to the patterned conductive layer, and described the
The dielectric layer is exposed in the bottom of one opening and the second opening；
4) second of etching is implemented to etch away the dielectric layer of the second open bottom to the second opening therein, is opened with forming third
Mouthful, wherein third opening exposes the conductive layer；
5) in first opening and third opening filling conductive materials to form on first through-hole on through-hole and second,
In, through-hole is separated with the conductive layer by the dielectric layer on described first, through-hole and conductive layer electricity on described second
Connection；
6) it is open from the back side of the substrate and carries out conductive materials and filled to form the first lower through-hole and the second lower through-hole,
Wherein, through-hole corresponds on first lower through-hole and described first, through-hole one on second lower through-hole and described second
One is corresponding, and first and second lower through-hole is electrically connected with the conductive layer.
2. the manufacturing method of capacitance component according to claim 1, it is characterised in that: wherein, which is silicon substrate.
3. the manufacturing method of capacitance component according to claim 1, it is characterised in that: the low-K material layer be silica or
Person's silicon nitride.
4. the manufacturing method of capacitance component according to claim 1, it is characterised in that: the dielectric layer is hafnium, example
Such as ZrO2, Al2O3, Si3N4, HfO2, Y2O3, SiO2, Ta2O5, La2O3, TiO2。
5. the manufacturing method of capacitance component according to claim 1, it is characterised in that: the conductive layer be aluminium, copper, titanium,
Titanium nitride, tantalum, any one or more combination in tantalum nitride.
6. a kind of semiconductor laminated packaging method comprising following steps:
1) the first chip of fixed placement and multiple capacitance components on temporary carrier, the multiple capacitance component are claim 1-
Capacitance component described in any one of 5；
2) first chip and multiple capacitance components are sealed using the first plastic packaging layer, wherein the top of the multiple capacitance component
Face is flushed from the top surface of the first plastic packaging layer, and through-hole reveals from the top of the first plastic packaging layer on described first and second
Out；
3) the second redistributing layer is formed on the first plastic packaging layer, through-hole is electrically connected to described on described first and second
Two redistributing layers；
4) the second chip is electrically connected by soldered ball on second redistributing layer, and utilizes the second plastic packaging layer sealing described second
Chip；
5) remove the temporary carrier, form the first redistributing layer in the lower section of the first plastic packaging layer, first chip and
First and second lower through-holes of the multiple capacitance component are electrically connected to first redistributing layer.
7. semiconductor laminated packaging method according to claim 6, it is characterised in that: further include in first redistribution
The lower section of layer forms external connection terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910619221.XA CN110459483A (en) | 2019-07-10 | 2019-07-10 | A kind of manufacturing method and semiconductor laminated packaging method of capacitance component |
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| CN201910619221.XA CN110459483A (en) | 2019-07-10 | 2019-07-10 | A kind of manufacturing method and semiconductor laminated packaging method of capacitance component |
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| CN110459483A true CN110459483A (en) | 2019-11-15 |
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| CN201910619221.XA Withdrawn CN110459483A (en) | 2019-07-10 | 2019-07-10 | A kind of manufacturing method and semiconductor laminated packaging method of capacitance component |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111261526A (en) * | 2020-01-19 | 2020-06-09 | 华为技术有限公司 | Packaging structure and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1367936A (en) * | 1999-06-08 | 2002-09-04 | 因芬尼昂技术股份公司 | Semiconductor storage component with storage cells, logic areas and filling structures |
| US20130039113A1 (en) * | 2010-01-21 | 2013-02-14 | Stmicroelectronics (Crolles 2) Sas | Integrated dram memory device |
| CN108109957A (en) * | 2017-12-15 | 2018-06-01 | 西安科锐盛创新科技有限公司 | The antistatic pinboard of system in package |
| CN108389823A (en) * | 2018-01-31 | 2018-08-10 | 浙江卓晶科技有限公司 | For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology |
-
2019
- 2019-07-10 CN CN201910619221.XA patent/CN110459483A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1367936A (en) * | 1999-06-08 | 2002-09-04 | 因芬尼昂技术股份公司 | Semiconductor storage component with storage cells, logic areas and filling structures |
| US20130039113A1 (en) * | 2010-01-21 | 2013-02-14 | Stmicroelectronics (Crolles 2) Sas | Integrated dram memory device |
| CN108109957A (en) * | 2017-12-15 | 2018-06-01 | 西安科锐盛创新科技有限公司 | The antistatic pinboard of system in package |
| CN108389823A (en) * | 2018-01-31 | 2018-08-10 | 浙江卓晶科技有限公司 | For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology |
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| CN111261526A (en) * | 2020-01-19 | 2020-06-09 | 华为技术有限公司 | Packaging structure and preparation method thereof |
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Application publication date: 20191115 |