CN106158772A - Plate level embedded packaging structure and preparation method thereof - Google Patents
Plate level embedded packaging structure and preparation method thereof Download PDFInfo
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- CN106158772A CN106158772A CN201510140205.4A CN201510140205A CN106158772A CN 106158772 A CN106158772 A CN 106158772A CN 201510140205 A CN201510140205 A CN 201510140205A CN 106158772 A CN106158772 A CN 106158772A
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- line layer
- circuit board
- chip
- cavity
- opening
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
The invention discloses a kind of plate level embedded packaging structure, including: circuit board；It is located in circuit board, in order to the opening of accommodating semiconductor chip or cavity；It is respectively arranged at first and second line layer on first and second surface of circuit board, and first and second line layer electrically connects through the conductive path running through circuit board, the highest, the minimum surface of first and second line layer surface corresponding circuits plate respectively；Being located at the semiconductor chip in opening or cavity, this chip electrically connects with first line layer through the second line layer, and the I/O bond pad surface of this chip is at least exposed from the second line layer surface, and is in same plane with the minimum surface of circuit board；Encapsulating material, in order to the first surface of covering board, first line layer and the space not occupied by chip in filling opening or cavity.Present invention also offers the method making this plate level embedded packaging structure.The packaging cost of sensor can be greatly reduced by the present invention, reduce encapsulation volume, and effectively promote the performance of sensor.
Description
Technical field
The present invention relates to a kind of circuit board package structure, particularly a kind of plate level embedded packaging structure and preparation method thereof, it can
It is applied to semiconductor chip, especially the envelope of the sensor chip such as capacitive fingerprint sensing device, cmos image sensor (CIS)
Dress.
Background technology
At present, during Wire Bonding Technology is generally applied to the encapsulation process of capacitance type sensor or CIS chip.Such as, existing
It is mutual that capacitance type sensor IC/CIS encapsulation generally uses that Wire Bonding Technology realizes on chip between tactile disk and the internal cabling of encapsulation
Even.Then, in place of these technology all Shortcomings.
I.e. as a example by the encapsulating structure shown in Fig. 1, it at least has a following deficiency:
1, Wire Bonding Technology is that line based on single-chip bonding connects, and for many I/O pad on single-chip (I/O pad) number
Multi-thread bonding be asynchronous, process speed is slow.
2, line defines suitable height with the combination technology that is bonded of line on chip.After fingerprint sensor chip is packed, this
There is the most remote distance between fingerprint and chip by causing, thus have a strong impact on the sensitivity of sensor.
3, using the technology that wire-bond technology and chip are placed on support plate, the thickness of the encapsulating structure ultimately formed is bigger.
4, the cost of this packing forms is high.
Summary of the invention
Present invention is primarily targeted at plate level embedded packaging structure that a kind of improvement is provided and preparation method thereof, existing to overcome
Deficiency in technology.
For realizing aforementioned invention purpose, the technical solution used in the present invention includes:
In one embodiment of this invention, a kind of plate level embedded packaging structure includes:
Circuit board；
Be located in described circuit board, in order to the opening of accommodating semiconductor chip or cavity,
It is respectively arranged at the first surface of described circuit board and the first line layer of second surface and the second line layer, and described first
Line layer and the second line layer electrically connect through the conductive path running through described circuit board, described first line layer surface and the second circuit
The highest face temperature of layer surface corresponding described circuit board respectively and minimum surface；
Being arranged at the semiconductor chip in described opening or cavity, described chip electrically connects with first line layer through the second circuit, and
I/O pad (I/O pad) surface of described chip is at least exposed from described second line layer surface, and with described second line layer
The minimum surface of surface or described circuit board is in same plane；
Encapsulating material, in order in covering the first surface of described circuit board, first line layer and filling described opening or cavity not by
The space that described chip occupies.
As more one of preferred embodiment, the first surface of described circuit board is additionally provided with module para-position mark, at least
For assisting described chip precisely to place.
As more one of preferred embodiment, described first line layer comprises described module para-position mark.
Further, all or part of described module para-position mark can be as connection line and offer conducting function.
Divide as more one of preferred embodiment, described opening or the highest face temperature of cavity in the vertical direction and minimum surface
Wei the highest face temperature of described circuit board or described first line layer surface and the minimum surface of described circuit board or described second circuit
Layer surface, and the border that described opening or cavity are in the horizontal direction is that described circuit board is between first surface and second surface
Opening or the sidewall of cavity, the most described opening or cavity include the first space, second space and the 3rd space, wherein said
One spatial distribution is between the first surface and second surface of described circuit board, and described second space is distributed in the of described circuit board
Between one surface and described first line layer surface, described 3rd spatial distribution is at the second surface and described second of described circuit board
Between line layer surface.
Further, the sidewall in described first space is that the circuit board between described circuit board first surface and second surface cuts continuously
Face, and described second space and the 3rd space are without sidewall.
Further, described semiconductor chip is sensor chip, the sensitive face of described sensor chip and I/O bond pad surface with
Described second line layer surface or the minimum surface copline of described circuit board.
Further, described encapsulating material also may extend to the second surface of covering board.
Further, described plate level embedded packaging structure also includes tertiary circuit layer, arranges on top of the encapsulation material, and through running through
The conductive path of encapsulating material electrically connects with first line layer.
As more one of preferred embodiment, described plate level embedded packaging structure also includes solder mask, in order to cover
State the second surface of circuit board and second, third line layer described and encapsulating material, but the sensitive face of described chip is from covering institute
State in the solder mask of the second line layer and expose.
As more one of preferred embodiment, described plate level embedded packaging structure also includes protective layer, and it is covered the most continuously
Cover the sensitive face of described sensor chip, or cover the solder mask of described circuit board second surface and described sensor the most continuously
The sensitive face of chip.
Further, described plate level embedded packaging structure also includes pad array, its be arranged on covering described tertiary circuit layer and
Electrically connect in the solder mask opening on encapsulating material surface and with described tertiary circuit layer, described pad array include BGA or
Contact array.
In one embodiment of this invention, the manufacture method of described plate level embedded packaging structure includes:
(1) providing circuit board, the first surface of described circuit board and second surface are respectively arranged with first line layer and the second circuit
Layer, described first line layer and the second line layer electrically connect through the conductive path running through described circuit board, and set on described circuit board
It is equipped with the opening for housing semiconductor chip or cavity；
(2) on described second line layer surface, attach adhesive film, and described chip upside down is entered described opening or cavity, and make
The sensitive face of described chip is adhesively fixed with adhesive film；
(3) on the first surface of described circuit board, described first line layer surface and described opening or cavity, encapsulation is at least applied
Material, makes the first surface of described circuit board, the described packed material of first line layer cover, and makes described opening or cavity
Packed material and described chip are filled up completely with；
(4) remove described adhesive film, and rewiring is set on described second line layer surface, thus by sensor chip and
Two line layers electrically connects, and forms tertiary circuit layer on described encapsulating material, and makes tertiary circuit layer and first line layer electricity
Connect；
(5) solder mask is set in the both side surface of step (4) obtained device, but makes the sensitive face of described chip from covering
The solder mask on described circuit board second surface and the second line layer surface exposes, and is covering described tertiary circuit layer and envelope
The solder mask opening on package material surface arranges pad array, and makes described pad array electrically connect with tertiary circuit layer；
As more one of preferred embodiment, the manufacture method of described plate level embedded packaging structure may also include that
(6) at least on the sensitive face of described chip, setting has the masking structures of protective effect.
Further, described masking structures can include described protective layer.
As one of preferred embodiment, described masking structures may also include the sapphire glass being covered on described protective layer.
As one of preferred embodiment, described masking structures may also include infrared glass, and it covers described circuit board the most continuously
The solder mask of second surface and the sensitive face of described sensor chip, and the biography of described infrared glass and described sensor chip
Leave gap between sense face, enable to shine directly into through the light of described infrared glass on the sensitive face of described sensor chip.
Compared with prior art, the present invention at least has the advantage that
1, this plate level embedded packaging structure has high production efficiency and premium properties, and with low cost；
2, the manufacturing process of this plate level embedded packaging structure is the Board level packaging process of high production speed, hence it is evident that be better than based on single
The inefficient production process of sheet bonding connecting line technics；
3, in this plate level embedded packaging structure, the distance between fingerprint sensor and the surface of chip is the least, thus can be effective
Promote the sensitivity of sensor；
4, utilize this plate level embedded packaging structure, the small size encapsulation of sensor can be realized.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the sensor core chip package using Wire Bonding Technology to realize；
Fig. 2 is the top view of the substrate in one embodiment of the invention with first line layer, opening or cavity and wiring board；
Fig. 3 a is laterally cuing open of the substrate that in one embodiment of the invention, one has first line layer, opening or cavity and wiring board
View；
Fig. 3 b is the horizontal of the substrate that in another embodiment of the present invention, one has first line layer, opening or cavity and wiring board
Sectional view；
Fig. 4 a is that in one embodiment of the invention, the longitudinal direction of the substrate that one has first line layer, opening or cavity and wiring board is cutd open
View；
Fig. 4 b is the longitudinal direction of the substrate that one has first line layer, opening or cavity and wiring board in another embodiment of the present invention
Sectional view；
Fig. 5 a-Fig. 5 b is that in one embodiment of the invention, sensor chip is inserted in opening or cavity with the ventricumbent state of sensitive face
Schematic diagram；
Fig. 6 a-Fig. 6 b be with encapsulating material encapsulate the adhesive film in device shown in Fig. 5 b and removal devices and by inverted signal
Figure；
Fig. 7 is the schematic diagram arranging circuit on device shown in Fig. 6 b；
Fig. 8 is the schematic diagram arranging solder mask and BGA on device shown in Fig. 7；
Fig. 9 is a kind of capacitive fingerprint sensor chip-packaging structure schematic diagram in one embodiment of the invention；
Figure 10 is a kind of CIS sensor core chip package schematic diagram in one embodiment of the invention；
Description of reference numerals: the encapsulating structure 100 of fingerprint sensor chip, base plate for packaging 110, semiconductor chip 120, partly lead
Body sensing chip face 121, semiconductor chip sensitive face 123, conductive connecting line 130, packing colloid 140, upper surface of base plate 150,
The sidewall 104 of sidewall 103, opening or the cavity of circuit board 1, first surface 101, second surface 102, opening or cavity,
Opening or cavity the 2, first space 201, second space the 202, the 3rd space 203, module para-position mark 3, module register guide
Know connecting plate 4, landing chassis (landing pad) 5, encapsulating material 6, first line layer 7, first line layer surface 701, the
Two line layers the 8, second line layer surface 801, conductive path 9, adhesive film 10, sensing chip 11, sensitive face 111, I/O
Pad 112, rewiring 12, tertiary circuit layer 13, conductive path 14, solder mask 15, BGA 16, protective layer 17, indigo plant
Cameo glass 18, IR glass 19, gap 20, L-is horizontal, V-is longitudinal.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing, technical scheme is more specifically illustrated.
In one embodiment of this invention, the basic structure of a kind of plate level embedded packaging structure may include that
Circuit board 1, particularly PCB；
First line layer 7 and the second line layer 8, be respectively arranged at first surface 101 and the second surface 102 of described circuit board 1,
And described first line layer and the second line layer electrically connect through the conductive path 9 running through described circuit board；
Sensor chip 11, is arranged in the opening on described circuit board or cavity 2, and described sensor chip 11 and second
Line layer 8 electrically connects, and the most directly electrically connects；
Encapsulating material 6, in order to cover the first surface 101 of described circuit board 1, first line layer and to fill described opening or cavity
In the space that do not occupied by described chip, further, described encapsulating material also may extend to the second surface of covering board 1
102；
Tertiary circuit layer 13, is arranged on encapsulating material 6, and through running through conductive path 14 and the first line layer of encapsulating material
Electrical connection.
Wherein, the sensitive face 111 of described sensor chip 11 at least exposes from described second line layer 8 surface 801, particularly,
It is directly exposed in air.
Further, protection structure also can be set in described encapsulating structure, to cover and to protect the sensitive face of sensor chip.
Further, described protection structure can include protective layer, and it at least covers the sensitive face of described sensor chip.
Further, I/O pad (I/O pad) 112 via line of described sensor chip 11 and the line on the second line layer 8
Road (Trace) electrically connects.Further, the I/O pad surface of described chip and the second line layer surface 801 or described electricity
The minimum surface of road plate is in same plane.
Further, described circuit board 1 surface, particularly it is additionally provided with module para-position mark on circuit board first surface 101, uses
To realize accurate flip-chip layout and conducting wire interconnection.
Further, described first line layer 7 identifies containing module para-position, precisely places for companion chip.
Further, described first line layer 7 identifies 3 containing module para-position, precisely places for companion chip, all marks
Know or portion identification becomes connection line simultaneously and provides conducting function.
And for opening or the cavity 2 for housing described chip, the highest face temperature of its in the vertical direction and minimum surface respectively
For first line layer surface 701 and the highest face temperature on the second line layer surface 801, the most respectively circuit board and minimum surface.With
Time, described opening or cavity 2 border in the horizontal direction are that described circuit board 1 is at first surface 101 and 102, the second table
Between opening or the sidewall 103,104 of cavity.
Further saying, the space of described opening or cavity 2 includes:
First space 201, i.e. opening between circuit board first surface 101 and second surface 102 or void space,
Second space 202, the i.e. first surface, space above to the space on first line layer surface 701 (circuit board highest face temperature),
And, the 3rd space 203, the i.e. first space underlying surfaces is to second layer line layer surface 801 (circuit board minimum surface)
Space.
Further, the sidewall in described first space 201 is the electricity between circuit board first surface 101 and second surface 102
The continuous cross section of road plate, and described second space and the 3rd space are without sidewall.
Further, described plate level embedded packaging structure also includes solder mask 15, in order to cover described circuit board 1 continuously
Second surface 102 and described second, third line layer 8,13 and encapsulating material 6, but the sensitive face 111 of sensor chip 11
Expose in the solder mask covering described circuit board second surface 102.
First line layer 7 and the second line layer 8 are respectively arranged on first, second surface 101,102 of described circuit board 1, and
Described opening or the upper and lower end of cavity 2 are distinguished and corresponded in described first line layer surface 701 and the second line layer surface 801
Face, that is to say highest face temperature and the minimum surface of described circuit board.
In one more specifically case study on implementation, described first line layer also can comprise module para-position mark, accurate in order to realize
Chip layout, this module para-position mark comprises the alignment mark with connection, and this circuit is via conducting path and the second line layer
Circuit interconnection, and/or, module para-position mark be realize precise die arrange para-position mark.
Further, refering to Fig. 2, described module para-position mark can comprise module para-position mark 3, module para-position identifies connecting plate 4,
Landing chassis 5 etc..
Preferably, the sensitive face 111 of described sensor chip 11 and the second circuit surface 801, that is described opening or cavity
Bottom face copline.
Wherein, described first, second, third line layer is preferably formed by materials such as Cu.
Wherein, described tertiary circuit layer 13 also referred to as RDL (rewiring layer), itself and the circuit interconnection on the second line layer.
Further, the conducting path that the sensor chip wrapper circuit containing RDL with first line layer interconnects.
Further, RDL circuit is connected with encapsulation accumulated layers surface.
Further, RDL circuit interconnects through the conducting path through encapsulating material with the circuit on first line layer.
Its complementary space in addition to the region occupied by sensor chip in further, encapsulating material is filled in opening or cavity,
Region more than opening or cavity, is not identified, by circuit and module para-position, the region covered.
Further, the region covering more than first line floor, opening or cavity, the district not covered by circuit and alignment mark
The encapsulating material in territory is an accumulated layers.
Further, solder mask layer covers the RDL in accumulated layers and accumulated layers, but has reserved BGA or LGA region.
Further, solder mask layer covers the second line layer, connects the circuit on I/O pad and the second line layer, not by second
The board area that line layer covers, but do not cover sensing chip face.
Further, aforesaid each conducting path can be conductive blind hole (blind via) or conduction PTH (heavy copper hole, Plating
Through Hole), but it is not limited to this.
Further, described plate level embedded packaging structure also includes protective layer, and it covers described sensor chip the most continuously
Sensitive face, it is preferred that its solder mask covering described circuit board second surface the most continuously and the sensing of described sensor chip
Face.
In one more specifically case study on implementation, described protection structure farther includes the sapphire glass being covered on described protective layer
Glass.
In another more specifically case study on implementation, the described further infrared glass of protection structure, it covers described electricity the most continuously
The solder mask of road plate second surface and the sensitive face of described sensor chip, and described infrared glass and described sensor chip
Sensitive face between leave gap, enable to shine directly into the sensing of described sensor chip through the light of described infrared glass
On face.
Further, described plate level embedded packaging structure also includes pad array, its be arranged on covering described tertiary circuit layer and
Electrically connecting in the solder mask opening on encapsulating material surface and with tertiary circuit layer, described pad array includes BGA (Ball Grid
Array) array or LGA (Land Grid Array) array.
And in one embodiment of this invention, the manufacture method of a kind of plate level embedded packaging structure may include that
(1) providing circuit board 1, first surface 101 and the second surface 102 of described circuit board are respectively arranged with first line layer
7 and second line layer 8, described first line layer 7 and the second line layer 8 electrically connect through the conductive path 9 running through described circuit board,
And on described circuit board 1, it is provided with opening or the cavity 2 of accommodating sensor chip 11, refer to Fig. 2, Fig. 3 a-Fig. 3 b,
Fig. 4 a-Fig. 4 b；
(2) on the second line layer surface 801 of described circuit board 1, adhesive film 10 is attached, and by sensor chip to be inverted
Form inserts described opening or cavity 2, and makes the sensitive face 111 of sensor chip 11 be adhesively fixed with adhesive film 10, refers to
Fig. 5 a and Fig. 5 b；
(3) on the first surface 101 of described circuit board 1 and described opening or cavity 2, at least apply encapsulating material 6, make electricity
First surface 101 and the packed material of first line floor 76 of road plate 1 cover, and make described opening or cavity 2 packed
Material 6 and sensor chip 11 are filled up completely with, and the encapsulating material 6 filled also may extend to the second surface of covering board
102, refer to Fig. 6 a；
In this step, also encapsulating material can be carried out planarizing process.
Wherein, encapsulating material can be molding compounds (Molding compound), epoxy resin, or epoxy resin/filler
Complex etc., it is filled into cavity and covers first line layer as a smooth accumulation horizon.
(4), refer to Fig. 6 b, remove described adhesive film 10, device is overturn, and at the second line layer of described circuit board 1
Rewiring 12 is set on surface 801, thus the I/O pad 112 of sensor chip 11 is electrically connected with the second line layer 8, with
And on described encapsulating material 6, form tertiary circuit layer 13, such as Cu RDL, and make tertiary circuit layer 13 and first line layer
7 electrical connections, refer to Fig. 7；
Wherein, the aforementioned Cu RDL with the circuit link on I/O pad the 112, second circuit 8 surface of chip be by metallization,
Upper photoresistance, photoetching, etching and removing photoresistance are formed.
Further, can be formed blind hole by laser boring, then copper facing forms Cu layer, finally goes up photoresistance, photoetching, erosion
Carve and removing photoresistance and form pattern and circuit.
(5) solder mask 15 is set in the both side surface of step (4) obtained device, but makes the sensing of sensor chip 11
Face 111 is exposed in the solder mask covering described circuit board 1 second surface 102, and is covering described circuit board the first table
BGA 16 or contact array are set on the solder mask in face 101, and make described BGA or contact array and tertiary circuit
Layer 13 electrical connection, refers to Fig. 8；
Wherein, solder mask can be formed by coating or compound, photoetching and annealing, and covers both side surface except sensor chip 11
Sensitive face 111 and corresponding to BGA or LGA opening outside region.
(6) at least on the sensitive face 111 of described sensor chip 11, setting has the masking structures of protective effect；
Such as, in a case study on implementation, refer to Fig. 9, protective layer 17 is set at device surface so that it is cover institute the most continuously
State the solder mask 15 of circuit board second surface 102 and the sensitive face 111 of described sensor chip 11, and at described protective layer
On cover sapphire glass 18 or other similar material.This encapsulating structure is suitable to the encapsulation of capacitive fingerprint sensor etc..
The most such as, in another case study on implementation, refer to Figure 10, use infrared glass 19 to cover described circuit board the most continuously
The solder mask 15 of second surface 102 and the sensitive face 111 of described sensor chip, and described infrared glass and described sensing
Leave gap 20 between the sensitive face of device chip, enable to shine directly into described sensor core through the light of described infrared glass
On the sensitive face 111 of sheet.This encapsulating structure is suitable to the encapsulation of CIS (CMOS Image Sensor) sensor etc..
The design utilizing the present invention can be greatly reduced the packaging cost of sensor, reduces encapsulation volume, and also can effectively promote
The performance of sensor, such as, is substantially improved its sensitivity.
Should be appreciated that above-described embodiment is only technology design and the feature of the explanation present invention, its object is to allow and be familiar with technique
Personage will appreciate that present disclosure and implement according to this, can not limit the scope of the invention with this.All according to this
The equivalence that bright spirit is made changes or modifies, and all should contain within protection scope of the present invention.
Claims (14)
1. a plate level embedded packaging structure, it is characterised in that including:
Circuit board；
Be located in described circuit board, at least in order to opening or the cavity of accommodating semiconductor chip,
It is respectively arranged at the first surface of described circuit board and the first line layer of second surface and the second line layer, and described first
Line layer and the second line layer electrically connect through the conductive path running through described circuit board, described first line layer surface and the second circuit
The highest face temperature of layer surface corresponding described circuit board respectively and minimum surface；
Being arranged at the semiconductor chip in described opening or cavity, described chip electrically connects with first line layer through the second line layer,
And the I/O bond pad surface of described chip at least exposes from described second line layer surface, and with described second line layer surface or institute
The minimum surface stating circuit board is in same plane；
Encapsulating material, at least in order to cover the first surface of described circuit board, first line layer and to fill in described opening or cavity
The space not occupied by described chip.
Plate level embedded packaging structure the most according to claim 1, it is characterised in that on the first surface of described circuit board also
It is provided with module para-position mark, is at least used for assisting described chip precisely to place.
Plate level embedded packaging structure the most according to claim 2, it is characterised in that described first line layer comprises described mould
Block para-position identifies.
4. according to the plate level embedded packaging structure described in Claims 2 or 3, it is characterised in that all or part of described module
Para-position mark can be as connection line and offer conducting function.
Plate level embedded packaging structure the most according to claim 1, it is characterised in that described opening or cavity are at vertical direction
On highest face temperature and minimum surface be respectively the highest face temperature of described circuit board or described first line layer surface and described circuit board
Minimum surface or described second line layer surface, and the border that described opening or cavity are in the horizontal direction is described circuit board exists
Opening between first surface and second surface or the sidewall of cavity, the most described opening or cavity include the first space, the second sky
Between and the 3rd space, wherein said first spatial distribution between the first surface and second surface of described circuit board, described second
Spatial distribution is between the first surface and described first line layer surface of described circuit board, and described 3rd spatial distribution is at described electricity
Between second surface and the described second line layer surface of road plate.
Plate level embedded packaging structure the most according to claim 5, it is characterised in that the sidewall in described first space is described
The continuous cross section of circuit board between circuit board first surface and second surface, and described second space and the 3rd space are without sidewall.
7. according to the plate level embedded packaging structure according to any one of claim 1-3,5-6, it is characterised in that described quasiconductor
Chip is sensor chip, the sensitive face of described sensor chip and I/O bond pad surface and described second line layer surface or described
The minimum surface copline of circuit board.
Plate level embedded packaging structure the most according to claim 1, it is characterised in that described encapsulating material also extends to cover
The second surface of described circuit board.
9. according to the plate level embedded packaging structure according to any one of claim 1-3,5-6, it is characterised in that also include the 3rd
Line layer, it arranges on top of the encapsulation material, and electrically connects with first line layer through running through the conductive path of encapsulating material.
Plate level embedded packaging structure the most according to claim 9, it is characterised in that also include solder mask, in order to cover
Cover the second surface of described circuit board and second, third line layer described and encapsulating material, but the sensitive face of described chip is from covering
Cover in the solder mask of described second line layer and expose.
11. plate level embedded packaging structures according to claim 10, it is characterised in that also including protective layer, it at least connects
The continuous sensitive face covering described sensor chip.
12. plate level embedded packaging structures according to claim 10, it is characterised in that also include pad array, it is arranged
Electrically connect in covering the solder mask opening on described tertiary circuit layer and encapsulating material surface and with described tertiary circuit layer, described
Pad array includes BGA or contact array.
The manufacture method of plate level embedded packaging structure according to any one of 13. claim 1-12, it is characterised in that including:
(1) providing circuit board, the first surface of described circuit board and second surface are respectively arranged with first line layer and the second circuit
Layer, described first line layer and the second line layer electrically connect through the conductive path running through described circuit board, and set on described circuit board
It is equipped with at least for housing opening or the cavity of semiconductor chip；
(2) on described second line layer surface, attach adhesive film, and described chip is inserted described opening or cavity, and make institute
The sensitive face stating chip is adhesively fixed with adhesive film；
(3) on the first surface of described circuit board, described first line layer surface and described opening or cavity, encapsulation is at least applied
Material, makes the first surface of described circuit board, the packed material of first line layer cover, and makes described opening or cavity be sealed
Package material and described chip are filled up completely with；
(4) remove described adhesive film, and rewiring be set on the second surface of described circuit board, thus by sensor chip with
Second line layer electrical connection, and on described encapsulating material, form tertiary circuit layer, and make tertiary circuit layer and first line layer
Electrical connection；
(5) solder mask is set in the both side surface of step (4) obtained device, but makes the sensitive face of described chip from covering
The solder mask on described circuit board second surface and the second line layer surface exposes, and is covering described tertiary circuit layer and envelope
The solder mask opening on package material surface arranges pad array, and makes described pad array electrically connect with tertiary circuit layer.
The manufacture method of plate level embedded packaging structure described in 14. claim 13, it is characterised in that also include:
(6) at least on the sensitive face of described chip, setting has the masking structures of protective effect.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449554A (en) * | 2016-12-06 | 2017-02-22 | 苏州源戍微电子科技有限公司 | Chip embedded packaging structure with sealed cavity and manufacturing method of structure |
| CN106531711A (en) * | 2016-12-07 | 2017-03-22 | 华进半导体封装先导技术研发中心有限公司 | Chip board-level packaging structure and manufacturing method |
| CN108649041A (en) * | 2018-04-16 | 2018-10-12 | 复旦大学 | A kind of chip-packaging structure and its method based on composite interconnection substrate |
| KR20180113885A (en) * | 2017-04-07 | 2018-10-17 | 삼성전기주식회사 | Fan-out sensor package and optical-type fingerprint sensor module |
| CN108831875A (en) * | 2018-08-10 | 2018-11-16 | 付伟 | Filter chip embeds and the encapsulating structure and preparation method thereof of electrode peripheral hardware |
| CN109075137A (en) * | 2017-07-20 | 2018-12-21 | 深圳市汇顶科技股份有限公司 | Chip-packaging structure, chip module and electric terminal |
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| US10644046B2 (en) | 2017-04-07 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out sensor package and optical fingerprint sensor module including the same |
| CN111261526A (en) * | 2020-01-19 | 2020-06-09 | 华为技术有限公司 | Packaging structure and preparation method thereof |
| WO2021016838A1 (en) * | 2019-07-30 | 2021-02-04 | 深圳市汇顶科技股份有限公司 | Image sensor and manufacturing method therefor, chip, and handheld apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364579A (en) * | 2007-08-10 | 2009-02-11 | 三星电子株式会社 | Semiconductor package, method of manufacturing the same and system containing the package |
| CN101859752A (en) * | 2009-04-06 | 2010-10-13 | 杨文焜 | Stack package structure and manufacture method thereof with chip embedded and silicon through hole crystal grain |
| US20110240354A1 (en) * | 2010-03-31 | 2011-10-06 | Ibiden Co., Ltd. | Wiring board and method for manufacturing wiring board |
| CN204424252U (en) * | 2015-03-27 | 2015-06-24 | 蔡亲佳 | The embedding formula Board level packaging structure of semiconductor chip |
-
2015
- 2015-03-27 CN CN201510140205.4A patent/CN106158772B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364579A (en) * | 2007-08-10 | 2009-02-11 | 三星电子株式会社 | Semiconductor package, method of manufacturing the same and system containing the package |
| CN101859752A (en) * | 2009-04-06 | 2010-10-13 | 杨文焜 | Stack package structure and manufacture method thereof with chip embedded and silicon through hole crystal grain |
| US20110240354A1 (en) * | 2010-03-31 | 2011-10-06 | Ibiden Co., Ltd. | Wiring board and method for manufacturing wiring board |
| CN204424252U (en) * | 2015-03-27 | 2015-06-24 | 蔡亲佳 | The embedding formula Board level packaging structure of semiconductor chip |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN106449554B (en) * | 2016-12-06 | 2019-12-17 | 苏州源戍微电子科技有限公司 | chip embedded packaging structure with closed cavity and manufacturing method thereof |
| CN106531711A (en) * | 2016-12-07 | 2017-03-22 | 华进半导体封装先导技术研发中心有限公司 | Chip board-level packaging structure and manufacturing method |
| CN106531711B (en) * | 2016-12-07 | 2019-03-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of the Board level packaging structure and production method of chip |
| KR102019353B1 (en) * | 2017-04-07 | 2019-09-09 | 삼성전자주식회사 | Fan-out sensor package and optical-type fingerprint sensor module |
| US11037971B2 (en) | 2017-04-07 | 2021-06-15 | Samsung Electronics Co., Ltd. | Fan-out sensor package and optical fingerprint sensor module including the same |
| KR20180113885A (en) * | 2017-04-07 | 2018-10-17 | 삼성전기주식회사 | Fan-out sensor package and optical-type fingerprint sensor module |
| US10644046B2 (en) | 2017-04-07 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out sensor package and optical fingerprint sensor module including the same |
| CN109075137A (en) * | 2017-07-20 | 2018-12-21 | 深圳市汇顶科技股份有限公司 | Chip-packaging structure, chip module and electric terminal |
| EP3454363A4 (en) * | 2017-07-20 | 2019-08-21 | Shenzhen Goodix Technology Co., Ltd. | Chip package structure, chip module, and electronic terminal |
| US10854526B2 (en) | 2017-07-20 | 2020-12-01 | Shenzhen GOODIX Technology Co., Ltd. | Chip packaging structure, chip module and electronic terminal |
| CN109075137B (en) * | 2017-07-20 | 2022-03-01 | 深圳市汇顶科技股份有限公司 | Chip packaging structure, chip module and electronic terminal |
| CN108649041B (en) * | 2018-04-16 | 2021-01-26 | 复旦大学 | Chip packaging structure based on composite interconnection substrate and method thereof |
| CN108649041A (en) * | 2018-04-16 | 2018-10-12 | 复旦大学 | A kind of chip-packaging structure and its method based on composite interconnection substrate |
| CN108831875A (en) * | 2018-08-10 | 2018-11-16 | 付伟 | Filter chip embeds and the encapsulating structure and preparation method thereof of electrode peripheral hardware |
| CN108831875B (en) * | 2018-08-10 | 2024-03-05 | 浙江熔城半导体有限公司 | Packaging structure with embedded filter chip and external electrode and manufacturing method thereof |
| CN109494163A (en) * | 2018-11-20 | 2019-03-19 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of chip |
| CN109768026A (en) * | 2018-12-20 | 2019-05-17 | 西安华为技术有限公司 | Flush type substrate and preparation method thereof |
| WO2021016838A1 (en) * | 2019-07-30 | 2021-02-04 | 深圳市汇顶科技股份有限公司 | Image sensor and manufacturing method therefor, chip, and handheld apparatus |
| CN111261526A (en) * | 2020-01-19 | 2020-06-09 | 华为技术有限公司 | Packaging structure and preparation method thereof |
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Effective date of registration: 20200612 Address after: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Patentee after: Zhejiang Rongcheng Semiconductor Co., Ltd Address before: Suzhou City, Jiangsu province 215000 Suzhou Industrial Park South Pavilion rain Street No. 18 building 6 room 1503 apartment essence Patentee before: Cai Qinjia |