CN109494163A - The encapsulating structure and packaging method of chip - Google Patents
The encapsulating structure and packaging method of chip Download PDFInfo
- Publication number
- CN109494163A CN109494163A CN201811382629.1A CN201811382629A CN109494163A CN 109494163 A CN109494163 A CN 109494163A CN 201811382629 A CN201811382629 A CN 201811382629A CN 109494163 A CN109494163 A CN 109494163A
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- chip
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- packaging layer
- electrical contact
- contact end
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 163
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000005520 cutting process Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000010329 laser etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000009467 reduction Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 238000005538 encapsulation Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of encapsulating structure and packaging methods, technical solution of the present invention uses the package substrate with through-hole to be packaged chip, first chip is set in through-hole, the first chip is fixed with package substrate by the first plastic packaging layer, the first plastic packaging layer in the second surface, the back side of first chip and the through-hole is covered by the second plastic packaging layer, to form encapsulating structure, device architecture is simple.First chip can be electrically connected by the first contact jaw of package substrate with external circuit, be electrically connected convenient for the first chip with external circuit.And, the first chip and the first plastic packaging layer in through-hole are carried by the second plastic packaging layer, when encapsulating structure is under pressure close to the side of the first chip front side, the pressure can be buffered by the second plastic packaging layer, to avoid the back side periphery of first chip and the second plastic packaging layer intersection Problem of Failure as caused by the pressure.
Description
Technical field
The present invention relates to chip encapsulation technology fields, saying more, are related to encapsulating structure and the encapsulation side of a kind of chip
Method.
Background technique
With the continuous development of science and technology, more and more electronic equipments are widely used in daily life
And in work, huge convenience is brought for daily life and work, it is indispensable to become current people
Important tool.
Electronic equipment realizes that the main component of preset function is chip, with being constantly progressive for integrated circuit technique, chip
Integrated level it is higher and higher, the function of chip is stronger and stronger, and the size of chip is smaller and smaller, thus chip needs pass through envelope
Dress forms encapsulating structure, in order to which chip is electrically connected with external circuit.
It is chip package that a kind of simple chip-packaging structure of structure, which is designed, in order to which chip is electrically connected with external circuit
Technical field urgent problem to be solved.
Summary of the invention
In view of this, it is simple structure can be formed the invention discloses a kind of encapsulating structure of chip and packaging method
Chip-packaging structure, and be electrically connected with external circuit convenient for chip.
To achieve the goals above, the present invention provides following scheme:
A kind of encapsulating structure of chip, the encapsulating structure include:
Package substrate, the package substrate include opposite first surface and second surface, run through the first surface
And the through-hole of the second surface, the second surface are provided with the first electrical contact end, first electrical contact end be used for
External circuit electrical connection；
First chip arranged in the through hole, first chip have opposite front and the back side, front
With chip functions unit and the weld pad being electrically connected with the chip functions unit, the weld pad and first electrical contact end
Electrical connection；Its back side is close to the second surface, and front is close to the first surface, and the through-hole is exposed in its front；
First plastic packaging layer, the first plastic packaging layer cover the first surface, fill the through-hole, and expose the chip
Functional unit；
Second plastic packaging layer, the second plastic packaging layer cover the second surface, the back side of first chip and described
The first plastic packaging layer in through-hole.
Preferably, in above-mentioned encapsulating structure, further includes: the second chip in the through-hole has on the contrary just
Face and the back side, the back side is close to the second surface, and front is close to the first surface；
Wherein, second chip is electrically connected with corresponding first electrical contact end.
Preferably, in above-mentioned encapsulating structure, the first plastic packaging layer covers the front of second chip；Described second
Plastic packaging layer covers the back side of second chip.
Preferably, in above-mentioned encapsulating structure, the back side of first chip is flushed with the second surface；
The back side of second chip is flushed with the second surface.
Preferably, in above-mentioned encapsulating structure, the first surface is provided with the second electrical contact end, first electrical contact
It holds and is electrically connected with second electrical contact end by the interconnection circuit being located in the package substrate, the weld pad and described second
Electrical contact end electrical connection.
Preferably, in above-mentioned encapsulating structure, the weld pad is electrically connected by conducting wire with second electrical contact end.
Preferably, in above-mentioned encapsulating structure, the front of first chip includes boss and the encirclement boss
Groove；The chip functions unit is located at the boss surface, and the weld pad is located at the bottom of the groove.
Preferably, in above-mentioned encapsulating structure, the second plastic packaging layer is the dry film that fitting is fixed on the second surface,
The dry film is capsulation material.
Preferably, in above-mentioned encapsulating structure, the second plastic packaging layer is formed by laser etching process exposes described the
The opening of one electrical contact end.
Preferably, in above-mentioned encapsulating structure, the first plastic packaging layer is formed by mold injection, described after demoulding
One plastic packaging layer has the opening for exposing the chip functions unit.
Preferably, in above-mentioned encapsulating structure, the first plastic packaging layer is formed by no mold injection, passes through reduction processing
Expose the opening of the chip functions unit.
The present invention also provides a kind of packaging method of chip, the packaging method includes:
One substrate is provided, the substrate includes multiple package substrates, there is cutting channel between the adjacent package substrate,
The package substrate includes opposite first surface and second surface, through the first surface and the second surface
Through-hole, the second surface are provided with the first electrical contact end, and first electrical contact end with external circuit for being electrically connected；
First chip is set in the through-hole, and first chip has opposite front and the back side, positive mask
The weld pad for having chip functions unit and being electrically connected with the functional unit, the weld pad are electrically connected with first electrical contact end
It connects；Its back side is close to the second surface, and front is close to the first surface, and the through-hole is exposed in its front；
The first plastic packaging layer is formed, the first plastic packaging layer covers the first surface, fills the through-hole, and described in exposing
Chip functions unit；
Form the second plastic packaging layer, the second plastic packaging layer cover the second surface, first chip the back side and
The first plastic packaging layer in the through-hole；
Divide the first plastic packaging layer, the substrate and the second plastic packaging layer based on the cutting channel.
Preferably, in above-mentioned packaging method, before forming the first plastic packaging layer, further includes:
Second chip is set in the through-hole, there is opposite front and back, the back side close to the second surface,
Its front is close to the first surface；
Wherein, second chip is electrically connected with corresponding first electrical contact end.
Preferably, in above-mentioned packaging method, the first plastic packaging layer covers the front of second chip；Described second
Plastic packaging layer covers the back side of second chip.
Preferably, in above-mentioned packaging method, the back side of first chip is flushed with the second surface；
The back side of second chip is flushed with the second surface.
Preferably, in above-mentioned packaging method, the first surface is provided with the second electrical contact end, first electrical contact
It holds and is electrically connected with second electrical contact end by the interconnection circuit being located in the package substrate, the weld pad and described second
Electrical contact end electrical connection.
Preferably, in above-mentioned packaging method, the weld pad is electrically connected by conducting wire with second electrical contact end.
Preferably, in above-mentioned packaging method, the front of first chip includes boss and the encirclement boss
Groove；The chip functions unit is located at the boss surface, and the weld pad is located at the bottom of the groove.
Preferably, in above-mentioned packaging method, the second plastic packaging layer of the formation includes:
It is bonded fixed dry film in the second surface, the dry film is capsulation material.
Preferably, in above-mentioned packaging method, the second plastic packaging layer of the formation includes:
The opening for exposing first electrical contact end is formed on the second plastic packaging layer by laser etching process.
Preferably, in above-mentioned packaging method, the first plastic packaging layer of the formation includes:
The first plastic packaging layer is formed by mold injection, the first plastic packaging layer after demoulding, which has, exposes the chip
The opening of functional unit.
Preferably, in above-mentioned packaging method, the first plastic packaging layer is formed by no mold injection, passes through reduction processing
Form the opening for exposing the chip functions unit.
In the encapsulating structure and packaging method of the chip that technical solution of the present invention provides, using the encapsulation base with through-hole
Plate is packaged chip, and the first chip is arranged in through-hole, is carried out the first chip and package substrate by the first plastic packaging layer
It is fixed, the first modeling in the second surface, the back side of first chip and the through-hole is covered by the second plastic packaging layer
Sealing, to form encapsulating structure, device architecture is simple.First chip can be by the first contact jaw of package substrate and external
Circuit electrical connection, is electrically connected convenient for the first chip with external circuit.Moreover, carrying the in through-hole by the second plastic packaging layer
One chip and the first plastic packaging layer pass through described second when encapsulating structure is under pressure close to the side of the first chip front side
Plastic packaging layer can buffer the pressure, thus avoid first chip back side periphery and the second plastic packaging layer intersection by
The Problem of Failure caused by the pressure improves reliability.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 2 is the front plan view of encapsulating structure shown in Fig. 1；
Fig. 3 is the schematic diagram of the encapsulating structure of another chip provided in an embodiment of the present invention；
Fig. 4 is the front plan view that encapsulation is dismissed shown in Fig. 3；
Fig. 5-Figure 14 is a kind of flow diagram of packaging method provided in an embodiment of the present invention；
Figure 15-Figure 21 is the flow diagram of another packaging method provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
With reference to Fig. 1 and Fig. 2, Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided in an embodiment of the present invention, and Fig. 2 is
The front plan view of encapsulating structure shown in Fig. 1.The encapsulating structure includes: package substrate 12, and the package substrate 12 includes opposite
First surface and second surface, set through the first surface and the through-hole T of the second surface, the second surface
It is equipped with the first electrical contact end 121, first electrical contact end 121 with external circuit for being electrically connected；It is arranged in the through-hole
The first chip 11, first chip 11 have opposite front and the back side, front have chip functions unit and
The weld pad 112 being electrically connected with the chip functions unit, the weld pad 112 are electrically connected with first electrical contact end 121, back
Face is close to the second surface, and front is close to the first surface, and the through-hole T is exposed in its front.Is not shown in Fig. 1
The chip functions unit of one chip 11.The first plastic packaging layer 13 is not shown in Fig. 2, in order to the front knot of clear diagram encapsulating structure
Structure.
The encapsulating structure further includes the first plastic packaging layer 13 and the second plastic packaging layer 14.The first plastic packaging layer 13 covers institute
First surface is stated, fills the through-hole T, and expose the chip functions unit.The second plastic packaging layer 14 covers described second
Surface, the back side of first chip 11 and the first plastic packaging layer 13 in the through-hole T.
In encapsulating structure described in the embodiment of the present invention, chip is packaged using the package substrate 12 with through-hole T,
First chip 11 is set in through-hole T, first chip 11 is fixed with package substrate 12 by the first plastic packaging layer 13, by the
Two plastic packaging layers 14 cover the second surface, the back side of first chip 11 and the first plastic packaging layer 13 in the through-hole T,
To form encapsulating structure, device architecture is simple.First chip 11 can by the first contact jaw 121 of package substrate 12 with it is outer
The electrical connection of portion's circuit, is electrically connected convenient for the first chip 11 with external circuit.Moreover, carrying through-hole by the second plastic packaging layer 14
The first chip 11 and the first plastic packaging layer 13 in T, when encapsulating structure is under pressure close to the positive side of the first chip 11,
The pressure can be buffered by the second plastic packaging layer 14, to avoid the back side periphery and described the of first chip 11
Two plastic packaging layers, 13 intersection Problem of Failure as caused by the pressure improves reliability, and such as the first chip 11 is fingerprint chip,
In fingerprint detection, user's touch operation can apply pressure in the front of encapsulating structure, seal using described in technical solution of the present invention
Assembling structure, can be to avoid Problem of Failure caused by the pressure, to guarantee the reliability of fingerprint detection.
Optionally, the first surface is provided with the second electrical contact end 123, first electrical contact end 121 and described the
Two electrical contact ends 123 are electrically connected by the interconnection circuit 122 being located in the package substrate 12, the weld pad 112 and described the
Two electrical contact ends 123 electrical connection, so that the weld pad 112 passes through second electrical contact end 123 and the interconnection circuit
122 are electrically connected with first electrical contact end 121.
As shown in Figure 1, the weld pad 112 is electrically connected by conducting wire 15 with second electrical contact end 123.Conducting wire can be
Gold thread or other plain conductors.The front that first chip 11 is arranged includes boss 111 and the encirclement boss 111
Groove；The chip functions unit is located at the boss surface, and the weld pad 112 is located at the bottom of the groove.In this way, when logical
When crossing the electrical connection weld pad 112 of conducting wire 15 and the second electrical contact end 123, the height of conducting wire 15 can be made to be no more than boss 111
Surface controls the height of conducting wire 15 under 111 surface of boss, can use the first plastic packaging layer 13 of lower thickness will in this way
Conducting wire 15 seals.
Optionally, the second plastic packaging layer 14 is the dry film that fitting is fixed on the second surface, and the dry film is plastic packaging
Material can directly fit the second surface for being fixed on the package substrate 12.The second plastic packaging layer 14 can pass through laser
Etching technics forms the opening 141 for exposing first electrical contact end 121, in order to the first electrical contact end 121 and external circuit
Electrical connection.
The first plastic packaging layer 13 can be set and expose the chip functions unit, in order to which flip chip functional unit is held
Row preset function, as shown in Figure 1, the first plastic packaging layer 13 exposes the boss 111 of the first chip 11, to expose the chip functions list
Member, and cover the positive groove of the first chip 11.A kind of mode can form the first plastic packaging layer 13 by mold injection, take off
The first plastic packaging layer 13 after mould has the opening for exposing the chip functions unit.Which directly passes through mold injection shape
At the first plastic packaging layer 13.Another way can form the first plastic packaging layer 13 by no mold injection, by being thinned
The opening of the chip functions unit is exposed in processing.
With reference to Fig. 3 and Fig. 4, Fig. 3 is the schematic diagram of the encapsulating structure of another chip provided in an embodiment of the present invention, Fig. 4
To encapsulate the front plan view dismissed shown in Fig. 3, in encapsulating structure mode shown in Fig. 1, further includes: be located at the through-hole T
The second interior chip 21, the second chip 21 have opposite front and back, and the back side is leaned on close to the second surface, front
The nearly first surface；Wherein, second chip 21 is electrically connected with corresponding first electrical contact end 123.Equally, Fig. 4
In the first plastic packaging layer 13 is not shown, in order to it is clear diagram encapsulating structure Facad structure.
The thickness of second chip 21 is less than the thickness of first chip 11.In this way, first modeling can be set
Sealing 13 covers the front of second chip 21；The second plastic packaging layer 14 covers the back side of second chip 21.Also
It is to say, completely can be sealed the front of the second chip 21 by the first plastic packaging layer 13, completely will by the second plastic packaging layer
The back side of second chip 21 is sealed.The back side that the second chip 21 and the first chip 11 can be set flushes, and the two back side
The second surface of uniform package substrate 12 flushes, when being packaged in this way to the two, in order to placement of the two in through-hole T and
It is fixed.
First chip 11 and the second chip 21 are electrically connected the second different electrical contact ends 123, to pass through different the
One electrical contact end 121 is electrically connected with external circuit.It can be based on circuit demand for interconnection, the first chip 11 and second can also be set
Chip 21 is electrically connected by corresponding lead 15.As 21 front of the second chip has weld pad 211, the positive part weldering of the first chip 11
Pad 112 and the corresponding electrical connection of the positive part of solder pads 211 of the second chip 21.
As can be seen from the above description, encapsulating structure described in the embodiment of the present invention passes through the first plastic packaging layer 13, the second plastic packaging layer
14 and package substrate 12 chip is packaged, structure is simple, low manufacture cost.But also by being located at package substrate 12
The pressure that second plastic packaging layer buffering package structure front of second surface is subject to, thus avoid in through-hole T chip back periphery with
The problem of first plastic packaging layer boundary position is due to pressure failure.But also two chips, encapsulation can be encapsulated simultaneously in through-hole T
The thinner thickness of structure.
Based on the above embodiment, a kind of packaging method of chip, the encapsulation side are additionally provided in another embodiment of the present invention
Method can be used for making encapsulating structure described in above-described embodiment, and for the packaging method as shown in Fig. 5-Figure 14, Fig. 5-Figure 14 is this hair
A kind of flow diagram for packaging method that bright embodiment provides, the packaging method include:
Step S11: as shown in Figure 5 and Figure 6, a substrate 10 is provided.
The substrate 10 includes multiple package substrates 12, has cutting channel 100, institute between the adjacent package substrate 12
Stating package substrate 12 includes opposite first surface and second surface, through the first surface and the second surface
Through-hole T, the second surface are provided with the first electrical contact end 121, and first electrical contact end 121 with external circuit for being electrically connected
It connects；
Step S12: as shown in Figure 7 and Figure 8, the first chip 11 is set in the through-hole T.
First chip 11 have opposite front and the back side, front have chip functions unit and with it is described
The weld pad 112 of functional unit electrical connection, the weld pad 112 are electrically connected with first electrical contact end 121；Its back side is close to described
Second surface, front is close to the first surface, and the through-hole T is exposed in its front.
In the step, first as shown in fig. 7, being fixed temporarily loading plate 31 at the back side of substrate 10, loading plate will be fixed with
31 substrate 10 is horizontal positioned, and the first surface of each package substrate 12 is placed upward.Then, as shown in figure 8, in each through-hole
One first chip 11 is respectively set in 31 surface of loading plate in T, and chip 11 is electrically connected with corresponding package substrate 12.
The first surface is provided with the second electrical contact end 123, first electrical contact end 123 and second electrical contact
End 121 is electrically connected by the interconnection circuit 122 being located in the package substrate 12, the weld pad 112 and second electrical contact
123 electrical connection of end.Optionally, the weld pad 112 is electrically connected by conducting wire 15 with second electrical contact end 123.Described first
The front of chip 11 includes boss 111 and the groove for surrounding the boss, and the chip functions unit is located at the boss table
Face, the weld pad 112 is located at the bottom of the groove, in order to reduce the height of conducting wire 15.
Step S13: as shown in Figure 9 and Figure 10, the first plastic packaging layer 13 is formed, the first plastic packaging layer 13 covers described first
The through-hole T is filled, and exposes the chip functions unit in surface.
In the step, the first plastic packaging layer 13 of the formation includes: firstly, as shown in figure 9, forming institute by no mold injection
The first plastic packaging layer 14 is stated, the first plastic packaging layer 14 covers the front of the first chip 11 and the first surface of package substrate 12, then,
As shown in Figure 10, the opening for exposing the chip functions unit is formed by reduction processing.In other modes, also directly to pass through
Mold injection forms the first plastic packaging layer 13, and the first plastic packaging layer 13 after demoulding, which has, exposes the chip functions unit
Opening.
Step S14: as shown in figures 11-13, the second plastic packaging layer 14 is formed, the second plastic packaging layer 14 covers described second
Surface, the back side of first chip 11 and the first plastic packaging layer 13 in the through-hole T；
In the step, the second plastic packaging layer 14 of the formation includes: to be bonded fixed dry film, the dry film in the second surface
For capsulation material.
In the step, the second plastic packaging layer 14 of the formation includes: first as shown in figure 11, loading plate 31 to be removed, by substrate
It is inverted, so that the second surface of each package substrate 12 is upward, then as shown in figure 12, forms the second plastic packaging at the back side of substrate
Layer, finally, as shown in figure 13, being formed on the second plastic packaging layer 14 by laser etching process and exposing first electrical contact
The opening 141 at end 121.
Step S15: as shown in figure 14, the first plastic packaging layer 13, the substrate 10 are divided based on the cutting channel 100
And the second plastic packaging layer 14.
By packaging method shown in Fig. 5-Figure 14, encapsulating structure as depicted in figs. 1 and 2 can be made.
Encapsulating structure as shown in Figure 3 and Figure 4 is such as made, packaging method can be as shown in Figure 15-Figure 21, and Figure 15-Figure 21 is
The flow diagram of another kind packaging method provided in an embodiment of the present invention, which is with above method difference,
Formed before the first plastic packaging layer 13, further includes: the second chip 21 is set in the through-hole T, have opposite front and
The back side, the back side is close to the second surface, and front is close to the first surface；Wherein, second chip 21 with it is corresponding
First electrical contact end 121 electrical connection.The first plastic packaging layer 13 covers the front of second chip 21；Described second
Plastic packaging layer 21 covers the back side of second chip 21.The back side of first chip 11 is flushed with the second surface；It is described
The back side of second chip 21 is flushed with the second surface.
Specifically, as shown in figure 15, the first chip 11 and the second chip 21, the first chip 11 is arranged simultaneously in through-hole T
Thickness be greater than the thickness of the second chip 21, the chip functions unit of the first chip 11 exposes through-hole T, the second chip 21 without departing from
Through-hole T.Two chips can be electrically connected by conducting wire 15 and package substrate respectively.Then, as shown in figure 16, the first plastic packaging is formed
Layer 13, the first plastic packaging layer 13 cover the first surface of two chip front sides and package substrate 12.Again as shown in figure 17, by subtracting
The chip functions unit of the first chip 11 is exposed in thin processing.For another example shown in Figure 18-Figure 20, the second envelope is formed at 10 back side of substrate
Layer 14 is filled, forming process is same as mentioned above, and details are not described herein.Finally, as shown in figure 21, cutting forms multiple encapsulation knots
Structure.
Packaging method described in the embodiment of the present invention can be used for making encapsulating structure described in above-described embodiment, simple process,
Low manufacture cost.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For being encapsulated disclosed in embodiment
For method, since it is corresponding with encapsulating structure disclosed in embodiment, so being described relatively simple, related place is referring to envelope
Assembling structure relevant portion explanation.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (22)
1. a kind of encapsulating structure of chip, which is characterized in that the encapsulating structure includes:
Package substrate, the package substrate include opposite first surface and second surface, through the first surface and
The through-hole of the second surface, the second surface are provided with the first electrical contact end, and first electrical contact end is used for and outside
Circuit electrical connection；
First chip arranged in the through hole, first chip have opposite front and the back side, and front has
Chip functions unit and the weld pad being electrically connected with the chip functions unit, the weld pad are electrically connected with first electrical contact end
It connects；Its back side is close to the second surface, and front is close to the first surface, and the through-hole is exposed in its front；
First plastic packaging layer, the first plastic packaging layer cover the first surface, fill the through-hole, and expose the chip functions
Unit；
Second plastic packaging layer, the second plastic packaging layer cover the second surface, the back side of first chip and the through-hole
The first interior plastic packaging layer.
2. encapsulating structure according to claim 1, which is characterized in that further include: the second chip in the through-hole,
With opposite front and back, the back side is close to the second surface, and front is close to the first surface；
Wherein, second chip is electrically connected with corresponding first electrical contact end.
3. encapsulating structure according to claim 2, which is characterized in that the first plastic packaging layer covers second chip
Front；The second plastic packaging layer covers the back side of second chip.
4. encapsulating structure according to claim 3, which is characterized in that the back side of first chip and the second surface
It flushes；
The back side of second chip is flushed with the second surface.
5. encapsulating structure according to claim 1, which is characterized in that the first surface is provided with the second electrical contact end,
First electrical contact end is electrically connected with second electrical contact end by the interconnection circuit being located in the package substrate, described
Weld pad is electrically connected with second electrical contact end.
6. encapsulating structure according to claim 5, which is characterized in that the weld pad passes through conducting wire and second electrical contact
End electrical connection.
7. encapsulating structure according to claim 1, which is characterized in that the front of first chip includes boss and packet
Enclose the groove of the boss；The chip functions unit is located at the boss surface, and the weld pad is located at the bottom of the groove.
8. encapsulating structure according to claim 1, which is characterized in that the second plastic packaging layer is that fitting is fixed on described the
The dry film on two surfaces, the dry film are capsulation material.
9. encapsulating structure according to claim 1, which is characterized in that the second plastic packaging layer passes through laser etching process shape
At the opening for exposing first electrical contact end.
10. encapsulating structure according to claim 1, which is characterized in that the first plastic packaging layer is formed by mold injection,
The first plastic packaging layer after demoulding has the opening for exposing the chip functions unit.
11. encapsulating structure according to claim 1, which is characterized in that form first plastic packaging by no mold injection
Layer, the opening of the chip functions unit is exposed by reduction processing.
12. a kind of packaging method of chip, which is characterized in that the packaging method includes:
A substrate is provided, the substrate includes multiple package substrates, has cutting channel between the adjacent package substrate, described
Package substrate includes opposite first surface and second surface, through the logical of the first surface and the second surface
Hole, the second surface are provided with the first electrical contact end, and first electrical contact end with external circuit for being electrically connected；
First chip is set in the through-hole, and first chip has opposite front and the back side, and front has core
Piece functional unit and the weld pad being electrically connected with the functional unit, the weld pad are electrically connected with first electrical contact end；Its
The back side is close to the second surface, and front is close to the first surface, and the through-hole is exposed in its front；
The first plastic packaging layer is formed, the first plastic packaging layer covers the first surface, fills the through-hole, and expose the chip
Functional unit；
Form the second plastic packaging layer, the second plastic packaging layer covers the second surface, the back side of first chip and described
The first plastic packaging layer in through-hole；
Divide the first plastic packaging layer, the substrate and the second plastic packaging layer based on the cutting channel.
13. packaging method according to claim 12, which is characterized in that before forming the first plastic packaging layer, also wrap
It includes:
Second chip is set in the through-hole, there is opposite front and back, the back side is close to the second surface, just
Face is close to the first surface；
Wherein, second chip is electrically connected with corresponding first electrical contact end.
14. packaging method according to claim 13, which is characterized in that the first plastic packaging layer covers second chip
Front；The second plastic packaging layer covers the back side of second chip.
15. packaging method according to claim 14, which is characterized in that the back side of first chip and second table
Face flushes；
The back side of second chip is flushed with the second surface.
16. packaging method according to claim 12, which is characterized in that the first surface is provided with the second electrical contact
End, first electrical contact end are electrically connected with second electrical contact end by the interconnection circuit being located in the package substrate,
The weld pad is electrically connected with second electrical contact end.
17. packaging method according to claim 16, which is characterized in that the weld pad is connect by conducting wire and second electricity
Contravention electrical connection.
18. packaging method according to claim 12, which is characterized in that the front of first chip include boss and
Surround the groove of the boss；The chip functions unit is located at the boss surface, and the weld pad is located at the bottom of the groove
Portion.
19. packaging method according to claim 12, which is characterized in that the second plastic packaging layer of the formation includes:
It is bonded fixed dry film in the second surface, the dry film is capsulation material.
20. packaging method according to claim 12, which is characterized in that the second plastic packaging layer of the formation includes:
The opening for exposing first electrical contact end is formed on the second plastic packaging layer by laser etching process.
21. packaging method according to claim 12, which is characterized in that the first plastic packaging layer of the formation includes:
The first plastic packaging layer is formed by mold injection, the first plastic packaging layer after demoulding, which has, exposes the chip functions
The opening of unit.
22. packaging method according to claim 12, which is characterized in that form first plastic packaging by no mold injection
Layer forms the opening for exposing the chip functions unit by reduction processing.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811382629.1A CN109494163A (en) | 2018-11-20 | 2018-11-20 | The encapsulating structure and packaging method of chip |
| PCT/CN2019/118167 WO2020103747A1 (en) | 2018-11-20 | 2019-11-13 | Chip packaging structure |
| PCT/CN2019/118170 WO2020103748A1 (en) | 2018-11-20 | 2019-11-13 | Chip packaging structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811382629.1A CN109494163A (en) | 2018-11-20 | 2018-11-20 | The encapsulating structure and packaging method of chip |
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| Publication Number | Publication Date |
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| CN109494163A true CN109494163A (en) | 2019-03-19 |
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| CN201811382629.1A Pending CN109494163A (en) | 2018-11-20 | 2018-11-20 | The encapsulating structure and packaging method of chip |
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| CN (1) | CN109494163A (en) |
| WO (2) | WO2020103748A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020103748A1 (en) * | 2018-11-20 | 2020-05-28 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and method |
| CN111276450A (en) * | 2020-02-22 | 2020-06-12 | 多感科技(上海)有限公司 | Chip module and forming method thereof |
| CN112635436A (en) * | 2020-12-17 | 2021-04-09 | 长江存储科技有限责任公司 | Chip packaging structure and preparation method thereof |
| WO2022165958A1 (en) * | 2021-02-05 | 2022-08-11 | 天芯互联科技有限公司 | Chip packaging method and chip packaging mechanism |
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| WO2020103747A1 (en) | 2020-05-28 |
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Application publication date: 20190319 |