WO2020103748A1

WO2020103748A1 - Chip packaging structure and method

Info

Publication number: WO2020103748A1
Application number: PCT/CN2019/118170
Authority: WO
Inventors: 王之奇; 张�成
Original assignee: 苏州晶方半导体科技股份有限公司
Priority date: 2018-11-20
Filing date: 2019-11-13
Publication date: 2020-05-28
Also published as: CN109494163A; WO2020103747A1

Abstract

A chip packaging structure and method. A package substrate (12) having a through hole (T) is used for packaging a chip; a first chip (11) is disposed in the through hole (T); the first chip (11) and the package substrate (12) are fixed by means of a first plastic packaging layer (13); a second surface of the packaging substrate (12), the back surface of the first chip (11), and the first plastic packaging layer (13) in the through hole (T) are covered by a second plastic packaging layer (14). Thus, a package structure is formed, and the device has a simple structure. The first chip (11) can be electrically connected to an external circuit by means of a first contact end (121) of the package substrate (12), so that the first chip (11) is electrically connected to the external circuit. Moreover, the first chip (11) and the first plastic packaging layer (13) in the through hole (T) are borne by means of the second plastic packaging layer (14); when the side of the package structure close to the front surface of the first chip (11) is under pressure, the second plastic packaging layer (14) can buffer the pressure, thereby avoiding the problem of failure at the junction of the back periphery of the first chip (11) and the second plastic packaging layer (14) due to the pressure.

Description

Chip packaging structure and packaging method

This disclosure requires the priority of the Chinese patent application filed on November 20, 2018 with the Chinese Patent Office and the application number 201811382629.1. The entire contents of the above applications are incorporated by reference in this disclosure.

Technical field

The present application relates to the field of chip packaging technology, for example, to a chip packaging structure and packaging method.

Background technique

With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and becomes an indispensable important thing for people today. tool.

The main component of the electronic device to realize the preset function is the chip. With the continuous progress of integrated circuit technology, the integration of the chip is getting higher and higher, the function of the chip is getting stronger, and the size of the chip is getting smaller and smaller, so the chip needs Through packaging, a packaging structure is formed, so that the chip is electrically connected to an external circuit.

Designing a chip packaging structure with a simple structure to facilitate electrical connection between the chip and an external circuit is an urgent problem to be solved in the field of chip packaging technology.

Summary of the invention

The present application discloses a chip packaging structure and a packaging method, which can form a chip packaging structure with a simple structure and facilitate the electrical connection between the chip and an external circuit.

This application provides the following solutions:

A packaging structure of a chip, the packaging structure includes:

A package substrate, the package substrate including opposite first surfaces and second surfaces, through holes penetrating the first surface and the second surface, the second surface is provided with a first electrical contact end, the first An electrical contact is used for electrical connection with external circuits;

A first chip provided in the through hole, the first chip having opposite front and back sides, the front side of which has a chip functional unit and a pad electrically connected to the chip functional unit, the pad and the The first electrical contact end is electrically connected; its rear side is close to the second surface, its front side is close to the first surface, and its front side exposes the through hole;

A first plastic encapsulation layer, the first plastic encapsulation layer covers the first surface, fills the through hole, and exposes the chip functional unit;

A second plastic encapsulation layer covering the second surface, the back surface of the first chip, and the first plastic encapsulation layer in the through hole.

This application also provides a chip packaging method, including:

A base is provided. The base includes a plurality of packaging substrates with a cutting channel between adjacent packaging substrates. The packaging substrate includes opposite first surfaces and second surfaces that extend through the first surfaces and the A through hole on the second surface, the second surface is provided with a first electrical contact end, the first electrical contact end is used for electrical connection with an external circuit;

A first chip is provided in the through hole, the first chip has opposite front and back sides, the front side has a chip functional unit and a pad electrically connected to the functional unit, the pad and the first The electrical contact ends are electrically connected; the back surface is close to the second surface, the front surface is close to the first surface, and the front surface exposes the through hole;

Forming a first plastic encapsulation layer, the first plastic encapsulation layer covering the first surface, filling the through hole, and exposing the chip functional unit;

Forming a second plastic encapsulation layer, the second plastic encapsulation layer covering the second surface, the back surface of the first chip, and the first plastic encapsulation layer in the through hole;

The first plastic encapsulation layer, the substrate, and the second plastic encapsulation layer are divided based on the cutting channel.

BRIEF DESCRIPTION

FIG. 1 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

2 is a front plan view of the packaging structure shown in FIG. 1;

3 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application;

FIG. 4 is a front plan view of the package dismissal shown in FIG. 3;

5 to 14 are schematic flowcharts of a packaging method provided by an embodiment of the present application;

15-21 are schematic flowcharts of another packaging method provided by an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. 1 and 2, FIG. 1 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application, and FIG. 2 is a front plan view of the packaging structure shown in FIG. 1. The packaging structure includes: a packaging substrate 12 including opposite first and second surfaces, a through hole T penetrating through the first surface and the second surface, the second surface being provided with a An electrical contact 121, the first electrical contact 121 is used for electrical connection with an external circuit; a first chip 11 disposed in the through hole, the first chip 11 has opposite front and back sides, the front side It has a chip functional unit and a pad 112 electrically connected to the chip functional unit, the pad 112 is electrically connected to the first electrical contact 121, its back is close to the second surface, and its front is close to the first One surface, and the front surface of the through hole T is exposed. The chip functional unit of the first chip 11 is not shown in FIG. 1. The first plastic encapsulation layer 13 is not shown in FIG. 2 in order to clearly illustrate the front structure of the packaging structure.

The packaging structure further includes a first plastic encapsulation layer 13 and a second plastic encapsulation layer 14. The first molding layer 13 covers the first surface, fills the through hole T, and exposes the chip functional unit. The second plastic encapsulation layer 14 covers the second surface, the back surface of the first chip 11 and the first plastic encapsulation layer 13 in the through hole T.

In the packaging structure described in the embodiment of the present application, a package substrate 12 having a through hole T is used to package the chip, a first chip 11 is provided in the through hole T, and the first chip 11 and the packaging substrate 12 are connected by a first plastic encapsulation layer 13 For fixing, the second plastic encapsulation layer 14 covers the second surface, the back surface of the first chip 11 and the first plastic encapsulation layer 13 in the through hole T, thereby forming a packaging structure, and the device structure is simple. The first chip 11 may be electrically connected to an external circuit through the first contact end 121 of the packaging substrate 12, so that the first chip 11 is electrically connected to the external circuit. Furthermore, the second plastic encapsulation layer 14 carries the first chip 11 and the first plastic encapsulation layer 13 in the through-hole T. When the side of the packaging structure close to the front surface of the first chip 11 is pressed, 14 can buffer the pressure, thereby avoiding the failure problem caused by the pressure at the boundary between the back edge of the first chip 11 and the second plastic encapsulation layer 13 and improving reliability. For example, if the first chip 11 is a fingerprint chip, During fingerprint detection, the user's touch operation will exert pressure on the front of the packaging structure. Using the packaging structure described in the technical solution of this application can avoid the failure problem caused by the pressure, thereby ensuring the reliability of fingerprint detection.

The first surface is provided with a second electrical contact end 123, the first electrical contact end 121 and the second electrical contact end 123 are electrically connected by an interconnection circuit 122 located in the packaging substrate 12, the pad 112 is electrically connected to the second electrical contact 123 so that the pad 112 is electrically connected to the first electrical contact 121 through the second electrical contact 123 and the interconnect circuit 122.

As shown in FIG. 1, the bonding pad 112 is electrically connected to the second electrical contact end 123 through a wire 15. The wire can be gold wire or other metal wire. The front surface of the first chip 11 includes a boss 111 and a groove surrounding the boss 111; the chip functional unit is located on the surface of the boss, and the bonding pad 112 is located on the bottom of the groove. In this way, when the bonding pad 112 and the second electrical contact end 123 are electrically connected through the wire 15, the height of the wire 15 can not exceed the surface of the boss 111, and the height of the wire 15 can be controlled below the surface of the boss 111, so that The first plastic encapsulation layer 13 with a thinner thickness is used to seal the wire 15.

The second plastic encapsulation layer 14 is a dry film that is adhered and fixed on the second surface. The dry film is a plastic encapsulation material and can be directly adhered and fixed on the second surface of the packaging substrate 12. The second plastic encapsulation layer 14 may form an opening 141 exposing the first electrical contact 121 through a laser etching process, so as to facilitate electrical connection between the first electrical contact 121 and an external circuit.

The first plastic encapsulation layer 13 may be disposed to expose the chip functional unit, so as to trigger the chip functional unit to perform a preset function. As shown in FIG. 1, the first plastic encapsulation layer 13 exposes the boss 111 of the first chip 11 to expose The chip functional unit covers the groove on the front surface of the first chip 11. In one way, the first plastic encapsulation layer 13 may be formed by injection molding in a mold, and the first plastic encapsulation layer 13 after demolding has an opening exposing the chip functional unit. In this way, the first plastic encapsulation layer 13 is formed by injection molding directly. In another way, the first plastic encapsulation layer 13 may be formed by moldless injection, and the opening of the chip functional unit may be exposed through a thinning process.

Referring to FIGS. 3 and 4, FIG. 3 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application, and FIG. 4 is a front plan view of the package dismissal shown in FIG. 3, which is in the manner shown in FIG. 1, Also includes: a second chip 21 located in the through-hole T, the second chip 21 has opposite front and back surfaces, the back surface is close to the second surface, and the front surface is close to the first surface; wherein, the first The two chips 21 are electrically connected to the corresponding first electrical contact terminals 123. Similarly, the first molding layer 13 is not shown in FIG. 4 in order to clearly illustrate the front structure of the packaging structure.

The thickness of the second chip 21 is smaller than the thickness of the first chip 11. In this way, the first plastic encapsulation layer 13 may be provided to cover the front surface of the second chip 21; the second plastic encapsulation layer 14 covers the back surface of the second chip 21. In other words, the front surface of the second chip 21 can be completely sealed by the first molding compound layer 13 and the back surface of the second chip 21 can be completely sealed by the second molding compound layer. The back surfaces of the second chip 21 and the first chip 11 may be flush with each other, and the back surface of the package substrate 12 is evenly flush with each other, so that when the two are packaged, it is convenient for the two to be placed in the through hole T And fixed.

The first chip 11 and the second chip 21 are respectively electrically connected to different second electrical contacts 123 to be electrically connected to external circuits through different first electrical contacts 121. Based on circuit interconnection requirements, the first chip 11 and the second chip 21 may also be electrically connected through corresponding wires 15. If the second chip 21 has a pad 211 on the front side, the partial pad 112 on the front side of the first chip 11 and the partial pad 211 on the front side of the second chip 21 are electrically connected correspondingly.

It can be known from the above description that the packaging structure described in the embodiment of the present application encapsulates the chip through the first plastic encapsulation layer 13, the second plastic encapsulation layer 14 and the packaging substrate 12. The structure is simple and the manufacturing cost is low. Furthermore, the pressure on the front of the packaging structure is buffered by the second plastic encapsulation layer on the second surface of the packaging substrate 12, so as to avoid the problem of pressure failure at the boundary between the back edge of the chip in the through hole T and the first plastic encapsulation layer. Moreover, two chips can be packaged in the through hole T at the same time, and the thickness of the package structure is relatively thin.

Based on the above embodiment, another embodiment of the present application also provides a chip packaging method. The packaging method can be used to fabricate the packaging structure described in the above embodiment. The packaging method is shown in FIGS. 5-14. 5- FIG. 14 is a schematic flowchart of a packaging method according to an embodiment of the present application. The packaging method includes:

Step S11: As shown in FIGS. 5 and 6, a substrate 10 is provided.

The base 10 includes a plurality of packaging substrates 12 with a cutting channel 100 between adjacent packaging substrates 12. The packaging substrate 12 includes opposite first surfaces and second surfaces that penetrate the first surfaces and all A through hole T on the second surface, the second surface is provided with a first electrical contact end 121, and the first electrical contact end 121 is used for electrical connection with an external circuit;

Step S12: As shown in FIGS. 7 and 8, the first chip 11 is disposed in the through hole T.

The first chip 11 has opposite front and back sides, and the front side has a chip functional unit and a pad 112 electrically connected to the functional unit, the pad 112 is electrically connected to the first electrical contact 121; The back side is close to the second surface, the front side is close to the first surface, and the front side exposes the through hole T.

In this step, first, as shown in FIG. 7, the carrier board 31 is temporarily fixed on the back surface of the base 10, the base 10 to which the carrier board 31 is fixed is placed horizontally, and the first surface of each package substrate 12 is placed upward. Then, as shown in FIG. 8, a first chip 11 is provided on the surface of the carrier board 31 in each through hole T, and the chip 11 is electrically connected to the corresponding package substrate 12.

The first surface is provided with a second electrical contact end 123, the first electrical contact end 123 and the second electrical contact end 121 are electrically connected through an interconnection circuit 122 located in the packaging substrate 12, the pad 112 is electrically connected to the second electrical contact terminal 123. The bonding pad 112 is electrically connected to the second electrical contact end 123 through the wire 15. The front surface of the first chip 11 includes a boss 111 and a groove surrounding the boss, the chip functional unit is located on the surface of the boss, and the bonding pad 112 is located on the bottom of the groove to facilitate lowering The height of the wire 15.

Step S13: As shown in FIGS. 9 and 10, a first plastic encapsulation layer 13 is formed. The first plastic encapsulation layer 13 covers the first surface, fills the through hole T, and exposes the chip functional unit.

In this step, the forming of the first plastic encapsulation layer 13 includes: first, as shown in FIG. 9, the first plastic encapsulation layer 14 is formed by moldless injection, and the first plastic encapsulation layer 14 covers the front surface of the first chip 11 and the packaging substrate The first surface of 12, and then, as shown in FIG. 10, an opening exposing the chip functional unit is formed through a thinning process. In other methods, the first plastic encapsulation layer 13 is also formed by injection molding directly through a mold, and the first plastic encapsulation layer 13 after demolding has an opening exposing the chip functional unit.

Step S14: As shown in FIGS. 11-13, a second plastic encapsulation layer 14 is formed, the second plastic encapsulation layer 14 covering the second surface, the back surface of the first chip 11 and the first in the through hole T A plastic seal layer 13;

In this step, the forming of the second plastic sealing layer 14 includes: bonding and fixing a dry film on the second surface, the dry film being a plastic sealing material.

In this step, the forming of the second plastic encapsulation layer 14 includes: first, as shown in FIG. 11, the carrier plate 31 is removed, and the base is inverted so that the second surface of each packaging substrate 12 faces upward, and then as shown in FIG. 12, in A second plastic encapsulation layer is formed on the back of the substrate. Finally, as shown in FIG. 13, an opening 141 is formed in the second plastic encapsulation layer 14 through the laser etching process to expose the first electrical contact 121.

Step S15: As shown in FIG. 14, the first plastic encapsulation layer 13, the substrate 10 and the second plastic encapsulation layer 14 are divided based on the cutting channel 100.

Through the packaging methods shown in FIGS. 5-14, the packaging structures shown in FIGS. 1 and 2 can be manufactured.

If the packaging structure shown in FIGS. 3 and 4 is manufactured, the packaging method may be shown in FIGS. 15-21. FIG. 15-21 is a schematic flowchart of another packaging method provided by an embodiment of the present application. The above method differs in that, before forming the first plastic encapsulation layer 13, it further includes: providing a second chip 21 in the through hole T, having opposite front and back surfaces, the back surface of which is close to the second surface and the front surface Close to the first surface; wherein, the second chip 21 is electrically connected to the corresponding first electrical contact 121. The first plastic encapsulation layer 13 covers the front side of the second chip 21; the second plastic encapsulation layer 21 covers the back side of the second chip 21. The back surface of the first chip 11 is flush with the second surface; the back surface of the second chip 21 is flush with the second surface.

As shown in FIG. 15, the first chip 11 and the second chip 21 are provided in the through hole T at the same time, the thickness of the first chip 11 is greater than the thickness of the second chip 21, the chip functional unit of the first chip 11 is exposed through the through hole T, The second chip 21 does not exceed the through hole T. The two chips may be electrically connected to the packaging substrate through wires 15 respectively. Then, as shown in FIG. 16, a first molding compound layer 13 is formed, and the first molding compound layer 13 covers the two chip front surfaces and the first surface of the package substrate 12. As shown in FIG. 17 again, through the thinning process, the chip functional unit of the first chip 11 is exposed. As shown in FIGS. 18-20, the second encapsulation layer 14 is formed on the back of the substrate 10, and the forming process is the same as the above method, which will not be repeated here. Finally, as shown in FIG. 21, cutting to form a plurality of packaging structures.

The packaging method described in the embodiments of the present application can be used to fabricate the packaging structure described in the above embodiments, the process is simple, and the manufacturing cost is low.

In the chip packaging structure and packaging method provided by the present application, a package substrate having a through hole is used to package the chip, a first chip is provided in the through hole, and the first chip and the package substrate are fixed by a first plastic encapsulation layer. The second plastic encapsulation layer covers the second surface, the back surface of the first chip, and the first plastic encapsulation layer in the through hole, thereby forming a packaging structure, and the device structure is simple. The first chip may be electrically connected to the external circuit through the first contact end of the packaging substrate, so as to facilitate the electrical connection between the first chip and the external circuit. Moreover, the second plastic encapsulation layer carries the first chip and the first plastic encapsulation layer in the through hole, and when the side of the packaging structure close to the front surface of the first chip is under pressure, the second plastic encapsulation layer can buffer the pressure In order to avoid the failure problem caused by the pressure at the boundary between the back edge of the first chip and the second molding layer, and improve the reliability.

The embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments may refer to each other. For the packaging method disclosed in the embodiment, since it corresponds to the packaging structure disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the relevant part of the packaging structure.

It should also be noted that in this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations There is any such actual relationship or order. Moreover, the terms "including", "comprising" or any other variant thereof are intended to cover non-exclusive inclusions, such that an article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed Or it also includes elements inherent to such articles or equipment. Without more restrictions, the element defined by the sentence "include one ..." does not exclude that there are other identical elements in the article or device that includes the above elements.

Claims

A chip packaging structure, including:

A package substrate, the package substrate including opposite first surfaces and second surfaces, through holes penetrating the first surface and the second surface, the second surface is provided with a first electrical contact end, the first An electrical contact is used for electrical connection with external circuits;

A first chip provided in the through hole, the first chip having opposite front and back sides, the front side of which has a chip functional unit and a pad electrically connected to the chip functional unit, the pad and the The first electrical contact end is electrically connected; its rear side is close to the second surface, its front side is close to the first surface, and its front side exposes the through hole;

A first plastic encapsulation layer, the first plastic encapsulation layer covers the first surface, fills the through hole, and exposes the chip functional unit;

A second plastic encapsulation layer covering the second surface, the back surface of the first chip, and the first plastic encapsulation layer in the through hole.
The packaging structure of a chip according to claim 1, further comprising: a second chip located in the through hole, having opposite front and back surfaces, the back surface is close to the second surface, and the front surface is close to the first surface ;

Wherein, the second chip is electrically connected to the corresponding first electrical contact terminal.
The chip packaging structure according to claim 2, wherein the first plastic encapsulation layer covers the front surface of the second chip; and the second plastic encapsulation layer covers the back surface of the second chip.
The chip packaging structure according to claim 3, wherein the back surface of the first chip is flush with the second surface;

The back surface of the second chip is flush with the second surface.
The packaging structure of a chip according to claim 1, wherein the first surface is provided with a second electrical contact end, the first electrical contact end and the second electrical contact end pass through the The interconnection circuit is electrically connected, and the pad is electrically connected to the second electrical contact end.
The chip packaging structure according to claim 5, wherein the bonding pad is electrically connected to the second electrical contact terminal through a wire.
The chip packaging structure according to claim 1, wherein the front surface of the first chip includes a boss and a groove surrounding the boss; the chip functional unit is located on the surface of the boss, and the bonding pad Located at the bottom of the groove.
The packaging structure of a chip according to claim 1, wherein the second plastic encapsulation layer is a dry film attached and fixed on the second surface, and the dry film is a plastic encapsulation material.
The packaging structure of a chip according to claim 1, wherein the second plastic encapsulation layer forms an opening exposing the first electrical contact end through a laser etching process.
The chip packaging structure according to claim 1, wherein the first plastic encapsulation layer is formed by injection molding of a mold, and the first plastic encapsulation layer after demolding has an opening exposing the chip functional unit.
The chip packaging structure according to claim 1, wherein the first plastic encapsulation layer is formed by moldless injection, and the opening of the chip functional unit is exposed by a thinning process.
A chip packaging method includes:

A base is provided. The base includes a plurality of packaging substrates with a cutting channel between adjacent packaging substrates. The packaging substrate includes opposite first surfaces and second surfaces that extend through the first surfaces and the A through hole on the second surface, the second surface is provided with a first electrical contact end, the first electrical contact end is used for electrical connection with an external circuit;

A first chip is provided in the through hole, the first chip has opposite front and back sides, the front side has a chip functional unit and a pad electrically connected to the functional unit, the pad and the first The electrical contact ends are electrically connected; the back surface is close to the second surface, the front surface is close to the first surface, and the front surface exposes the through hole;

Forming a first plastic encapsulation layer, the first plastic encapsulation layer covering the first surface, filling the through hole, and exposing the chip functional unit;

Forming a second plastic encapsulation layer, the second plastic encapsulation layer covering the second surface, the back surface of the first chip, and the first plastic encapsulation layer in the through hole;

The first plastic encapsulation layer, the substrate, and the second plastic encapsulation layer are divided based on the cutting channel.
The method for packaging a chip according to claim 12, wherein, before forming the first plastic encapsulation layer, the method further comprises:

A second chip is provided in the through hole, having opposite front and back surfaces, the back surface is close to the second surface, and the front surface is close to the first surface;

Wherein, the second chip is electrically connected to the corresponding first electrical contact terminal.
The method for packaging a chip according to claim 13, wherein the first plastic encapsulation layer covers the front surface of the second chip; and the second plastic encapsulation layer covers the back surface of the second chip.
The chip packaging method according to claim 14, wherein the back surface of the first chip is flush with the second surface;

The back surface of the second chip is flush with the second surface.
The method for packaging a chip according to claim 12, wherein the first surface is provided with a second electrical contact terminal, and the first electrical contact terminal and the second electrical contact terminal pass through a The interconnection circuit is electrically connected, and the pad is electrically connected to the second electrical contact end.
The chip packaging method according to claim 16, wherein the bonding pad is electrically connected to the second electrical contact terminal through a wire.
The method for packaging a chip according to claim 12, wherein the front surface of the first chip includes a boss and a groove surrounding the boss; the chip functional unit is located on the surface of the boss, and the bonding pad Located at the bottom of the groove.
The method for packaging a chip according to claim 12, wherein the forming of the second plastic encapsulation layer comprises:

A dry film is attached and fixed on the second surface, and the dry film is a plastic sealing material.
The method for packaging a chip according to claim 12, wherein the forming of the second plastic encapsulation layer comprises:

An opening exposing the first electrical contact is formed on the second plastic encapsulation layer through a laser etching process.
The method of packaging a chip according to claim 12, wherein the forming of the first plastic encapsulation layer comprises:

The first plastic encapsulation layer is formed by injection molding with a mold, and the first plastic encapsulation layer after demolding has an opening exposing the chip functional unit.
The method of packaging a chip according to claim 12, wherein the first plastic encapsulation layer is formed by moldless injection molding, and an opening exposing the chip functional unit is formed by a thinning process.