CN114883206A - Chip packaging method and chip packaging mechanism - Google Patents
Chip packaging method and chip packaging mechanism Download PDFInfo
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- CN114883206A CN114883206A CN202110164514.0A CN202110164514A CN114883206A CN 114883206 A CN114883206 A CN 114883206A CN 202110164514 A CN202110164514 A CN 202110164514A CN 114883206 A CN114883206 A CN 114883206A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 64
- 230000007246 mechanism Effects 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims description 31
- 239000011347 resin Substances 0.000 claims description 31
- 239000002390 adhesive tape Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 19
- 239000003822 epoxy resin Substances 0.000 claims description 17
- 229920000647 polyepoxide Polymers 0.000 claims description 17
- 238000002679 ablation Methods 0.000 claims description 7
- 238000007650 screen-printing Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000003698 laser cutting Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000005553 drilling Methods 0.000 claims description 4
- 238000004080 punching Methods 0.000 claims description 2
- 238000009489 vacuum treatment Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000002313 adhesive film Substances 0.000 description 3
- 238000010891 electric arc Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000005007 epoxy-phenolic resin Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention discloses a chip packaging method and a chip packaging mechanism, wherein the chip packaging method comprises the following steps: obtaining a chip and a substrate, wherein the substrate is provided with at least one through hole; covering the first film layer on the opening at one side of the through hole; placing a chip into the through hole from the opening on the other side of the through hole; thermosetting filling is carried out on the through hole from the opening on the other side of the through hole so as to fill the gap between the chip and the through hole; and removing the first film layer. By the chip packaging method, the periphery of the chip can be wrapped and packaged, and the stability and reliability of chip packaging are improved.
Description
Technical Field
The invention is applied to the technical field of chip packaging, in particular to a chip packaging method and a chip packaging mechanism.
Background
The chip is a product of semiconductor devices, which is also called microcircuits, microchips, and integrated circuits. Refers to a silicon chip containing integrated circuits, which is small in size and is often part of a computer or other electronic device. While semiconductors are a generic term for a class of materials, integrated circuits are large collections of circuits made of semiconductor materials, and chips are products formed of different types of integrated circuits or a single type of integrated circuit.
At present, direct bare chip welding is generally adopted when a chip is used on a solar cell panel, after the bare chip is welded, the arc discharge phenomenon is easy to occur when the side surface of the chip is electrified with forward current, so that the electrical property of a product is influenced, and meanwhile, the bare chip is easy to cause collision damage in daily carrying and using processes, so that the service life and the performance of the chip are influenced.
Disclosure of Invention
The invention provides a chip packaging method and a chip packaging mechanism, which aim to solve the problem of performance damage caused by exposure of a chip in the prior art and provide better structural protection for the chip.
In order to solve the technical problem, the invention provides a chip packaging method, which comprises the following steps: obtaining a chip and a substrate, wherein the substrate is provided with at least one through hole; covering a first film layer on one side opening of the through hole; placing the chip into the through hole from the opening on the other side of the through hole; thermosetting filling is carried out on the through hole from the opening on the other side of the through hole so as to fill the gap between the chip and the through hole; and removing the first film layer.
The step of obtaining the chip and the substrate, wherein the substrate is provided with at least one through hole, comprises: obtaining a chip and a resin plate; at least one through hole is manufactured on the resin plate by laser cutting, mechanical die punching or mechanical drilling, wherein the size of the through hole is larger than that of the chip.
Wherein the step of covering the first film layer on the opening of one side of the through hole comprises: and attaching a high-temperature adhesive tape to one side of the substrate so as to cover the opening on one side of the through hole through the high-temperature adhesive tape.
Wherein the step of placing the chip into the via from the other side opening of the via comprises: and placing the chip into the hole groove of the through hole from the opening at the other side of the through hole through a chip mounting machine, so that the first surface of the chip is attached to the high-temperature adhesive tape.
The step of performing thermosetting filling on the through hole from the other side opening of the through hole to fill up the gap between the chip and the through hole comprises: and filling epoxy resin into the through hole from the opening on the other side of the through hole by using a screen printing machine so as to fill the gap between the chip and the through hole.
Wherein the step of thermosetting filling the through hole from the other side opening of the through hole to fill the gap between the chip and the through hole comprises the following steps: and removing the filling material on the other side of the substrate by etching or ablation until the second surface of the chip is exposed.
The step of performing thermosetting filling on the through hole from the other side opening of the through hole to fill up the gap between the chip and the through hole comprises: attaching a second film layer on the first surface of the chip; coating epoxy resin on the substrate from the opening on the other side of the through hole by using a screen printing machine; carrying out vacuum treatment on the substrate to enable epoxy resin to fill the gap between the chip and the through hole; and removing the second film layer.
Wherein the step of removing the first film layer further comprises: and cutting the substrate based on the number and the positions of the through holes to obtain the independent packaging mechanism of the chip.
In order to solve the above technical problem, the present invention further provides a chip packaging mechanism, where the chip packaging mechanism includes: a chip; the filling layer is attached to the periphery of the chip; and the substrate frame surrounds the periphery of the filling layer and is attached to the filling layer.
The first surface and the second surface of the chip are exposed.
The invention has the beneficial effects that: different from the situation of the prior art, the chip packaging method provided by the invention has the advantages that the chip and the substrate provided with at least one through hole are obtained, the first film layer is covered on the opening on one side of the through hole, then the chip is placed into the through hole from the opening on the other side of the through hole, the through hole is subjected to thermosetting filling from the opening on the other side of the through hole so as to fill the gap between the chip and the through hole, and finally the first film layer is removed, so that the chip packaging mechanism is obtained. According to the invention, the two layers of coating and fixing around the chip are realized through the substrate and the thermosetting filling, so that the periphery of the chip is protected, and the stability and reliability of the chip packaging mechanism are improved.
Drawings
FIG. 1 is a flow chart illustrating a method for packaging a chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of another embodiment of a chip packaging method provided by the present invention;
fig. 3 is a schematic structural diagram of a packaging mechanism of the chip after step S23 in the embodiment of fig. 2;
fig. 4 is a schematic structural diagram of a packaging mechanism of the chip after step S24 in the embodiment of fig. 2;
fig. 5 is a schematic structural diagram of an embodiment of a packaging mechanism of a chip according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a chip packaging method according to an embodiment of the present invention.
Step S11: and obtaining the chip and the substrate, wherein at least one through hole is formed in the substrate.
And acquiring a chip and a substrate which need to be packaged, wherein the substrate is provided with at least one through hole for accommodating the chip. The number of the through holes on the substrate may be set based on the size between the substrate and the chip in practical application, and is not limited herein.
In a specific application scenario, when the substrate is provided with a plurality of through holes, the through holes can be arrayed and arranged at intervals, so that the subsequent chips can be independently divided.
In a specific application scenario, when the chip is circular, the through hole may also be circular. In another specific application scenario, when the chip is square, the through hole may also be square.
In a specific application scenario, the thickness of the substrate may be smaller than or equal to the thickness of the chip, so as to facilitate the exposure of the upper and lower surfaces of the chip for soldering.
Step S12: and covering the first film layer on the opening at one side of the through hole.
And covering the first film layer on the opening at one side of the through hole on the substrate, and attaching the first film layer to the substrate. The first film layer may be an adhesive film with adhesive force and high temperature resistance, such as a high temperature adhesive tape. And covering the first film layer on the opening at one side of the through hole on the substrate to close the opening at one side of the through hole on the substrate.
Step S13: and placing the chip into the through hole from the opening at the other side of the through hole.
And placing the chip into the through hole from the other side of the through hole without covering the opening of the first film layer. At this time, since the opening on one side of the through hole is covered with the first film layer, the chip can not fall off from the through hole.
In a specific application scenario, after the chip is placed into the through hole from the opening on the other side of the through hole, the bottom of the chip is attached to the first film layer.
Step S14: and performing thermosetting filling on the through hole from the opening on the other side of the through hole so as to fill the gap between the chip and the through hole.
And performing thermosetting filling on the through hole from the opening on the other side of the through hole so as to fill the gap between the chip and the through hole. The thermosetting filling material may include a liquid organic insulating material such as epoxy resin, phenolic resin, or unsaturated polyester, and the like, which is not limited herein.
The gap between the chip and the through hole is filled with the thermosetting filling material, so that the periphery of the chip is coated with the thermosetting filling material, and the relative position between the chip and the wall of the through hole is fixed by the thermosetting filling material.
In a specific application scenario, after the thermosetting filling material fills the gap between the chip and the through hole, and the top of the chip is also filled with the material, the excess filling material on the top of the chip can be removed through etching, ablation, and other processes, so as to expose the top of the chip. In another specific application scenario, when the top of the chip is exposed after the thermosetting filling material fills the gap between the chip and the through hole, step S15 can be directly performed.
Step S15: and removing the first film layer.
And after thermosetting filling is finished and the thermosetting filling material is cooled, the first film layer is removed, so that the packaging mechanism with the periphery coated and the upper and lower surfaces exposed is realized.
In a specific application scenario, when the first film layer is a high-temperature adhesive tape, the first film layer is torn off in this step, and a packaging mechanism with the periphery of the chip covered and the upper and lower surfaces exposed is obtained.
Through the above steps, in the chip packaging method of this embodiment, the chip and the substrate provided with at least one through hole are obtained, the first film layer is firstly covered on the opening on one side of the through hole, then the chip is placed into the through hole from the opening on the other side of the through hole, the through hole is thermally cured and filled from the opening on the other side of the through hole to fill up the gap between the chip and the through hole, and finally the first film layer is removed to obtain the chip packaging mechanism. The embodiment realizes the two layers of coating and fixing around the chip through the substrate and the thermosetting filling so as to protect the periphery of the chip, improve the stability and the reliability of the chip packaging mechanism, ensure the welding of the upper surface and the lower surface of the chip by products and ensure the original state of the chip as much as possible.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a chip packaging method according to another embodiment of the present invention. The chip of the embodiment is an SBD (schottky diode) chip, and is applied to a solar cell panel.
Step S21: and obtaining the chip and the resin plate, and manufacturing at least one through hole on the resin plate through laser cutting, mechanical die stamping or mechanical drilling, wherein the size of the through hole is larger than that of the chip.
And obtaining the chip and the resin plate. The thickness of the resin plate is smaller than or equal to that of the chip, so that the upper surface and the lower surface of the chip can be exposed after the encapsulation is finished. The material of the resin board of the present embodiment may include epoxy resin or other resin material. In other embodiments, the resin plate may be replaced with another insulating plate having a certain strength, which is not limited herein.
At least one through hole is manufactured on the resin plate by means of laser cutting, mechanical die stamping or mechanical drilling, and the substrate is obtained, wherein the size of the through hole is larger than that of the chip, so that the chip is accommodated in the through hole.
In a specific application scenario, the size of the resin plate can be 200 mm × 500 mm and above, when the resin plate is drilled, a plurality of through holes spaced from each other can be prepared on the resin plate in batches based on the size of the chip, so that the plurality of chips are accommodated through the plurality of through holes, the batch packaging of the chips is realized, and the packaging efficiency of the chips is improved.
Step S22: and attaching the high-temperature adhesive tape to one side of the substrate so as to cover the opening on one side of the through hole through the high-temperature adhesive tape.
And attaching a high-temperature adhesive tape to one side of the substrate or placing the substrate on the high-temperature adhesive tape so as to cover the opening on one side of the through hole through the high-temperature adhesive tape. The high-temperature adhesive tape in this step may be replaced with other adhesive films having a certain adhesive force and high temperature resistance, and the type of the specific adhesive film is not limited herein.
Step S23: and placing the chip into the hole groove of the through hole from the opening at the other side of the through hole through a chip mounting machine, so that the first surface of the chip is attached to the high-temperature adhesive tape.
And placing the chip into the hole groove of the through hole from the opening at the other side of the through hole through a chip loader, so that the first surface of the chip is attached to the high-temperature adhesive tape, and the chip bonding is realized. In other embodiments, the chip may be placed into the hole groove of the through hole from the other side opening of the through hole by a person or other chip mounting equipment, and the first surface of the chip is attached to the high temperature adhesive tape, and the specific chip placement means is not limited herein.
The first surface of the chip refers to any one of the upper and lower surfaces of the chip which are not to be coated.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a packaging mechanism of the chip after step S23 in the embodiment of fig. 2.
The chip packaging mechanism 30 of the present embodiment includes a chip 31, a substrate 32, and a high temperature adhesive tape 33. The substrate 32 is provided with a through hole 321, the chip 31 is disposed in the through hole 321, and the substrate 32 is disposed around the chip 31 at intervals. Wherein, the bottom of the chip 31 is attached to the high temperature adhesive tape 33. The high temperature tape 33 is attached to the substrate 32.
Step S24: and filling epoxy resin into the through hole from the opening on the other side of the through hole by using a screen printing machine so as to fill the gap between the chip and the through hole.
And performing resin printing on the substrate from the opening on the other side of the through hole by using a screen printing machine to fill epoxy resin into the through hole so as to fill the gap between the chip and the through hole. In other embodiments, the resin filling may be performed by a human or other filling tool, which is not limited herein.
In a specific application scenario, after the epoxy resin fills the gap between the chip and the through hole, and the top of the chip is also filled with the epoxy resin, the excess epoxy resin on the top of the chip can be removed by methods such as chemical liquid etching, physical ablation and the like, so that the whole second surface of the chip is exposed. In another specific application scenario, when the epoxy resin fills the gap between the chip and the through hole and the entire second surface of the chip is exposed, step S25 may be directly performed. Wherein the second surface of the chip is opposite to the first surface.
Wherein, because the filler material of this embodiment is epoxy, and the base plate material is the resin board together, then after resin filling is accomplished and is cooled off, the cohesion between filler material and the resin board can obtain the promotion of certain degree to improve the stability of chip package. The epoxy resin is an insulating material, the periphery of the chip is coated by the insulating material, the periphery of the chip can be protected, the phenomenon that the periphery of the chip is subjected to arc discharge is effectively reduced, and therefore the performance of products is affected.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a packaging mechanism of the chip after step S24 in the embodiment of fig. 2.
The packaging mechanism 40 of the chip of the present embodiment includes a chip 41, a substrate 42, a high temperature adhesive tape 43, and a filling layer 44. The filling layer 44 is filled between the chip 41 and the substrate 42. The high temperature adhesive tape 43 is attached to the chip 41, the substrate 42 and the filling layer 44 on the same side. In the embodiment, the filling layer 44 covers the top of the chip 41, and in the subsequent packaging process, the excess filling layer 44 on the top of the chip 41 needs to be removed by chemical etching, physical ablation, or the like, so as to expose the top of the chip 41. In other embodiments, when the top of the chip 41 is not covered with the filling layer 44, the above etching or ablation operation is not required for the chip 41.
In other embodiments, the step of resin filling may be: the method comprises the steps of firstly pasting a second film layer on the first surface of a chip, ablating the second film layer by using laser equipment, reserving the second film layer above the chip, reserving connecting ribs with certain widths among the second film layers on the chips, coating liquid resin materials such as epoxy resin and the like above a substrate by using a screen printing machine, vacuumizing the substrate, and filling the gap between the chip and a through hole with the epoxy resin through atmospheric pressure. And tearing off the adhesive tape above the chip once based on the connecting ribs after the filling is finished, then carrying out curing treatment, and tearing off the second film layer at the bottom of the substrate after the resin is cured to finish the resin filling. Wherein, the second film layer can be a film layer with certain adhesive force and high temperature resistance, such as a high temperature adhesive tape.
Step S25: and removing the high-temperature adhesive tape.
And after the resin filling is finished and the cooling is carried out, removing the high-temperature adhesive tape attached to one side of the substrate. And then cutting the substrate into independent packaging mechanisms based on the positions and the number of the chips by using a cutter wheel cutting mode, a laser cutting mode and the like. In a specific application scenario, when 50 through holes are formed in the substrate and 50 chips are respectively placed in the 50 through holes, the substrate can be cut into at least 50 parts based on the positions of the chips by means of cutter wheel cutting, laser cutting and the like, so that the packaging mechanism of a single chip is obtained. The outermost layer of the packaging mechanism of the chip is a substrate, so that the periphery of the chip is wrapped and packaged through the substrate.
Meanwhile, the periphery of the packaging mechanism of the chip obtained by the method is coated, but the upper surface and the lower surface of the chip can be directly used for welding, and transition can be performed without other indirect layers such as RDL (re-wiring) and the like, so that the application steps of the chip are simplified.
Through the above steps, the chip packaging method of the present embodiment receives the chip through the through hole by cutting at least one through hole in the resin plate. After the chip is arranged in the through hole, the substrate is subjected to resin printing to fill a gap between the chip and the substrate, so that the periphery of the chip is coated by resin, after the chip is cut, a resin frame is formed around a filling layer of the chip by the substrate, the rigidity of the whole structure of the chip is increased by the resin frame, and the stability and the reliability of chip packaging are improved. And the upper surface and the lower surface of the chip are ensured to be exposed through high-temperature adhesive tape and etching or ablation operation, so that the upper surface and the lower surface of the chip can be directly welded, and the original state of the chip is ensured as much as possible. This embodiment can be through around resin filling cladding chip to protect around the chip through the filling layer, and reduce the chip and appear all around and put the condition emergence that the arc phenomenon influences product performance.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a chip packaging mechanism according to an embodiment of the present invention.
The packaging mechanism 50 of the chip of the present embodiment includes: a chip 51, a substrate frame 52, and a filling layer 54. The filling layer 54 is attached to the periphery of the chip 51, and the substrate frame 52 is attached to the periphery of the filling layer 54.
The filling layer 54 on the side surface of the chip 51 has no supporting structure, and the substrate frame 52 with certain strength is used for structural reinforcement, so that the overall structural rigidity of the packaging mechanism 50 of the chip 51 is improved, the structural reinforcement function is achieved, and the reliability and the stability of the packaging mechanism 50 of the chip 51 are improved.
In a specific application scenario, the first surface and the second surface of the chip 51 of the embodiment are exposed, so as to facilitate the connection of the subsequent chip 51 by soldering.
Through the structure, the packaging mechanism of the chip of the embodiment protects the periphery of the chip through the filling layer and the substrate frame which are arranged on the periphery of the chip, and insulates air, so that the phenomenon that the arc discharge phenomenon of the chip is generated to influence the product performance is reduced. In the embodiment, the substrate frame with certain strength is used for structurally reinforcing the packaging mechanism, so that the overall structural rigidity of the packaging mechanism of the chip is improved, and the stability and reliability of the packaging mechanism of the chip are improved.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for packaging a chip, the method comprising:
obtaining a chip and a substrate, wherein the substrate is provided with at least one through hole;
covering a first film layer on one side opening of the through hole;
placing the chip into the through hole from the opening on the other side of the through hole;
thermosetting filling is carried out on the through hole from the opening on the other side of the through hole so as to fill the gap between the chip and the through hole;
and removing the first film layer.
2. The method for packaging a chip according to claim 1, wherein the step of obtaining the chip and a substrate, the substrate having at least one through hole disposed thereon, comprises:
obtaining a chip and a resin plate;
at least one through hole is manufactured on the resin plate by laser cutting, mechanical die punching or mechanical drilling, wherein the size of the through hole is larger than that of the chip.
3. The method for packaging a chip according to claim 1, wherein the step of covering the first film layer on the opening on one side of the through hole comprises:
and attaching a high-temperature adhesive tape to one side of the substrate so as to cover the opening on one side of the through hole through the high-temperature adhesive tape.
4. The method of packaging a chip according to claim 3, wherein the step of placing the chip into the through hole from the other side opening of the through hole comprises:
and placing the chip into the hole groove of the through hole from the opening at the other side of the through hole through a chip mounting machine, so that the first surface of the chip is attached to the high-temperature adhesive tape.
5. The method for packaging the chip according to claim 1, wherein the step of thermally filling the through hole from the other side opening of the through hole to fill a gap between the chip and the through hole comprises:
and filling epoxy resin into the through hole from the opening on the other side of the through hole by using a screen printing machine so as to fill the gap between the chip and the through hole.
6. The method for packaging a chip according to claim 1 or 5, wherein the step of thermally filling the through hole from the other side opening of the through hole to fill the gap between the chip and the through hole is followed by:
and removing the filling material on the other side of the substrate by etching or ablation until the second surface of the chip is exposed.
7. The method for packaging the chip according to claim 1, wherein the step of thermally filling the through hole from the other side opening of the through hole to fill a gap between the chip and the through hole comprises:
attaching a second film layer on the first surface of the chip;
coating epoxy resin on the substrate from the opening on the other side of the through hole by using a screen printing machine;
carrying out vacuum treatment on the substrate to enable epoxy resin to fill the gap between the chip and the through hole;
and removing the second film layer.
8. The method for packaging a chip according to claim 1, wherein the step of removing the first film layer further comprises:
and cutting the substrate based on the number and the positions of the through holes to obtain the independent packaging mechanism of the chip.
9. A chip packaging mechanism is characterized by comprising:
a chip;
the filling layer is attached to the periphery of the chip;
and the substrate frame surrounds the periphery of the filling layer and is attached to the filling layer.
10. The chip packaging mechanism of claim 9, wherein the first surface and the second surface of the chip are exposed.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110164514.0A CN114883206A (en) | 2021-02-05 | 2021-02-05 | Chip packaging method and chip packaging mechanism |
| PCT/CN2021/084130 WO2022165958A1 (en) | 2021-02-05 | 2021-03-30 | Chip packaging method and chip packaging mechanism |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110164514.0A CN114883206A (en) | 2021-02-05 | 2021-02-05 | Chip packaging method and chip packaging mechanism |
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| CN114883206A true CN114883206A (en) | 2022-08-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110164514.0A Pending CN114883206A (en) | 2021-02-05 | 2021-02-05 | Chip packaging method and chip packaging mechanism |
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| WO (1) | WO2022165958A1 (en) |
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| CN117747586B (en) * | 2023-12-25 | 2024-09-24 | 江苏宜兴德融科技有限公司 | Flexible film type chip packaging structure and packaging method |
| CN117594455B (en) * | 2024-01-19 | 2024-04-16 | 凯瑞电子(诸城)有限公司 | Microelectronic chip shell interference-free mounting device |
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| TWI251910B (en) * | 2004-06-29 | 2006-03-21 | Phoenix Prec Technology Corp | Semiconductor device buried in a carrier and a method for fabricating the same |
| CN102738094B (en) * | 2012-05-25 | 2015-04-29 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure for stacking and manufacturing method thereof |
| CN107910274A (en) * | 2017-12-18 | 2018-04-13 | 苏州晶方半导体科技股份有限公司 | A kind of method for packing and encapsulating structure of fingerprint chip |
| CN108417498A (en) * | 2018-03-14 | 2018-08-17 | 中国电子科技集团公司第五十八研究所 | A kind of packaging method and encapsulation chip of chip |
| CN109494163A (en) * | 2018-11-20 | 2019-03-19 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of chip |
| WO2020103147A1 (en) * | 2018-11-23 | 2020-05-28 | 北京比特大陆科技有限公司 | Chip heat dissipation structure, chip structure, circuit board and supercomputing device |
| CN110233113A (en) * | 2019-06-17 | 2019-09-13 | 青岛歌尔微电子研究院有限公司 | A kind of packaging method of chip |
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- 2021-02-05 CN CN202110164514.0A patent/CN114883206A/en active Pending
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