CN112928028A - Board-level chip packaging method with embedded circuit and packaging structure thereof - Google Patents

Board-level chip packaging method with embedded circuit and packaging structure thereof Download PDF

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Publication number
CN112928028A
CN112928028A CN202110090761.0A CN202110090761A CN112928028A CN 112928028 A CN112928028 A CN 112928028A CN 202110090761 A CN202110090761 A CN 202110090761A CN 112928028 A CN112928028 A CN 112928028A
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layer
chip
board
carrier plate
rewiring layer
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CN202110090761.0A
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杨斌
罗绍根
崔成强
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Priority to CN202110090761.0A priority Critical patent/CN112928028A/en
Publication of CN112928028A publication Critical patent/CN112928028A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The application provides a board-level chip packaging method with an embedded circuit and a packaging structure thereof, wherein the method comprises the following steps: providing a carrier plate, and arranging a first rewiring layer on one side surface of the carrier plate along the thickness direction of the carrier plate; providing at least one first chip, arranging the first chip at a preset position of the first redistribution layer, and electrically connecting the electric signal connecting bump of the first chip with the first redistribution layer; providing a first plastic package material, carrying out plastic package on one side surface of the carrier plate provided with the first rewiring layer and the first chip, and forming a first plastic package layer wrapping the first rewiring layer and the first chip after curing; and removing the carrier plate to obtain the board-level chip packaging structure with the embedded circuit. This application can encapsulate the protection to the heavy-wiring circuit layer, can protect the interconnection interface to the heavy-wiring circuit layer and chip simultaneously, improves packaging structure's leakproofness, increase of service life.

Description

Board-level chip packaging method with embedded circuit and packaging structure thereof
Technical Field
The application relates to the technical field of chip packaging, in particular to a board-level chip packaging method with an embedded circuit and a packaging structure thereof.
Background
Modern electronic information technology is rapidly developed, and electronic products are developed in the directions of miniaturization, portability and multiple functions. The fan-out package is widely applied to the development of semiconductor technology because high-density integration, multi-element embedded integration, volume miniaturization and lower cost can be realized by the fan-out integrated advanced package technology.
At present, for a fan-out chip packaging structure, the following technical problems also exist: at least one dielectric material layer is required to be laminated between the chip and the rewiring layer for insulating the protection circuit, and because the dielectric material layer is usually laminated and a signal connection bump is arranged on the surface of the chip, which is in contact with the dielectric material layer, a tiny gap exists between the dielectric material layer and the signal connection bump of the chip, so that the signal connection bump cannot be well protected, the sealing performance of the packaging structure is influenced, and the service life of the packaging structure is shortened.
Therefore, there is a great need for improvement in the art.
Disclosure of Invention
An object of the embodiments of the present application is to provide a board-level chip packaging method with an embedded circuit and a packaging structure thereof, which solve the problem that in the existing chip packaging process, a small gap exists between a dielectric material layer and a signal connection bump of a chip, so that the electrical signal connection bump of the chip cannot be well protected, and can greatly improve the sealing performance of the packaging structure and prolong the service life.
The embodiment of the application provides a board-level chip packaging method with an embedded circuit, which comprises the following steps:
A. providing a carrier plate, and arranging a first rewiring layer on one side surface of the carrier plate along the thickness direction of the carrier plate;
B. providing at least one first chip, arranging the first chip at a preset position of the first redistribution layer, and electrically connecting the electric signal connecting bump of the first chip with the first redistribution layer;
C. providing a first plastic package material, carrying out plastic package on one side surface of the carrier plate, which is provided with the first rewiring layer and the first chip, and forming a first plastic package layer wrapping the first rewiring layer and the first chip after curing;
D. and removing the carrier plate to obtain the board-level chip packaging structure with the embedded circuit.
Preferably, in the board-level chip packaging method with an embedded circuit according to the embodiment of the present application, between or after step C and step D, the method further includes the following steps:
r1, arranging a second rewiring layer on the first plastic packaging layer, and electrically connecting the second rewiring layer with the first rewiring layer;
r2, providing at least one second chip, arranging the second chip at a preset position on the second rewiring layer, and electrically connecting the electric signal connecting convex points of the second chip with the second rewiring layer;
and R3, providing a second plastic package material, carrying out plastic package on the first plastic package layer, and forming a second plastic package layer wrapping the second rewiring layer and the second chip after curing.
Preferably, in the board-level chip packaging method with embedded circuits according to the embodiment of the present application,
in the step a, the following steps are further included: manufacturing a plurality of electric connecting columns on one side surface of the carrier plate along the thickness direction of the carrier plate, and electrically connecting the electric connecting columns with the first rewiring layer;
in the step R1, the method further includes the following steps: and electrically connecting the electric connecting column with the second rewiring layer to ensure that the second rewiring layer is electrically connected with the first rewiring layer.
Preferably, in the method for packaging a board-level chip with an embedded circuit according to the embodiment of the present application, the electrically connecting posts are copper posts or keys and wires.
Preferably, in the board-level chip packaging method with embedded circuits according to the embodiment of the present application,
in the step B, the following steps are further included: manufacturing a plurality of heat dissipation copper columns on one side surface of the carrier plate along the thickness direction of the carrier plate, so that the heat dissipation copper columns are positioned around the first chip;
between the step C and the step D or after the step D, the method further comprises the following steps: and arranging a heat dissipation device on the first plastic packaging layer, and connecting the heat dissipation device with the heat dissipation copper column.
Preferably, in the method for packaging a board-level chip with an embedded circuit according to the embodiment of the present application, the heat dissipation device is one of a heat dissipation copper layer, a graphene layer, or a heat dissipation strand glue layer.
Preferably, in the board-level chip packaging method with an embedded circuit according to the embodiment of the present application, after the step D, the method further includes the following steps:
t1, laminating at least one dielectric material layer on the first rewiring layer, and forming a first through hole in the dielectric material layer, wherein the first through hole enables the pad area of the first rewiring layer to be exposed;
t2, coating photosensitive solder resist ink on the dielectric material layer, and sequentially performing exposure and development to form a solder resist layer with a second through hole, wherein the position of the second through hole corresponds to the position of the first through hole;
and T3, providing a metal bump, and welding the metal bump to the pad area of the first redistribution layer.
The embodiment of the present application further provides a board-level chip package structure with an embedded circuit, including:
a first redistribution layer having a first side and a second side opposite to each other in a thickness direction thereof;
the first chip is arranged on the first side face of the first redistribution layer, and an electric signal connecting bump of the first chip is electrically connected with the first redistribution layer;
the first encapsulation layer wraps the first rewiring layer and the first chip, and only the second side face of the second rewiring layer is exposed.
Preferably, in the board-level fan-out package structure of an embedded circuit according to an embodiment of the present invention, the board-level fan-out package structure further includes:
the second rewiring layer is arranged on the first plastic packaging layer and is electrically connected with the first rewiring layer through a plurality of electric connecting columns;
the second chip is arranged on the second redistribution layer, and an electric signal connecting bump of the second chip is electrically connected with the second redistribution layer;
and the second redistribution layer and the second chip are wrapped in the second encapsulation layer.
According to the board-level chip packaging method with the embedded circuit, the rewiring layer is manufactured on the carrier plate in advance, then the chip is arranged on the rewiring layer, and finally plastic packaging is carried out on the rewiring layer and the chip through the plastic packaging material, so that the rewiring layer and the chip are wrapped in the plastic packaging layer, the rewiring layer is packaged and protected, the plastic packaging layer can be filled in a connecting gap between the rewiring layer and the chip, an interconnection interface between the rewiring layer and the chip is protected, the sealing performance of a packaging structure is improved, and the service life is prolonged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a flowchart of a board-level chip packaging method with embedded circuits according to embodiment 1 of the present application.
Fig. 2 is a detailed schematic diagram of each step of a board-level chip packaging method with embedded circuits according to embodiment 1 of the present application.
Fig. 3 is a detailed schematic diagram of each step of a board-level chip packaging method with embedded circuits according to embodiment 2 of the present application.
Fig. 4 is a detailed schematic diagram of each step of a board-level chip packaging method with embedded circuits according to embodiment 3 of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it should be noted that the terms "side" and the like refer to an orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is conventionally put out when the product of the application is used, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features.
It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The board-level chip packaging method with embedded circuits of the present application is described below by some specific embodiments.
Example 1
Referring to fig. 1, fig. 1 is a schematic flow chart of a board-level chip packaging method with an embedded circuit according to embodiment 1 of the present application. The board-level chip packaging method with the embedded circuit comprises the following steps:
A. providing a carrier plate, and arranging a first rewiring layer on one side surface of the carrier plate along the thickness direction of the carrier plate;
B. providing at least one first chip, arranging the first chip at a preset position of the first redistribution layer, and electrically connecting the electric signal connecting bump of the first chip with the first redistribution layer;
C. providing a first plastic package material, carrying out plastic package on one side surface of the carrier plate, which is provided with the first rewiring layer and the first chip, and forming a first plastic package layer wrapping the first rewiring layer and the first chip after curing;
D. and removing the carrier plate to obtain the board-level chip packaging structure with the embedded circuit.
Referring to fig. 2, fig. 2 is a detailed schematic diagram of each step of a board-level chip packaging method with an embedded circuit according to embodiment 1 of the present application, and embodiment 1 of the present application is further described below.
Specifically, in step a, the carrier 10 may be covered with the temporary bonding glue layer 20, and then the first redistribution layer 30 is fabricated on the temporary bonding glue layer 20. The temporary bonding glue layer 20 may be a common bonding glue, such as blue film or other bonding glue. The carrier 10 may be a glass carrier, an organic carrier, a stainless steel carrier, an alloy carrier, an FR2 carrier, an FR4 carrier, an FR5 carrier, or a BT resin carrier. In practical application, the first redistribution layer 30 may be fabricated by the following two methods, the first method is specifically: firstly, providing a photosensitive dry film or photosensitive ink, and covering the temporary bonding glue layer 20 with the photosensitive dry film or the photosensitive ink; then, sequentially exposing and developing the photosensitive dry film or the photosensitive ink to form a patterned through hole; then, copper electroplating is performed in the patterned through hole to form a first redistribution layer 30, and an upper pad is formed at a predetermined position of the first redistribution layer 30 by copper electroplating and deposition, wherein the upper pad is used for electrically connecting with the electrical signal connection bump 41 of the first chip 40. The second method is specifically as follows: and covering a copper foil on the temporary bonding glue layer 20, directly obtaining a first redistribution layer 30 through laser etching, and depositing copper through electroplating to form an upper bonding pad on a preset position of the first redistribution layer 30.
In step B, the electrical signal connection bumps 41 of the first chip 40 and the upper pads of the first redistribution layer 30 may be electrically connected by reflow soldering.
In step C, the first molding compound may be a liquid epoxy resin, for example, a bisphenol A type epoxy resin, a brominated epoxy resin, a novolak type epoxy resin, a bisphenol F type epoxy resin, a hydrogenated bisphenol A type epoxy resin, a glycidyl amine type epoxy resin, a hydantoin type epoxy resin, an alicyclic epoxy resin, a trishydroxyphenylmethane type epoxy resin, a bis-or bisphenol type epoxy resin or a mixture thereof, a bisphenol S type epoxy resin, a bisphenol A novolak type epoxy resin, a tetraphenylphenol alcohol (PhenylLOL) ethane type epoxy resin, a heterocyclic epoxy resin, a diglycidyl benzoate resin, a tetraglycidyl dimethylol ethane resin, a naphthyl group-containing epoxy resin, a nitrogen-containing epoxy resin, an epoxy resin having a dicyclopentadiene skeleton, a glycidyl methacrylate copolymerization type epoxy resin, a hydrogenated epoxy resin, a glycidyl amine type epoxy resin, a hydantoin type epoxy resin, a cycloaliphatic epoxy resin, a trihydroxyphenyl methane type epoxy resin, a bis-or bisphenol type epoxy resin, a diglycidyl benzoate type epoxy, Epoxy resins obtained by copolymerizing cyclohexylmaleimide with glycidyl methacrylate, CTBN-modified epoxy resins, and the like. Of course, these epoxy resins may be used alone or in combination of 2 or more. In addition, the first molding compound may also be liquid polyimide or liquid silicone, and the first molding compound must be liquid, but the specific material thereof is not limited. During plastic packaging, the first plastic packaging material can be filled in the patterned through holes of the first redistribution layer 30 to play an insulating role, a connection gap between the first redistribution layer 30 and the first chip 40 is filled, and after curing, the first plastic packaging layer 50 which wraps the first redistribution layer 30 and the first chip 40 is formed. Therefore, the board-level chip packaging method with the embedded circuit in the embodiment of the application can package and protect the first redistribution layer 30, and can protect the interconnection interface between the first redistribution layer 30 and the first chip 40, so that the sealing performance of the packaging structure can be improved, and the service life can be prolonged.
In step D, the temporary bonding glue layer 20 may be removed by thermal disassembly, mechanical disassembly or laser disassembly to disassemble the carrier 10. In practical application, according to actual needs, the obtained board-level chip package structure with the embedded circuit can be cut to obtain chip package structure monomers with the embedded circuit, each monomer comprises one first chip 40, and therefore the chip package structure monomers with the embedded circuit can be produced in a large batch at one time and used for being attached to the corresponding circuit. The first chip 40 may also be a chipset including a plurality of functional chips, and the distribution of the chipset on the first redistribution layer 30 may be set according to a pre-designed circuit.
In addition, in the board-level chip packaging method with an embedded circuit in embodiment 1 of the present application, after step D, the method further includes the following steps:
t1, laminating at least one dielectric material layer 60 on the first redistribution layer 30, and opening a first via hole in the dielectric material layer 60, wherein the first via hole exposes the pad region of the first redistribution layer 30;
t2, coating photosensitive solder resist ink on the dielectric material layer 60, and sequentially exposing and developing to form a solder resist layer 70 having a second through hole corresponding to the first through hole;
t3, providing the metal bump 71, and soldering the metal bump 71 to the pad region of the first redistribution layer 30.
The material of the dielectric material layer 60 is ABF (Ajinomoto Build-up Film), PP (Polypropylene), polyimide Film, or the like. Since the first redistribution layer 30 is made of copper, the thermal expansion coefficient of copper is greatly different from that of the solder mask layer 70, and thus delamination is likely to occur in practical applications, and the thermal expansion coefficient of the material of the dielectric material layer 60 is between that of copper and the solder mask layer 70, so that the thermal reliability of the circuit can be increased and delamination of the package structure can be prevented by providing the dielectric material layer 60.
In addition, the metal bump 71 may be one of a solder, a silver solder or a gold-tin alloy solder, and the metal bump 71 in embodiment 1 of the present application is a metal ball structure, and the metal ball is solder-implanted in the pad region to electrically lead out the first redistribution layer 30.
Example 2
Referring to fig. 3, fig. 3 is a detailed schematic diagram of each step of a board-level chip packaging method with an embedded circuit according to embodiment 2 of the present application, and embodiment 2 is a package with a 3D stacked chip structure based on embodiment 1, so as to obtain a more compact and higher integrated package structure. Example 2 of the present application will be further described below.
In the board-level chip packaging method with an embedded circuit in embodiment 2 of the present application, between or after step C and step D, the following steps are further included:
r1, disposing the second redistribution layer 80 on the first molding compound layer 50, and electrically connecting the second redistribution layer 80 with the first redistribution layer 30;
r2, providing at least one second chip 90, disposing the second chip 90 at a predetermined position on the second redistribution layer 80, and electrically connecting the electrical signal connection bumps of the second chip 90 with the second redistribution layer 80;
and R3, providing a second plastic package material, performing plastic package on the first plastic package layer 50, and curing to form a second plastic package layer 100 wrapping the second redistribution layer 80 and the second chip 90.
Further, in the board-level chip packaging method with embedded circuits of embodiment 2 of the present application,
in step a, the method further comprises the following steps: manufacturing a plurality of electrical connection posts 31 on one side surface of the carrier plate 10 along the thickness direction thereof, and electrically connecting the electrical connection posts 31 with the first redistribution layer 30;
accordingly, in step R1, the following steps are further included: the electrical connection posts 31 are electrically connected to the second redistribution layer 80, so that the second redistribution layer 80 is electrically connected to the first redistribution layer 30.
Preferably, in the board-level chip packaging method with embedded circuit of embodiment 2 of the present application, the electrical connection pillars 31 are copper pillars or keys and wires.
Example 3
Referring to fig. 4, fig. 4 is a detailed schematic diagram of each step of a board-level chip packaging method with an embedded circuit according to embodiment 3 of the present application, and embodiment 3 is to perform packaging of a heat dissipation device 82 on the basis of embodiment 1 to obtain a package structure with higher integration level and better heat dissipation effect. Example 2 of the present application will be further described below.
Specifically, in the board-level chip packaging method with an embedded circuit according to embodiment 3 of the present application, in step a, the method further includes the following steps: manufacturing a plurality of heat dissipation copper pillars 81 on one side surface of the carrier plate 10 along the thickness direction thereof, so that the heat dissipation copper pillars 81 are located around the first chip 40;
between step C and step D or after step D, the following steps are also included: a heat dissipation device 82 is disposed on the first molding compound layer 50, and the heat dissipation device 82 is connected to the heat dissipation copper pillar 81.
In practical applications, the heat dissipation device 82 is one of a heat dissipation copper layer, a graphene layer, or a heat dissipation strand glue layer. In practical applications, the heat dissipation device 82 may also be composed of only one heat conductive interface material layer, and preferably, the heat dissipation device 82 may be composed of a heat conductive interface material layer and a heat sink stacked in sequence from bottom to top. The thermal interface material layer is used for conducting heat generated by the first chip 40 to the heat sink, and then rapidly dissipating the heat generated by the first chip 40 through the heat sink. Specifically, in practical application, the heat-conducting interface material layer may be one of heat-conducting silicone grease, a heat-conducting silicone sheet, a heat-conducting phase-change material, or a heat-conducting double-sided adhesive tape, and the heat sink is one, two, or a combination of more than two of a metal plate, a graphite film, a graphene film, a heat pipe, or a vapor chamber containing heat dissipation fins. For example, a heat pipe or a vapor chamber may be disposed on the heat conducting interface material layer, and a graphite film or a graphene film may be disposed on the heat pipe or the vapor chamber, so that the heat generated by the first chip 40 is first transferred to the heat pipe or the vapor chamber through the heat conducting interface material layer, then transferred to the graphite film or the graphene film, and then transferred into the air directly or through a metal plate having heat dissipation fins, thereby forming an efficient heat dissipation system.
Further, in embodiment 3 of the present application, the heat dissipation copper pillar 81 is disposed around the first chip 40, the heat dissipation copper pillar 81 is connected to the heat dissipation device 82, so as to dissipate heat generated by the first chip 40 in the longitudinal direction, and in combination with the heat dissipation device 82 above the first chip 40, the heat generated by the first chip 40 can be dissipated in all directions, thereby achieving efficient heat dissipation.
In addition, the heat spreader 82 may also be encapsulated with a heat spreader molding layer 83 to protect the heat spreader 82.
It should be noted that, an embodiment of the present application further provides a board-level chip package structure with an embedded circuit, including:
a first rewiring layer 30, the first rewiring layer 30 having a first side surface and a second side surface opposite to each other in a thickness direction thereof;
at least one first chip 40, wherein the first chip 40 is disposed on a first side surface of the first redistribution layer 30, and the electrical signal connection bump of the first chip 40 is electrically connected to the first redistribution layer 40;
the first plastic package layer 50 wraps the first redistribution layer 30 and the first chip 40, and only the second side surface of the second redistribution layer 30 is exposed by the first package layer 50.
In addition, the board-level fan-out package structure of the embedded circuit of the embodiment of the present application, the board-level fan-out package structure further includes:
a second redistribution layer 80, wherein the second redistribution layer 80 is disposed on the first plastic-sealed layer 50 and electrically connected to the first redistribution layer 30 through a plurality of electrical connection posts 31;
at least one second chip 90, wherein the second chip 90 is disposed on the second redistribution layer 80, and the electrical signal connection bump of the second chip 80 is electrically connected to the second redistribution layer 80;
a second molding compound layer 100, the second encapsulation layer 100 encapsulating the second redistribution layer 80 and the second chip 90.
The 3D stacking packaging mode of the embodiment of the application can not only package the first redistribution layer 30 and the second redistribution layer 80, play a role in line protection, but also shorten the wiring length between chips, thereby achieving the purposes of shortening delay time, easily realizing modularization and high speed, and realizing system-in-package with high integration level.
According to the board-level chip packaging method with the embedded circuit and the packaging structure thereof, the rewiring layer is manufactured on the carrier plate in advance, then the chip is arranged on the rewiring layer, and finally the rewiring layer and the chip are packaged in a plastic package mode through the plastic package material, so that the rewiring layer and the chip are wrapped in the plastic package layer, the rewiring layer is packaged and protected and can be filled in a connecting gap between the rewiring layer and the chip, an interconnection interface between the rewiring layer and the chip is protected, the sealing performance of the packaging structure is improved, and the service life is prolonged; and 3D stacked packaging or packaging of a heat dissipation structure can be realized, and the packaging process can be simplified.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (9)

1. A board level chip packaging method with embedded circuits is characterized by comprising the following steps:
A. providing a carrier plate, and arranging a first rewiring layer on one side surface of the carrier plate along the thickness direction of the carrier plate;
B. providing at least one first chip, arranging the first chip at a preset position of the first redistribution layer, and electrically connecting the electric signal connecting bump of the first chip with the first redistribution layer;
C. providing a first plastic package material, carrying out plastic package on one side surface of the carrier plate, which is provided with the first rewiring layer and the first chip, and forming a first plastic package layer wrapping the first rewiring layer and the first chip after curing;
D. and removing the carrier plate to obtain the board-level chip packaging structure with the embedded circuit.
2. The board-level chip packaging method with embedded circuits according to claim 1, further comprising the following steps between or after the step C and the step D:
r1, arranging a second rewiring layer on the first plastic packaging layer, and electrically connecting the second rewiring layer with the first rewiring layer;
r2, providing at least one second chip, arranging the second chip at a preset position on the second rewiring layer, and electrically connecting the electric signal connecting convex points of the second chip with the second rewiring layer;
and R3, providing a second plastic package material, carrying out plastic package on the first plastic package layer, and forming a second plastic package layer wrapping the second rewiring layer and the second chip after curing.
3. The board-level chip packaging method with embedded circuits according to claim 2,
in the step a, the following steps are further included: manufacturing a plurality of electric connecting columns on one side surface of the carrier plate along the thickness direction of the carrier plate, and electrically connecting the electric connecting columns with the first rewiring layer;
in the step R1, the method further includes the following steps: and electrically connecting the electric connecting column with the second rewiring layer to ensure that the second rewiring layer is electrically connected with the first rewiring layer.
4. The board-level chip packaging method with embedded wiring according to claim 3, wherein the electrical connection posts are copper posts or keys and wires.
5. The board-level chip packaging method with embedded circuits according to claim 1,
in the step B, the following steps are further included: manufacturing a plurality of heat dissipation copper columns on one side surface of the carrier plate along the thickness direction of the carrier plate, so that the heat dissipation copper columns are positioned around the first chip;
between the step C and the step D or after the step D, the method further comprises the following steps: and arranging a heat dissipation device on the first plastic packaging layer, and connecting the heat dissipation device with the heat dissipation copper column.
6. The board-level chip packaging method with embedded circuits according to claim 5, wherein the heat dissipation device is one of a heat dissipation copper layer, a graphene layer or a heat dissipation die attach adhesive layer.
7. The board-level chip packaging method with embedded circuits according to claim 1, further comprising the following steps after said step D:
t1, laminating at least one dielectric material layer on the first rewiring layer, and forming a first through hole in the dielectric material layer, wherein the first through hole enables the pad area of the first rewiring layer to be exposed;
t2, coating photosensitive solder resist ink on the dielectric material layer, and sequentially performing exposure and development to form a solder resist layer with a second through hole, wherein the position of the second through hole corresponds to the position of the first through hole;
and T3, providing a metal bump, and welding the metal bump to the pad area of the first redistribution layer.
8. A board-level chip package structure with embedded lines, comprising:
a first redistribution layer having a first side and a second side opposite to each other in a thickness direction thereof;
the first chip is arranged on the first side face of the first redistribution layer, and an electric signal connecting bump of the first chip is electrically connected with the first redistribution layer;
the first encapsulation layer wraps the first rewiring layer and the first chip, and only the second side face of the second rewiring layer is exposed.
9. The board-level fan-out package for embedded lines of claim 8, further comprising:
the second rewiring layer is arranged on the first plastic packaging layer and is electrically connected with the first rewiring layer through a plurality of electric connecting columns;
the second chip is arranged on the second redistribution layer, and an electric signal connecting bump of the second chip is electrically connected with the second redistribution layer;
and the second redistribution layer and the second chip are wrapped in the second encapsulation layer.
CN202110090761.0A 2021-01-22 2021-01-22 Board-level chip packaging method with embedded circuit and packaging structure thereof Withdrawn CN112928028A (en)

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TWI790880B (en) * 2021-08-16 2023-01-21 大陸商深南電路股份有限公司 Packaging mechanism and manufacturing method thereof
CN115985783A (en) * 2023-03-20 2023-04-18 合肥矽迈微电子科技有限公司 Packaging structure and process of MOSFET chip

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CN101189717A (en) * 2006-01-13 2008-05-28 日本Cmk株式会社 Printed wiring board with built-in semiconductor element and method for manufacturing same
CN103000593A (en) * 2011-09-09 2013-03-27 台湾积体电路制造股份有限公司 Packaging methods and structures for semiconductor devices
CN104733413A (en) * 2015-03-27 2015-06-24 江阴长电先进封装有限公司 MOSFET packaging structure
CN104869753A (en) * 2014-02-21 2015-08-26 三星电机株式会社 Printed Circuit Board And Method Of Manufacturing The Same
CN107611043A (en) * 2017-08-24 2018-01-19 通富微电子股份有限公司 A kind of fan-out package method

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Publication number Priority date Publication date Assignee Title
CN1321411A (en) * 1999-09-02 2001-11-07 伊比登株式会社 Printed wiring board and method of producing same
CN101189717A (en) * 2006-01-13 2008-05-28 日本Cmk株式会社 Printed wiring board with built-in semiconductor element and method for manufacturing same
CN103000593A (en) * 2011-09-09 2013-03-27 台湾积体电路制造股份有限公司 Packaging methods and structures for semiconductor devices
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI790880B (en) * 2021-08-16 2023-01-21 大陸商深南電路股份有限公司 Packaging mechanism and manufacturing method thereof
CN115985783A (en) * 2023-03-20 2023-04-18 合肥矽迈微电子科技有限公司 Packaging structure and process of MOSFET chip

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