KR102607055B1 - Semiconductor package system - Google Patents

Abstract

According to the present invention, a semiconductor package system is provided. A semiconductor package system according to embodiments includes a substrate; a first semiconductor package mounted on the substrate; a second semiconductor package mounted on the substrate; a first passive element mounted on the substrate; a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the first passive element; And it may include a first heat-conducting layer interposed between the first semiconductor package and the heat dissipation structure. The sum of the height of the mounted first semiconductor package and the height of the first heat-conducting layer may be greater than the height of the mounted first passive element. The height of the mounted first semiconductor package may be greater than the height of the mounted second semiconductor package.

Description

Semiconductor package system

The present invention relates to a semiconductor package system, and more specifically to a semiconductor package system provided with a heat dissipation structure.

A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, a semiconductor package mounts a semiconductor chip on a printed circuit board (PCB) and electrically connects them using bonding wires or bumps. As semiconductor packages become faster and have higher capacities, the power consumption of semiconductor packages is increasing. Accordingly, the importance of the thermal characteristics of semiconductor packages is increasing.

The problem to be solved by the present invention is to provide a semiconductor package with improved thermal properties and a semiconductor module including the same.

The present invention relates to a semiconductor package system. According to the present invention, a semiconductor package system includes a substrate; a first semiconductor package mounted on the substrate; a second semiconductor package mounted on the substrate; a first passive element mounted on the substrate; a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the first passive element; And it may include a first heat-conducting layer interposed between the first semiconductor package and the heat dissipation structure. The sum of the height of the mounted first semiconductor package and the height of the first heat-conducting layer may be greater than the height of the mounted first passive element. The height of the mounted first semiconductor package may be greater than the height of the mounted second semiconductor package.

According to the present invention, a semiconductor package system includes a substrate; a first semiconductor package mounted on the upper surface of the substrate and including a first semiconductor chip, the first semiconductor chip including logic circuits; a second semiconductor package mounted on the upper surface of the substrate; a passive element mounted on the upper surface of the substrate; a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the passive element; And it may include a plurality of heat conductive layers each physically contacting the lower surface of the heat dissipation structure. The heat-conducting layers include a first heat-conducting layer provided on the upper surface of the first semiconductor package, and the first heat-conducting layer may have the thinnest thickness among the heat-conducting layers.

According to the present invention, a semiconductor package system substrate; a first semiconductor package mounted on the substrate and including a first semiconductor chip, the first semiconductor chip including logic circuits; a second semiconductor package mounted on the substrate; Passive elements mounted on the board; a heat dissipation structure provided on the first package, the second package, and the passive element; a first heat-conducting layer provided on the first semiconductor package and physically contacting the heat dissipation structure; and a second heat-conducting layer provided on the second semiconductor package and physically contacting the heat dissipation structure. The first heat-conducting layer may have a smaller thickness than the second heat-conducting layer, and the top surface of the first heat-conducting layer may be provided at a higher level than the top surface of the passive element.

According to the present invention, when the package system operates, the first semiconductor package can generate a lot of heat. The thickness of the first heat-conducting layer may be smaller than the thickness of the second heat-conducting layer and the third heat-conducting layer. As the thickness of the first heat-conducting layer decreases, the thermal characteristics of the first semiconductor package may be improved. Packaged systems may exhibit improved operating characteristics.

1A is a plan view showing a package system according to embodiments.
Figure 1B is a plan view showing a package system according to embodiments.
FIG. 1C is a cross-section taken along line I-II of FIG. 1A.
FIG. 1D is an enlarged view of area A of FIG. 1C.
FIG. 1E is an enlarged view of area B of FIG. 1C.
FIG. 1F is a diagram illustrating a package system according to embodiments.
FIG. 1g corresponds to an enlarged view of area III of FIG. 1a.
Figure 1h is a cross-section taken along line I'-II' of Figure 1e.
FIG. 1I is a diagram for explaining a first semiconductor package according to embodiments.
Figure 2A is a plan view showing a package system according to embodiments.
Figure 2b is a cross-section taken along line I-II of Figure 2a.
Figure 2C is a plan view showing a package system according to embodiments.
FIG. 2D is a cross-section taken along line I-II of FIG. 2C.
Figure 2e is a cross-sectional view showing a package system according to embodiments.
Figure 3a is a cross-sectional view showing a package system according to embodiments.
Figure 3b is a cross-sectional view showing a package system according to embodiments.
Figure 3C is a cross-sectional view showing a package system according to embodiments.
Figure 4a is a cross-sectional view showing a package system according to embodiments.
Figure 4b is a cross-sectional view showing a package system according to embodiments.
Figure 4c is a cross-sectional view showing a package system according to embodiments.
5A is a cross-sectional view showing a semiconductor module according to embodiments.
FIG. 5B is a diagram for explaining a second passive element according to embodiments, and is an enlarged cross-section of region C of FIG. 5A.
FIG. 5C is a diagram for explaining lower pads and conductive terminals according to embodiments.
FIG. 5D is a diagram for explaining lower pads according to embodiments.

In this specification, the same reference numerals may refer to the same elements throughout. Hereinafter, a package system according to the concept of the present invention and a semiconductor module including the same will be described. The semiconductor package system may be a package system or a semiconductor module including the package system.

1A is a plan view showing a package system according to embodiments. Figure 1B is a plan view showing a package system according to embodiments. FIG. 1C is a cross-section taken along line I-II of FIG. 1A. FIG. 1D is an enlarged view of area A of FIG. 1C. FIG. 1E is an enlarged view of area B of FIG. 1C.

1A, 1B, 1C, 1D, and 1E, the package system 1 includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, and a third semiconductor package. It may include 300, a first passive element 400, a heat dissipation structure 600, and a first heat conductive layer 710. As an example, a printed circuit board (PCB) with a circuit pattern may be used as the substrate 500. Conductive terminals 550 may be provided on the lower surface of the substrate 500. The conductive terminals 550 may include at least one of solder balls, bumps, and pillars. The conductive terminals 550 may include metal, for example.

The first semiconductor package 100 may be mounted on the top surface 500a of the substrate 500. The first semiconductor package 100 may include a logic chip or a system-on-chip, as will be described later. First connection terminals 150 may be interposed between the substrate 500 and the first semiconductor package 100 . The first semiconductor package 100 may be electrically connected to the substrate 500 through first connection terminals 150 . In this specification, being electrically connected to the substrate 500 may mean being electrically connected to wires 505 within the substrate 500. The first connection terminals 150 may include solder balls, pillars, bumps, or ball grid arrays. The height H1 of the mounted first semiconductor package 100 may be defined to include the height of the first connection terminals 150. In this specification, the height of a certain component may mean the maximum distance of the component measured in a direction perpendicular to the upper surface 500a of the substrate 500. The pitch of the first connection terminals 150 may be smaller than the pitch of the conductive terminals 550.

The second semiconductor package 200 may be mounted on the top surface 500a of the substrate 500. The second semiconductor package 200 may be arranged to be spaced apart from the first semiconductor package 100 in a plan view. The second semiconductor package 200 may be a different type of semiconductor package from the first semiconductor package 100. Second connection terminals 250 may be interposed between the substrate 500 and the second semiconductor package 200 . The second semiconductor package 200 may be electrically connected to the substrate 500 through second connection terminals 250 . The second connection terminals 250 may include solder balls, pillars, bumps, or ball grid arrays. The pitch of the second connection terminals 250 may be smaller than the pitch of the conductive terminals 550. The height H2 of the mounted second semiconductor package 200 may be defined to include the height of the second connection terminals 250. A plurality of second semiconductor packages 200 may be provided. The second semiconductor packages 200 may be spaced apart from each other. However, the number and planar arrangement of the second semiconductor packages 200 may vary.

The third semiconductor package 300 may be mounted on the substrate 500 . The third semiconductor package 300 may be arranged to be spaced apart from the first semiconductor package 100 and each second semiconductor package 200 in a plan view. The third semiconductor package 300 may be a different type of semiconductor package from the first and second semiconductor packages 100 and 200. The third semiconductor package 300 may be provided as a single piece as shown in FIG. 1A. As another example, the third semiconductor package 300 may be provided in plural pieces as shown in FIG. 1B. In this case, the third semiconductor packages 300 may be spaced apart from each other. The number and planar arrangement of the third semiconductor packages 300 are not limited to those shown in FIGS. 1A and 1B and may be varied in various ways. Hereinafter, a single third semiconductor package 300 will be described. Third connection terminals 350 may be interposed between the substrate 500 and the third semiconductor package 300, as shown in FIG. 1C. The third semiconductor package 300 may be electrically connected to the substrate 500 through third connection terminals 350. The third connection terminals 350 may include solder balls, pillars, bumps, or ball grid arrays. The pitch of the third connection terminals 350 may be smaller than the pitch of the conductive terminals 550. The height H3 of the mounted third semiconductor package 300 may be defined to include the height of the third connection terminals 350. The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the third semiconductor package 300 mounted.

The first passive element 400 may be mounted on the top surface 500a of the substrate 500. The first passive element 400 may be arranged to be spaced apart from the first to third semiconductor packages 100, 200, and 300 in a plan view. The first passive element 400 may include any one of an inductor, a resistor, and a capacitor. As shown in FIG. 1D , first connection terminal portions 401 may be further provided between the substrate 500 and the first passive element 400 . The first connection terminal portions 401 may include, for example, solder, pillars, bumps, or ball grid arrays. The height H4 of the mounted first passive element 400 may be defined to include the height of the first connection terminal portions. For example, the height (H4) of the mounted first passive element 400 is the height (H41) of the first connection terminal portions 401 and the height (H40) of the first passive element 400' before mounting. It may be equal to the sum of . The height H4 of the mounted first passive element 400 may be substantially equal to the distance between the upper surface 500a of the substrate 500 and the uppermost surface of the first passive element 400. The first passive element 400 may be provided in plural numbers. As shown in FIGS. 1A and 1B , the first passive elements 400 may be spaced apart from each other. The number and planar arrangement of the first passive elements 400 may be varied in various ways. Hereinafter, the singular first passive element 400 will be described. In the drawings other than FIG. 1D, the first connection terminal portions 401 are omitted for simplicity, but the present invention is not limited thereto.

The heat dissipation structure 600 is connected to the first to third semiconductor packages 100, 200, and 300. and may be provided on the first passive element 400. The lower surface 600b of the heat dissipation structure 600 may face the first to third semiconductor packages 100, 200, and 300. The lower surface 600b of the heat dissipation structure 600 may be substantially flat. For example, the lower surface 600b of the heat dissipation structure 600 on the first semiconductor package 100, the lower surface 600b on the second semiconductor package 200, the lower surface 600b on the third semiconductor package 300, and The lower surface 600b on the first passive element 400 may be disposed at substantially the same level. Separate processing on the lower surface 600b of the heat dissipation structure 600 is omitted, so manufacturing of the heat dissipation structure 600 can be simplified. The processing may include forming a trench or forming a protrusion. The heat dissipation structure 600 may include a thermally conductive material. The thermally conductive material may include a metal (eg, copper and/or aluminum, etc.) or a carbon-containing material (eg, graphene, graphite, and/or carbon nanotubes, etc.). The heat dissipation structure 600 may have relatively high thermal conductivity. As an example, a single metal layer or a plurality of stacked metal layers may be used as the heat dissipation structure 600. As another example, the heat dissipation structure 600 may include a heat sink or heat pipe. As another example, the heat dissipation structure 600 may use a water cooling method. The heat dissipation structure 600 may include a first heat dissipation structure 610. The first heat dissipation structure 610 may be spaced apart from the substrate 500 .

The first heat-conducting layer 710 may be interposed between the first semiconductor package 100 and the heat dissipation structure 600. The first heat-conducting layer 710 may physically contact the upper surface of the first semiconductor package 100 and the lower surface 600b of the heat dissipation structure 600. The first heat-conducting layer 710 may include a thermal interface material (TIM). Thermal interface materials may include polymers and thermally conductive particles, for example. The thermally conductive particles may be dispersed within the polymer. When the first semiconductor package 100 operates, heat generated in the first semiconductor package 100 may be transferred to the heat dissipation structure 600 through the first heat-conducting layer 710.

According to embodiments, the sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat-conducting layer 710 is the height H4 of the mounted first passive element 400. It can be bigger than Even if the first passive element 400 is provided on the upper surface 500a of the substrate 500, the first heat-conducting layer 710 may be in physical contact with the first semiconductor package 100 and the heat dissipation structure 600. .

A second heat-conducting layer 720 may be provided between the second semiconductor package 200 and the heat dissipation structure 600. The second heat-conducting layer 720 may physically contact the upper surface of the second semiconductor package 200 and the lower surface 600b of the heat dissipation structure 600. The second heat-conducting layer 720 may include, for example, a thermal interface material (TIM). When the second semiconductor package 200 operates, heat generated in the second semiconductor package 200 may be transferred to the heat dissipation structure 600 through the second heat-conducting layer 720.

A third heat-conducting layer 730 may be provided between the third semiconductor package 300 and the heat dissipation structure 600. The third heat-conducting layer 730 may physically contact the upper surface of the third semiconductor package 300 and the lower surface 600b of the heat dissipation structure 600. The third heat-conducting layer 730 may include, for example, a thermal interface material (TIM). When the third semiconductor package 300 operates, heat generated in the third semiconductor package 300 may be transferred to the third semiconductor package 300 through the third heat-conducting layer 730.

When the package system 1 operates, a lot of heat may be generated in the first semiconductor package 100. For example, the first semiconductor package 100 may generate more heat than the second semiconductor package 200, the third semiconductor package 300, and the first passive element 400. The thermal characteristics of the first semiconductor package 100 may have a greater impact on the operating characteristics of the package system 1 than the thermal characteristics of the second and third semiconductor packages 200 and 300. As the thermal characteristics of the first semiconductor package 100 improve, the operating characteristics of the package system 1 may improve. The first to third heat conductive layers 710, 720, and 730 may have a lower thermal conductivity than the heat dissipation structure 600. As the thickness A1 of the first heat-conducting layer 710 decreases, heat generated in the first semiconductor package 100 can be dissipated more quickly to the heat dissipation structure 600. According to embodiments, the thickness A1 of the first heat-conducting layer 710 may be the smallest among the thicknesses of heat-conducting layers in contact with the lower surface 600b of the heat dissipation structure 600. Here, the heat-conducting layers may include first to third heat-conducting layers 710, 720, and 730. The heat-conducting layers may further include conductive adhesive patterns 741, which will be described later in FIGS. 2A to 2D. For example, the thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A2 of the second heat-conducting layer 720 and the thickness A3 of the third heat-conducting layer 730. Accordingly, heat generated in the first semiconductor package 100 can be transferred to the heat dissipation structure 600 more quickly. Packaged system 1 may exhibit improved operating characteristics.

Electronic devices 430 may be further provided on the top surface 500a of the substrate 500. The electronic device 430 may include an oscillator such as a crystal oscillator or a real-time clock. As shown in FIG. 1E, a conductive connection terminal 403 is further provided between the electronic device 430 and the upper surface 500a of the substrate 500, so that it can be electrically connected to the electronic device 430 and the substrate 500. The height H5 of the mounted electronic device 430 may be defined to include the height H51 of the conductive connection terminal 403. For example, the height H5 of the mounted electronic device 430 may be equal to the sum of the height H51 of the conductive connection terminal 403 and the height H50 of the electronic device 430' before mounting. there is. The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat-conducting layer 710 may be greater than the height H5 of the mounted electronic device 430. Even if the electronic device 430 is provided on the upper surface 500a of the substrate 500, the heat generated in the first semiconductor package 100 is smoothly discharged to the heat dissipation structure 600 through the first heat-conducting layer 710. It can be. As another example, the electronic device 430 may not be provided. In the drawings except FIG. 1E, the conductive connection terminal 403 is omitted for simplicity, but the present invention is not limited thereto. Hereinafter, the electrical connection of the semiconductor packages 100, 200, and 300 will be described.

As shown in FIG. 1C, the first semiconductor package 100 is electrically connected to the second semiconductor package 200, the third semiconductor package 300, and the conductive terminals 550 through the wiring 505 of the substrate 500. can be connected The second semiconductor package 200 may be electrically connected to the first semiconductor package 100, the third semiconductor package 300, and the conductive terminals 550 through the wiring 505 of the substrate 500. The third semiconductor package 300 may be electrically connected to the first semiconductor package 100, the second semiconductor package 200, and the conductive terminals 550 through the wiring 505 of the substrate 500.

The first underfill film 160 may be provided in the gap between the substrate 500 and the first semiconductor package 100 to seal the first connection terminals 150. The second underfill film 260 may be provided in the gap between the substrate 500 and the second semiconductor package 200 to seal the second connection terminals 250. A third underfill film 360 may be provided in the gap between the substrate 500 and the second semiconductor package 200 to seal the third connection terminals 350. The first to third underfill layers 160, 260, and 360 may include an insulating polymer such as an epoxy-based polymer. As the first to third underfill films 160, 260, and 360 are provided, the joint reliability of the first to third connection terminals 150, 250, and 350 can be improved. Unlike shown, at least one of the first to third underfill layers 160, 260, and 360 may be omitted.

A dam structure 590 may be further provided on the upper surface 500a of the substrate 500. The dam structure 590 may be disposed between the third semiconductor package 300 and the first passive element 400. The dam structure 590 may include liquid resin. Although not shown, the substrate 500 may include a plurality of layers, and the top layer of the layers may include an insulating polymer such as a solder resist material. For example, the dam structure 590 may be formed integrally with the uppermost layer of the substrate 500. In this case, the dam structure 590 may be connected to the uppermost layer of the substrate 500 without an interface. As another example, the dam structure 590 may include a material different from that of the substrate 500. For example, the dam structure 590 may be formed of the same material as any one of the first to third underfill films 160, 260, and 360. The height of the dam structure 590 may be equal to or smaller than the sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat-conducting layer 710.

The arrangement and number of dam structures 590 may be modified in various ways. For example, the dam structure 590 may be disposed between the first semiconductor package 100 and the first passive element 400. As another example, the dam structure 590 may be disposed between the second semiconductor package 200 and the first passive element 400. The dam structure 590 may be provided in plural pieces, as shown in FIG. 1A. Dam structures 590 may be spaced apart from each other. Hereinafter, each of the first to third semiconductor packages 100, 200, and 300 will be described in more detail.

FIG. 1F is a diagram illustrating a package system according to embodiments, and corresponds to a cross section taken along line I-II of FIG. 1A. Hereinafter, content that overlaps with what was previously described will be omitted. In the description of FIG. 1F, the description is made with reference to FIGS. 1A, 1B, and 1C.

Referring to FIG. 1F, the package system 1a includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction layers ( 710, 720, 730), and a heat dissipation structure 600.

The first semiconductor package 100 may include a first substrate 110, a first semiconductor chip 120, and a first molding film 130. As an example, a printed circuit board (PCB) may be used as the substrate 500. As another example, a redistribution layer may be used as the substrate 500. The first semiconductor chip 120 may be flip-chip mounted on the first substrate 110 . Connection parts may be provided between the first semiconductor chip 120 and the first substrate 110. Connections may include solder balls, pillars, bumps, or ball grid arrays. The first semiconductor chip 120 may be a system-on-chip (SOC), logic chip, or application processor (AP) chip. The first semiconductor chip 120 may include circuits that perform different functions. The first semiconductor chip 120 may include a logic circuit and a memory circuit. The first semiconductor chip 120 may further include at least one of a digital integrated circuit (IC), a wireless radio frequency integrated circuit (RFIC), and an input/output circuit. The fact that heat is generated from the first semiconductor package 100 may mean that heat is generated from the first semiconductor chip 120.

The first molding film 130 may be disposed on the first substrate 110 to cover the first semiconductor chip 120. The first molding film 130 may cover the side and top surfaces of the first semiconductor chip 120 and seal the first semiconductor chip 120. In this case, the top surface of the first semiconductor package 100 may correspond to the top surface of the first molding film 130. The first molding film 130 may include an insulating polymer such as an epoxy-based molding compound. The first molding film 130 may further extend into the gap between the first substrate 110 and the first semiconductor chip 120. Unlike shown, a separate underfill pattern may be filled in the gap between the first substrate 110 and the first semiconductor chip 120. The underfill pattern may be formed by thermal compression of a non-conductive paste or a non-conductive film, or a capillary underfill process. The height H1 of the mounted first semiconductor package 100 will be defined as the sum of the height of the first connection terminals 150, the height of the first substrate 110, and the height of the first molding film 130. You can.

The second semiconductor package 200 may include a second substrate 210, a second semiconductor chip 220, and a second molding film 230. A printed circuit board (PCB) or a rewiring layer may be used as the substrate 500. The second semiconductor chip 220 may be a different type of semiconductor chip than the first semiconductor chip 120. For example, the second semiconductor chip 220 may function as a memory chip. Memory chips may include DRAM chips. As another example, the memory chip may include SRAM, MRAM, and/or NAND flash memory. The fact that heat is generated from the second semiconductor package 200 may mean that heat is generated from the second semiconductor chip 220. The second semiconductor chip 220 may be mounted using a flip chip method or a bonding wire method. When the second semiconductor chip 220 is flip-chip mounted, a separate underfill pattern may be filled in the gap between the second substrate 210 and the second semiconductor chip 220. The second semiconductor package 200 may include a plurality of second semiconductor chips 220. As another example, the second semiconductor package 200 may include a single second semiconductor chip 220. The second molding film 230 may cover the side and top surfaces of the second semiconductor chip 220 and seal the second semiconductor chip 220. In this case, the top surface of the second semiconductor package 200 may correspond to the top surface of the second molding film 230. Unlike shown, the second molding film 230 may cover the side surfaces of the second semiconductor chip 220 and expose the top surface. In this case, the top surface of the second semiconductor package 200 may correspond to the top surface of the second molding film 230 and the top surface of the second semiconductor chip 220 exposed by the second molding film 230. The second molding film 230 may include an insulating polymer such as an epoxy-based polymer. The height H2 of the mounted second semiconductor package 200 may be equal to the sum of the height of the second connection terminals 250, the height of the second substrate 210, and the height of the second molding film 230. You can.

The third semiconductor package 300 may include a third substrate 310, a third semiconductor chip 320, and a third molding film 330. A redistribution layer or a printed circuit board may be used as the third substrate 310. When the redistribution layer is used as the third substrate 310, the third semiconductor package 300 is a fan-out panel level package or a fan-out wafer level package. It can be manufactured with The third semiconductor chip 320 may be a different type of semiconductor chip from the first semiconductor chip 120 and the second semiconductor chip 220. For example, the third semiconductor chip 320 may include a power management integrated circuit (PMIC) and function as a power management chip. The fact that heat is generated from the third semiconductor package 300 may mean that heat is generated from the third semiconductor chip 320. A third molding film 330 may be provided on the third substrate 310 to cover the top and side surfaces of the third semiconductor chip 320. In this case, the top surface of the third semiconductor package 300 may correspond to the top surface of the third molding film 330. As another example, the third molding film 330 may cover the side surfaces of the third semiconductor chip 320 and expose the top surface. In this case, the top surface of the third semiconductor package 300 may correspond to the top surface of the third molding film 330 and the top surface of the third semiconductor chip 320 exposed by the third molding film 330. The third molding film 330 may include an insulating polymer such as an epoxy polymer. The height H3 of the mounted third semiconductor package 300 will be defined as the sum of the height of the third connection terminals 350, the height of the third substrate 310, and the height of the third molding film 330. You can. Formation of the third semiconductor package 300 includes providing a third semiconductor chip 320 on a carrier substrate, forming a third molding film 330 covering the third semiconductor chip 320, and forming a carrier substrate. This may include exposing the lower surface of the third semiconductor chip 320 by removing it, and forming a redistribution layer on the exposed lower surface of the third semiconductor chip 320 and the lower surface of the molding film. In this case, the redistribution layer may be the third substrate 310.

FIG. 1g corresponds to an enlarged view of area III of FIG. 1a. Figure 1h is a cross-section taken along line I'-II' of Figure 1g. In the following descriptions, FIGS. 1A, 1B, 1C, and 1D are referred to together.

Referring to FIGS. 1G and 1H , a first marker 139 may be provided on the first molding film 130 . For example, the first marker 139 may be provided on the upper surface of the first molding film 130. Alternatively, the first marker 139 may be provided on the side of the first molding film 130. The first marker 139 may be a recessed portion on one surface of the first molding film 130. Formation of the first marker 139 may include removing a portion of the first molding film 130. When the first marker 139 is formed on the first semiconductor chip 120, the first semiconductor chip 120 may be damaged during the marker formation process. For example, cracks may be formed on or within the first semiconductor chip 120 . According to embodiments, as the first marker 139 is provided on the first molding film 130, the first semiconductor chip 120 may not be damaged during the formation of the first marker 139. The first marker 139 may provide and display information about the first semiconductor package 100. In drawings other than FIGS. 1G to 1I, the first marker 139 is omitted for convenience, but the present invention is not limited thereto.

The first heat-conducting layer 710 may be formed on the top surface of the first semiconductor package 100. Formation of the first heat-conducting layer 710 may include providing a thermal interface material on the first semiconductor package 100 and then curing the thermal interface material. The thermal interface material prior to curing may have fluidity. In the process of forming the first heat-conducting layer 710, even if the thermal interface material on the edge area of the upper surface of the first semiconductor package 100 flows down to the side 100c of the first semiconductor package 100, the first semiconductor package 100 The thermal interface material on the center region of the upper surface of (100) may not flow. Accordingly, the first heat-conducting layer 710 can satisfactorily fill the gap between the center region of the upper surface of the first semiconductor package 100 and the heat dissipation structure 600. For example, the top surface 710a of the first heat-conducting layer 710 in the center area of the first semiconductor package 100 may physically contact the heat-conducting layer 710. According to embodiments, since the first molding film 130 is provided, the first semiconductor chip 120 may be provided in the center area of the first semiconductor package 100 from a plan view. Accordingly, even if some of the thermal interface material flows during the formation of the first heat-conducting layer 710. The first heat-conducting layer 710 can effectively transfer heat from the first semiconductor chip 120 to the first heat dissipation structure 610. When the first molding film 130 includes the first marker 139, the first heat-conducting layer 710 may extend into the first marker 139. Referring to FIG. 1C, a second heat-conducting layer 720 may be provided on the upper surface of the second molding film 230. Formation of the second heat-conducting layer 720 may be performed by substantially the same method as previously described in the process of forming the first heat-conducting layer 710. Even if some of the thermal interface material flows down during the formation of the second heat-conducting layer 720, the second heat-conducting layer 720 closes the gap between the center region of the upper surface of the second semiconductor package 200 and the heat dissipation structure 600. It can be filled well. The center area of the second semiconductor package 200 may be an area where the second semiconductor chip 220 is provided. Accordingly, the heat generated in the second semiconductor chip 220 can be efficiently dissipated to the heat dissipation structure 600 through the second heat-conducting layer 720.

Although not shown, a second marker may be further provided on the second molding film 230. The second marker may be a recessed portion of the second molding film 230.

A third heat-conducting layer 730 may be formed on the upper surface of the third molding film 330. The formation of the third heat-conducting layer 730 may be performed by substantially the same method as described above in the process of forming the first heat-conducting layer 710. At this time, even if some of the thermal interface material flows down during the formation of the third heat-conducting layer 730. The third heat-conducting layer 730 can satisfactorily fill the gap between the center region of the upper surface of the third semiconductor package 300 and the heat dissipation structure 600. The center area of the third semiconductor package 300 may be an area where the third semiconductor chip 320 is provided. Accordingly, the thermal characteristics of the third semiconductor package 300 may be improved. Although not shown, a third marker may be further provided on the third molding film 330. The third marker may be a recessed portion of the third molding film 330.

FIG. 1I is a diagram for explaining a first semiconductor package according to embodiments, and corresponds to a cross section cut along line I'-II' of 1g.

Referring to FIGS. 1G and 1I , the first semiconductor package 100 may include a first substrate 110, a first semiconductor chip 120, and a first molding film 130. The first molding film 130 may cover the side surfaces of the first semiconductor chip 120 and expose the top surface. In this case, the top surface of the first semiconductor package 100 may correspond to the top surface of the first molding film 130 and the top surface of the first semiconductor chip 120 exposed by the first molding film 130. The exposed upper surface of the first semiconductor chip 100 may be in direct physical contact with the first heat-conducting layer 710. Heat generated in the first semiconductor chip 100 may be transferred to the heat dissipation structure 600 through the first heat-conducting layer 710. Accordingly, the heat dissipation characteristics of the first semiconductor chip 100 can be further improved.

Figure 2A is a plan view showing a package system according to embodiments. Figure 2b is a cross-section taken along line I-II of Figure 2a. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2A and 2B, the package system 1b includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The substrate 500, the first to third semiconductor packages 100, 200, and 300, the first passive element 400, and the first to third heat conductive layers 710, 720, and 730 are previously described in FIGS. 1A to 1A. It may be substantially the same as described in FIG. 1I.

A ground pad 510G may be provided on the top surface 500a of the substrate 500. At least one of the conductive terminals 550 may function as a ground terminal. A ground voltage may be applied to the ground pad 510G through the ground terminal and the substrate 500.

The heat dissipation structure 600 may include a second heat dissipation structure 620. The second heat dissipation structure 620 may include a body portion 621 and a leg portion 622. The body portion 621 of the second heat dissipation structure 620 may be similar to the first heat dissipation structure 610 previously described in FIGS. 1A to 1C. The lower surface 600b of the heat dissipation structure 600 may include the lower surface of the body portion 621 of the second heat dissipation structure 620. For example, the body portion 621 may be provided on the top surfaces of the first semiconductor package 100, the second semiconductor package 200, and the first passive element 400. The first heat-conducting layer 710 may physically contact the lower surface of the body portion 621 of the second heat dissipation structure 620.

The leg portion 622 of the second heat dissipation structure 620 may be provided between the edge region of the body portion 621 and the substrate 500. The leg portion 622 of the second heat dissipation structure 620 may be connected to the body portion 621. As shown in FIG. 2A , the first semiconductor package 100, the second semiconductor package 200, and the first passive element 400 may be spaced apart from the leg portion 622 of the second heat dissipation structure 620. The leg portion 622 may be provided in an edge area of the substrate 500 from a plan view. The second heat dissipation structure 620 may include a thermally conductive material.

The second heat dissipation structure 620 has electrical conductivity and can shield electromagnetic interference (EMI) of the first to third semiconductor packages 100, 200, and 300. Electromagnetic interference means that electromagnetic waves radiated or conducted from an electrical element cause interference in the reception/transmission function of other electrical elements. By the second heat dissipation structure 620, the operations of the first to third semiconductor packages 100, 200, 300 and the first passive element 400 are prevented from interfering with the operation of other packages or being interfered with by other packages. It may not be possible.

Adhesion patterns 741 and 742 may be provided between the substrate 500 and the leg portion 622 of the second heat dissipation structure 620 to fix the second heat dissipation structure 620 to the substrate 500. The adhesive patterns 741 and 742 may include a conductive adhesive pattern 741 and an insulating adhesive pattern 742. The conductive adhesive pattern 741 may be provided between the ground pad 510G and the leg portion 622 of the second heat dissipation structure 620. The second heat dissipation structure 620 may be connected to the ground pad 510G through a conductive adhesive pattern 741.

If a certain amount of charge or more is accumulated in the heat dissipation structure 600, the charge may flow from the heat dissipation structure 600 to other electrically conductive components and damage the electrically conductive components. The electrically conductive components include integrated circuits and wiring in the first to third semiconductor chips 120, 220, and 320, wiring in the first to third substrates 110, 210, and 310, and first to third semiconductor chips 120, 220, and 320. It may include at least one of three connection terminals 350 and wires within the substrate 500. According to embodiments, a ground voltage may be applied to the second heat dissipation structure 620 by the conductive adhesive pattern 741. Accordingly, the second heat dissipation structure 620 can prevent electrical damage to the package system 1b due to electrostatic discharge (ESD).

An insulating adhesive pattern 742 may be provided between the substrate 500 and the heat dissipation structure 600. Accordingly, the heat dissipation structure 600 is insulated from the substrate 500, and the occurrence of an electrical short can be prevented. The thickness A5 of the conductive adhesive pattern 741 may be substantially the same as the thickness of the insulating adhesive pattern 742.

The height B of the leg portion 622 of the second heat dissipation structure 620 may be lower than the height H1 of the mounted first semiconductor package 100. At this time, the height B of the leg portion 622 may be equal to the height of the inner surface of the second heat dissipation structure 620. The conductive adhesive pattern 741 may physically contact the lower surface of the leg portion 622. Accordingly, the thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness of the adhesive patterns 741 and 742 (for example, the thickness A5 of the conductive adhesive pattern 741). Since the thickness A1 of the first heat-conducting layer 710 is small, heat generated in the first semiconductor package 100 can be more quickly transferred to the heat dissipation structure 600 through the first heat-conducting layer 710.

Figure 2C is a plan view showing a package system according to embodiments. FIG. 2D is a cross-section taken along line I-II of FIG. 2C. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2C and 2D, the package system 1c includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The heat dissipation structure 600 may include the second heat dissipation structure 620 described in FIGS. 2A and 2B. For example, the second heat dissipation structure 620 may include a body portion 621 and a leg portion 622.

A conductive adhesive pattern 741 is provided between the ground pad 510G and the leg portion 622 of the second heat dissipation structure 620 to connect to the second heat dissipation structure 620 and the ground pad 510G. Unlike the examples of FIGS. 2A and 2B, a separate insulating adhesive pattern 742 may not be provided. The thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A5 of the conductive adhesive pattern 741.

The substrate 500, the first to third semiconductor packages 100, 200, and 300, the first passive element 400, and the first to third heat conductive layers 710, 720, and 730 are previously described in FIGS. 1A to 1A. It may be substantially the same as described in FIG. 1I.

FIG. 2E is a diagram illustrating a package system according to embodiments, and corresponds to a cross section taken along line I-II in FIG. 2C. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2C and 2E, the package system 1d includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The substrate 500, the first to third semiconductor packages 100, 200, and 300, the first passive element 400, and the first to third heat conductive layers 710, 720, and 730 are previously described in FIGS. 1A to 1A. It may be substantially the same as described in FIG. 1E.

The heat dissipation structure 600 may include a first heat dissipation structure 610, a second heat dissipation structure 620, and a heat dissipation layer 630. The first heat dissipation structure 610 may be substantially the same as previously described in FIGS. 1A to 1C. However, the first heat dissipation structure 610 may be disposed on the upper surface of the second heat dissipation structure 620. The second heat dissipation structure 620 may be substantially the same as the second heat dissipation structure 620 previously described with reference to FIGS. 2A to 2D. For example, the second heat dissipation structure 620 may include a body portion 621 and a leg portion 622. The width of the first heat dissipation structure 610 may be the same as or wider than the width of the second heat dissipation structure 620. A conductive adhesive pattern 741 may be provided between the ground pad 510G and the first heat dissipation structure 610. As another example, an insulating adhesive pattern 742 as described in the examples of FIGS. 2A and 2B may be further provided. The heat dissipation layer 630 may be interposed between the first heat dissipation structure 610 and the second heat dissipation structure 620. The heat dissipation layer 630 may include, for example, a thermal interface material.

FIG. 3A is a cross-sectional view showing a package system according to embodiments, taken along line I-II of FIG. 2A. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2C and 3A, the package system 1e includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600.

The first semiconductor package 100 includes a first substrate 110, a first semiconductor chip 120, and a first molding film 130, as well as a first adhesive layer 141 and a first heat conduction structure 140. can do. The first heat conduction structure 140 may have relatively high heat conductivity. The first heat-conducting structure 140 may include the heat-conductive material described in the examples of FIGS. 1A to 1C. As an example, the first heat-conducting structure 140 may include a metal layer, a heat sink, or a heat pipe. As another example, the first heat conduction structure 140 may use a water cooling method. The first adhesive layer 141 may be provided between the first molding film 130 and the first heat-conducting structure 140. The first adhesive layer 141 may include a thermal interface material. When the first semiconductor package 100 operates, heat generated in the first semiconductor chip 120 may be transferred to the first heat-conducting layer 710 through the first adhesive layer 141 and the first heat-conducting structure 140.

According to embodiments, the top surface of the first semiconductor package 100 may correspond to the top surface of the first heat-conducting structure 140. The height H1 of the mounted first semiconductor package 100 is the height of the first connection terminals 150, the height of the first substrate 110, the height of the first molding film 130, and the first adhesive layer 141. ) may be equal to the sum of the height of the height and the height of the first heat-conducting structure 140. Even if the top surface of the first molding film 130 is provided at a lower level than the top surface of the second semiconductor package 200 or the top surface of the third semiconductor package 300, the first adhesive layer 141 and the first heat conduction structure 140 ), the height H1 of the first semiconductor package 100 is equal to the height H2 of the second semiconductor package 200 and the height H3 of the third semiconductor package 300. It can be bigger than The thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A2 of the second heat-conducting layer 720 and the thickness A3 of the third heat-conducting layer 730. Accordingly, the thermal characteristics of the first semiconductor package 100 may be improved.

The substrate 500, the first and third semiconductor packages 100 and 300, the first passive element 400, the first to third heat conductive layers 710, 720, and 730, and the heat dissipation structure 600 are shown in FIG. It may be substantially the same as described in FIGS. 1A to 1F and FIGS. 2A to 2E.

FIG. 3B is a cross-sectional view showing a package system according to embodiments, taken along line I-II of FIG. 2C. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2C and 3B, the package system 1f includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The substrate 500, the first semiconductor package 100, the first passive element 400, the first to third heat-conducting layers 710, 720, and 730, and the heat dissipation structure 600 are substantially as described above. may be the same.

The second semiconductor package 200 includes a second substrate 210, a second semiconductor chip 220, and a second molding film 230, as well as a second adhesive layer 241 and a second heat conduction structure 240. can do. The second heat-conducting structure 240 may include a heat-conductive material and have relatively high heat conductivity. The second heat-conducting structure 240 may include a metal layer, a heat sink, or a heat pipe. A second adhesive layer 241 may be provided between the second molding film 230 and the second heat-conducting structure 240. The second adhesive layer 241 may include a thermal interface material. When the second semiconductor package 200 is operated, heat generated from the second semiconductor chip 220 may be transferred to the second heat-conducting layer 720 through the second adhesive layer 241 and the second heat-conducting structure 240. there is.

The top surface of the second semiconductor package 200 may correspond to the top surface of the second heat-conducting structure 240. The height H2 of the mounted second semiconductor package 200 is the height of the second connection terminals 250, the height of the second substrate 210, the height of the second molding film 230, and the second adhesive layer 241. ) may be equal to the sum of the height of the height and the height of the second heat-conducting structure 240. The height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200. Accordingly, the thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A2 of the second heat-conducting layer 720.

The third semiconductor package 300 includes a third substrate 310, a third semiconductor chip 320, and a third molding film 330, as well as a third adhesive layer 341 and a third heat conduction structure 340. can do. The third heat-conducting structure 340 includes a heat-conductive material and may have relatively high heat conductivity. The third heat conduction structure 340 may include a metal layer, a heat sink, or a heat pipe. A third adhesive layer 341 may be provided between the third molding film 330 and the second heat-conducting structure 240. The third adhesive layer 341 may include a thermal interface material. When the third semiconductor package 300 operates, heat generated from the third semiconductor chip 320 may be transferred to the third heat-conducting layer 730 through the third adhesive layer 341 and the third heat-conducting structure 340. there is.

The top surface of the third semiconductor package 300 may correspond to the top surface of the third heat-conducting structure 340. The height H3 of the mounted third semiconductor package 300 is the height of the third connection terminals 350, the height of the third substrate 310, the height of the third molding film 330, and the third adhesive layer 341. ) may be equal to the sum of the height of the and the height of the third heat-conducting structure 340. The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the third semiconductor package 300 mounted. Accordingly, the thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A3 of the third heat-conducting layer 730.

Unlike shown, the second heat-conducting layer 720 and the second heat-conducting structure 240 are omitted, and the second heat-conducting layer 720 may directly contact the upper surface of the second molding film 230 as shown in FIG. 1D. there is. As another example, the third heat-conducting layer 730 and the third heat-conducting structure 340 may be omitted, and the third heat-conducting layer 730 may directly contact the upper surface of the third molding film 330.

FIG. 3C is a cross-sectional view showing a package system according to embodiments, taken along line I-II of FIG. 2A. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2C and 3C, the package system 1g includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The substrate 500, the first to third semiconductor packages 300, the first passive element 400, the first to third heat conductive layers 730, and the heat dissipation structure 600 may be substantially the same as described above. there is.

The first semiconductor package 100 may be substantially the same as described in the example of FIG. 3A. For example, the first semiconductor package 100 includes a first substrate 110, a first semiconductor chip 120, a first molding film 130, a first adhesive layer 141, and a first heat conduction structure 140. may include. The second semiconductor package 200 and the third semiconductor package 300 may each be substantially the same as described in the example of FIG. 3B. The second semiconductor package 200 may include a second substrate 210, a second semiconductor chip 220, a second molding film 230, a second adhesive layer 241, and a second heat conduction structure 240. there is. The third semiconductor package 300 may include a third substrate 310, a third semiconductor chip 320, a third molding film 330, a third adhesive layer 341, and a third heat conduction structure 340. there is.

The height H1 of the first semiconductor package 100 may be greater than the height H2 of the second semiconductor package 200 and the height H3 of the third semiconductor package 300. The thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A2 of the second heat-conducting layer 720 and the thickness A3 of the third heat-conducting layer 730. .

FIG. 4A is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II in FIG. 2C. FIG. 4B is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II in FIG. 2C. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2C, 4A, and 4B, the package system 1h, 1i includes a substrate 500, first to third semiconductor packages 100, 200, and 300, a first passive element 400, It may include first to third heat conductive layers 710, 720, and 730, and a heat dissipation structure 600. The substrate 500, the first to third semiconductor packages 300, the first passive element 400, the first to third heat conductive layers 710, 720, 730, and the heat dissipation structure 600 are as described above. may be substantially the same.

As shown in FIG. 4A, the package system 1h may not include the second heat-conducting layer 720. The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat-conducting layer 710 may be greater than the height H2 of the mounted second semiconductor package 200.

As shown in FIG. 4B, the package system 1i may not include the third heat-conducting layer 730. The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat-conducting layer 710 may be greater than the height H3 of the mounted third semiconductor package 300.

FIG. 4C is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II of FIG. 2C. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 2C and 4C, the package system 1j includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A2 of the second heat-conducting layer 720 and the thickness A3 of the third heat-conducting layer 730.

The fourth heat-conducting layer 740 is provided between the first passive element 400 and the heat dissipation structure 600, and is in physical contact with the upper surface of the first passive element 400 and the lower surface 600b of the heat dissipation structure 600. can do. The fourth heat-conducting layer 740 may include a thermal interface material. Heat generated from the first passive element 400 may be transferred to the heat dissipation structure 600 through the fourth heat-conducting layer 740. The height H1 of the mounted first semiconductor package 100 may be greater than the height H4 of the mounted first passive element 400. For example, the top surface of the first semiconductor package 100 may be placed at a higher level than the top surface of the first passive element 400. Accordingly, the thickness A1 of the first heat-conducting layer 710 may be smaller than the thickness A4 of the fourth heat-conducting layer 740.

As another example, either the second heat-conducting layer 720 or the third heat-conducting layer 730 may be omitted.

In the description of FIGS. 3A to 3C and FIGS. 4A to 4C , either the first heat dissipation structure 610 or the second heat dissipation structure 620 may be omitted. In this case, the heat dissipation layer 630 may not be provided.

In the description of FIGS. 4A to 4C , the first semiconductor package 100 may further include a first adhesive layer 141 and a first heat-conducting structure 140. The second semiconductor package 200 may further include a second adhesive layer 241 and a second heat-conducting structure 240. The third semiconductor package 300 may further include a third adhesive layer 341 and a third heat-conducting structure 340.

5A is a cross-sectional view showing a semiconductor module according to embodiments. FIG. 5B is a diagram for explaining a second passive element according to embodiments, and is an enlarged cross-section of region C of FIG. 5A. FIG. 5C is a diagram for explaining lower pads and conductive terminals according to embodiments, and is an enlarged view of area IV of FIG. 5A. FIG. 5D is a diagram for explaining lower pads according to embodiments. Hereinafter, content that overlaps with what was previously described will be omitted.

Referring to FIGS. 1A, 5A, and 5B, the semiconductor module 10 may include a board 1000 and a package system 1. For example, a printed circuit board may be used as the board 1000. Conductive pads 1500 may be provided on the top surface 1000a of the board 1000. The conductive pads 1500 may be electrically connected to internal wiring (not shown) of the board 1000. In this specification, being electrically connected to the board 1000 may mean being electrically connected to internal wiring of the board 1000.

The package system 1 described in FIGS. 1A to 1C may be mounted on the board 1000 to form the semiconductor module 10. As another example, the package system 1a of FIG. 1D, the package system 1b of FIGS. 2A and 2B, the package system 1c of FIGS. 2C and 2D, the package system 1d of FIG. 2E, and the package system of FIG. 3A. (1e), the package system 1f in Figure 3b, the package system 1g in Figure 3c, the package system 1h in Figure 4a, the package system 1i in Figure 4b, or the package system 1j in Figure 4c. By mounting on the board 1000, the semiconductor module 10 may be formed. For convenience, the package system 1 of FIGS. 1A to 1C is shown and described with respect to the semiconductor module 10 mounted on the board 1000, but the present invention is not limited thereto.

Mounting the package system 1 involves providing the package system 1 on the board 1000 so that the conductive terminals 550 face the board 1000, and attaching the conductive terminals 550 to the conductive pads ( 1500). The pitch of the conductive terminals 550 may be substantially the same as the pitch P4 of the conductive pads 1500. The pitch P4 of the conductive pads 1500 may be standardized. For example, the pitch P4 of the conductive pads 1500 may satisfy the JEDEC standard. The pitch P4 of the conductive pads 1500 may be relatively large. For example, the pitch P4 of the conductive pads 1500 may be 0.65 mm or more.

When the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 are mounted directly on the board 1000, the pitch P1 of the first connection terminals 150, Each of the pitch P2 of the two connection terminals 250 and the pitch P3 of the third connection terminals 350 may be required to be substantially equal to the pitch P4 of the conductive pads 1500. . According to embodiments, the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 may be connected to the board 1000 through the substrate 500. Accordingly, the pitch (P1) of the first connection terminals 150, the pitch (P2) of the second connection terminals 250, and the pitch (P3) of the third connection terminals 350 are conductive pads ( It can be freely designed without being restricted by the pitch (P4) of 1500).

The pitch P1 of the first connection terminals 150 may be smaller than the pitch P4 of the conductive pads 1500. For example, the pitch P1 of the first connection terminals 150 may be 0.4 mm or less. Accordingly, the first connection terminals 150 are provided more densely, so the planar area of the first semiconductor package 100 can be reduced. Each of the pitch P2 of the second connection terminals 250 and the pitch P3 of the third connection terminals 350 may be smaller than the pitch P4 of the conductive pads 1500 . For example, the pitch (P2) of the second connection terminals 250 and the pitch (P3) of the third connection terminals 350 may each be 0.4 mm or less. Accordingly, the second semiconductor package 200 and the third semiconductor package 300 can be miniaturized. Since the first to third semiconductor packages 100, 200, and 300 are miniaturized, the distances between the first to third semiconductor packages 100, 200, and 300 may be reduced. Accordingly, the lengths of electrical signal paths between the first to third semiconductor packages 100, 200, and 300 may be reduced. The operating speed and reliability of the package system 1 can be improved.

The second passive element 420 may be mounted on the lower surface 1000b of the board 1000. As shown in FIG. 5B , second connection terminal portions 402 may be further provided between the board 1000 and the second passive element 420 . The second passive element 420 may be connected to the board 1000 through the second connection terminal portions 402. The second connection terminal portions 402 may include, for example, solder, pillars, bumps, or ball grid arrays. The height H6 of the mounted second passive element 420 may be defined to include the height H61 of the second connection terminal portions 402. The height H6 of the mounted second passive element 420 may be defined to include the height H61 of the second connection terminal portions 402. For example, the height (H6) of the mounted second passive element 420 is the height (H61) of the second connection terminal portions 402 and the height (H60) of the first passive element 420' before mounting. It may be equal to the sum of . For example, the height H6 of the mounted second passive element 420 may be greater than the sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first heat-conducting layer 710. there is. Even if the height H6 of the mounted second passive element 420 is large, the second passive element 420 may be electrically connected to the package system 1 through the substrate 500.

The second passive element 420 may be electrically connected to any one of the first to third semiconductor packages 100, 200, and 300. The second passive element 420 may be provided to overlap or be adjacent to one of the semiconductor packages 100, 200, and 300 from a plan view. Accordingly, the signal length between the second passive element 420 and one of the semiconductor packages 100, 200, and 300 may be reduced. Accordingly, the electrical characteristics of the semiconductor module 10 may be improved.

The second passive element 420 may be provided in plural numbers. In this case, the heights H6 of the second passive elements 420 may be the same or different from each other. The number of second passive elements 420 may vary. Hereinafter, the conductive terminals 550 and the lower pads 540 will be described with reference to FIGS. 5C and 5D.

Lower pads 540 may be provided on the lower surface of the substrate 500 . The lower pads 540 may include a connection pad 541 and a test pad 542. During the manufacturing process of the package system 1 or before the package system 1 is mounted on the module 10 substrate 500, the electrical characteristics of the package system 1 may be evaluated. Evaluation of the electrical characteristics can be performed using a test pad 542. For example, a probe (not shown) contacts the test pad 542 to detect among the first to third semiconductor packages 100, 200, 300, the first passive device 400, and the electronic device 430. At least one electrical characteristic and connection relationship can be evaluated. Afterwards, conductive terminals 550 are formed, and the package system 1 can be mounted on the board 1000.

As shown in FIG. 5C, the conductive terminals 550 may include a first terminal 551 and a second terminal 552. The first terminal 551 is provided on the lower surface of the connection pad 541 and can be connected to the connection pad 541 and one of the conductive pads 1500. The first terminal 551 may electrically connect the package system 1 to the board 1000. The first terminal 551 may function as a signal transmission path.

The second terminal 552 is provided on the lower surface of the test pad 542 and can be connected to the test pad 542. As an example, the second terminal 552 may function as a ground terminal. The ground voltage may be transmitted to the package system 1 through the board 1000 and the second terminal 552. As another example, the second terminal 552 may be a dummy terminal. For example, the second terminal 552 may not be electrically connected to the internal wiring within the board 1000. Alternatively, the second terminal 552 may not be electrically connected to the package system 1.

As shown in FIG. 5D, the second terminal (552 in FIG. 5C) may not be provided. The test pad 542 may be spaced apart from the board 1000 and electrically insulated. Although not shown, underfill material may further fill the gap between the board 1000 and the test pad 542. The underfill material may include an insulating polymer.

The detailed description of the invention above is not intended to limit the invention to the disclosed embodiments, and can be used in various other combinations, changes, and environments without departing from the gist of the invention. The appended claims should be construed to include other embodiments as well.

Claims (20)

Board;
a first semiconductor package mounted on the substrate and including a system on chip;
a second semiconductor package mounted on the substrate and including a memory chip;
a first passive element mounted on the substrate;
a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the first passive element;
a first heat-conducting layer interposed between the first semiconductor package and the heat dissipation structure; and
It includes a second heat-conducting layer interposed between the second semiconductor package and the heat dissipation structure,
The sum of the height of the mounted first semiconductor package and the height of the first heat-conducting layer is greater than the height of the mounted first passive element,
The height of the mounted first semiconductor package is greater than the height of the mounted second semiconductor package,
The thickness of the first heat-conducting layer is smaller than the thickness of the second heat-conducting layer,
The heat dissipation structure has a first part that vertically overlaps the first semiconductor package and a second part that vertically overlaps the second semiconductor package,
A semiconductor package system wherein the lowermost portion of the first portion and the lowermost portion of the second portion are disposed farther from the substrate than the uppermost portion of the first semiconductor package.
According to clause 1,
Further comprising a second heat-conducting layer provided between the second semiconductor package and the heat dissipation structure,
A semiconductor package system in which the thickness of the first heat-conducting layer is smaller than the thickness of the second heat-conducting layer. According to clause 2,
The first heat-conducting layer and the second heat-conducting layer are in physical contact with the heat dissipation structure. According to clause 1,
The first semiconductor package includes a first substrate, a first semiconductor chip, and a first molding film,
The first semiconductor chip is a semiconductor package system including a system-on-chip. According to clause 4,
The first semiconductor package further includes a first heat-conducting structure provided on the first molding film. According to clause 5,
A semiconductor package system wherein the top surface of the first molding film is provided at a lower level than the top surface of the second semiconductor package. According to clause 1,
The second semiconductor package is a semiconductor package system including a second substrate, a second semiconductor chip, a second molding film, and a second heat-conducting structure provided on the second molding film. According to clause 1,
a ground pattern provided on the top surface of the substrate; and
Further comprising a conductive adhesive pattern interposed between the ground pattern and the heat dissipation structure,
The heat dissipation structure is:
A body portion extending parallel to the upper surface of the substrate
It is connected to the body portion and includes a bridge portion provided between the substrate and the body portion,
A semiconductor package system wherein the heat dissipation structure is electrically connected to the ground pattern through the conductive adhesive pattern. According to clause 8,
A semiconductor package system in which the thickness of the first heat-conducting layer is smaller than the thickness of the conductive adhesive pattern. According to clause 1,
a board provided on the lower surface of the substrate;
conductive terminals connected to the substrate and the board; and
It further includes a second passive element mounted on the bottom of the board,
A semiconductor package system wherein the height of the mounted second passive element is greater than the height of the mounted first semiconductor package. According to clause 10,
It further includes first connection terminals interposed between the board and the first semiconductor package,
A semiconductor package system wherein the pitch of the first connection terminals is smaller than the pitch of the conductive terminals.
Board;
a first semiconductor package mounted on the upper surface of the substrate and including a first semiconductor chip, the first semiconductor chip including logic circuits and memory circuits;
a second semiconductor package mounted on the upper surface of the substrate;
a passive element mounted on the upper surface of the substrate;
a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the passive element; and
Includes a plurality of heat-conducting layers each in physical contact with the lower surface of the heat dissipation structure,
The heat-conducting layers include a first heat-conducting layer provided on the upper surface of the first semiconductor package, and the first heat-conducting layer has the thinnest thickness among the heat-conducting layers,
The heat dissipation structure has a first part that vertically overlaps the first semiconductor package and a second part that vertically overlaps the second semiconductor package,
A semiconductor package system wherein the lowermost portion of the first portion and the lowermost portion of the second portion are disposed farther from the substrate than the uppermost portion of the first semiconductor package.
According to clause 12,
A semiconductor package system wherein the height of the mounted first semiconductor package is greater than the height of the mounted second semiconductor package. According to clause 13,
The first semiconductor package is:
A first substrate, the first semiconductor chip is provided on the substrate;
a first molding film covering the first semiconductor chip; and
A semiconductor package system further comprising a first heat-conducting structure provided on the first molding film. According to clause 12,
A semiconductor package system wherein the sum of the height of the mounted first semiconductor package and the thickness of the first heat-conducting layer is greater than the height of the mounted passive element. According to clause 12,
A semiconductor package system wherein the heat-conducting layers include a second heat-conducting layer provided on an upper surface of the second semiconductor package. According to clause 16,
A semiconductor package system wherein the second semiconductor package includes a power semiconductor chip or a memory chip.
Board;
a first semiconductor package mounted on the substrate and including a first semiconductor chip, the first semiconductor chip including logic circuits and memory circuits;
a second semiconductor package mounted on the substrate;
Passive elements mounted on the board;
a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the passive element;
a first heat-conducting layer provided on the first semiconductor package and physically contacting the heat dissipation structure; and
A second heat-conducting layer provided on the second semiconductor package and physically contacting the heat dissipation structure,
The first heat-conducting layer has a smaller thickness than the second heat-conducting layer,
The top surface of the first heat-conducting layer is provided at a higher level than the top surface of the passive element,
The heat dissipation structure has a first part that vertically overlaps the first semiconductor package and a second part that vertically overlaps the second semiconductor package,
A semiconductor package system wherein the lowermost portion of the first portion and the lowermost portion of the second portion are disposed farther from the substrate than the uppermost portion of the first semiconductor package.
According to clause 18,
a third semiconductor package mounted on the substrate; and
It further includes a third heat-conducting layer provided on the third semiconductor package and in physical contact with the heat dissipation structure,
A semiconductor package system wherein the first heat-conducting layer has a thickness smaller than the third heat-conducting layer. According to clause 18,
The second semiconductor package includes a second substrate, a second semiconductor chip, and a second molding film,
A semiconductor package system wherein the second semiconductor chip is of a different type from the first semiconductor chip.