KR102607109B1 - Semiconductor package system - Google Patents

Abstract

According to the present invention, a semiconductor package system is provided. A semiconductor package system according to embodiments includes a substrate; a first semiconductor package mounted on the upper surface of the substrate and including a first semiconductor chip, the first semiconductor chip including logic circuits; a first heat-conducting layer provided on the first semiconductor package; a second semiconductor package mounted on the upper surface of the substrate; a first passive element mounted on the top surface of the substrate; and a heat dissipation structure provided on the first heat-conducting layer, the second semiconductor package, and the first passive element.

Description

Semiconductor package system

The present invention relates to a semiconductor package system, and more specifically to a semiconductor package system provided with a heat dissipation structure.

A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. As semiconductor packages become faster and have higher capacities, the power consumption of semiconductor packages is increasing. The importance of thermal characteristics of semiconductor packages is increasing.

The problem to be solved by the present invention is to provide a package system with improved thermal properties and a semiconductor module including the same.

According to the present invention, a semiconductor package system includes a substrate; a first semiconductor package mounted on the upper surface of the substrate and including a first semiconductor chip, the first semiconductor chip including logic circuits; a first heat-conducting layer provided on the first semiconductor package; a second semiconductor package mounted on the upper surface of the substrate; a first passive element mounted on the top surface of the substrate; and a heat dissipation structure provided on the first heat-conducting layer, the second semiconductor package, and the first passive element. The heat dissipation structure includes: a first lower surface in physical contact with the first heat-conducting layer; and a second lower surface disposed at a higher level than the first lower surface, and the second lower surface may be provided on at least one of the second semiconductor package and the first passive element.

According to the present invention, a semiconductor package system includes a substrate; a first semiconductor package mounted on the substrate; a second semiconductor package mounted on the substrate; Passive elements mounted on the board; a heat dissipation structure provided on the first package, the second package, and the passive element; and a plurality of heat-conducting layers each physically contacting the heat-dissipating structure, wherein the heat-conducting layers include a first heat-conducting layer provided on the upper surface of the first semiconductor package, and the first heat-conducting layer is among the heat-conducting layers. It has the thinnest thickness, and a trench is provided on the first lower surface of the heat dissipation structure, and the trench may overlap at least one of the second semiconductor package and the first passive element in a plan view.

According to the present invention, a first heat-conducting layer may be provided on the first semiconductor package. The trench may overlap in plan view with at least one of the passive device and the second and third semiconductor packages. Accordingly, the first heat-conducting layer may have a smaller height than the second and third heat-conducting layers. As the height of the first heat-conducting layer decreases, the thermal characteristics of the first semiconductor package may improve. As the thermal properties of the first semiconductor package are improved, the thermal properties of the package system may be improved.

1A is a plan view showing a package system according to embodiments.
Figure 1B is a plan view showing a package system according to embodiments.
FIG. 1C is a cross-section taken along line I-II of FIG. 1A.
FIG. 1D is a cross-section taken along line III-III' of FIG. 1A.
FIG. 1E is an enlarged view of area A of FIG. 1C.
FIG. 1F is an enlarged view of area B of FIG. 1C.
FIG. 1G is a diagram for explaining a first semiconductor package according to an embodiment.
Figure 1h is a cross-section taken along line I'-II' of Figure 1f.
1I and 1J are diagrams illustrating a first semiconductor package according to embodiments.
FIG. K and FIG. 1L are diagrams each illustrating a second semiconductor package according to embodiments.
1M and 1N are diagrams illustrating a third semiconductor package according to embodiments.
Figure 2A is a plan view showing a package system according to embodiments.
Figure 2b is a cross-section taken along line I-II of Figure 2a.
Figure 2C is a plan view showing a package system according to embodiments.
FIG. 2D is a cross-section taken along line I-II of FIG. 2C.
Figure 2e is a cross-sectional view showing a package system according to embodiments.
3A to 3D are cross-sectional views showing package systems according to embodiments, respectively.
Figure 4 is a cross-sectional view showing a package system according to embodiments.
Figure 5A is a cross-sectional view showing a semiconductor module according to embodiments.
FIG. 5B is a diagram for explaining a second passive element according to embodiments, and is an enlarged cross-section of region C of FIG. 5A.
FIG. 5C is a diagram for explaining lower pads and conductive terminals according to embodiments.
FIG. 5D is a diagram for explaining lower pads according to embodiments.

In this specification, the same reference numerals may refer to the same elements throughout. Hereinafter, a package system according to the present invention and a semiconductor module including the same will be described. The semiconductor package system may be a package system or a semiconductor module including the package system.

1A is a plan view showing a package system according to embodiments. Figure 1B is a plan view showing a package system according to embodiments. FIG. 1C is a cross-section taken along line I-II of FIG. 1A. FIG. 1D is a cross-section taken along line III-III' of FIG. 1A. FIG. 1E is an enlarged view of area A of FIG. 1C. FIG. 1F is an enlarged view of area B of FIG. 1C.

1A, 1B, 1C, and 1D, the package system 1 includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, and a third semiconductor package 300. , may include a first passive element 400, a heat dissipation structure 600, and a first heat-conducting layer 710. As an example, a printed circuit board (PCB) with a circuit pattern may be used as the substrate 500. Conductive terminals 550 may be provided on the lower surface of the substrate 500. The conductive terminals 550 may include at least one of solder balls, bumps, and pillars. The conductive terminals 550 may include metal.

The first semiconductor package 100 may be mounted on the top surface 500a of the substrate 500. The first semiconductor package 100 may include a system-on-chip or logic chip, as will be described later. First connection terminals 150 may be interposed between the substrate 500 and the first semiconductor package 100 . The first semiconductor package 100 may be electrically connected to the substrate 500 through first connection terminals 150 . In this specification, being electrically connected to the substrate 500 means being electrically connected to the wires 505 within the substrate 500. The first connection terminals 150 may include solder balls, pillars, bumps, or ball grid arrays. The height H1 of the mounted first semiconductor package 100 may be defined to include the height of the first connection terminals 150.

The second semiconductor package 200 may be mounted on the top surface 500a of the substrate 500. The second semiconductor package 200 may be arranged to be spaced apart from the first semiconductor package 100 in a plan view. The second semiconductor package 200 may be a different type of semiconductor package from the first semiconductor package 100. Second connection terminals 250 may be interposed between the substrate 500 and the second semiconductor package 200 . The second semiconductor package 200 may be electrically connected to the substrate 500 through second connection terminals 250 . The second connection terminals 250 may include solder balls, pillars, bumps, or ball grid arrays. The height H2 of the mounted second semiconductor package 200 may include the height of the second connection terminals 250. The height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200. For example, the top surface 100a of the first semiconductor package 100 may be placed at a higher level than the top surface 200a of the second semiconductor package 200. A plurality of second semiconductor packages 200 may be provided.

The third semiconductor package 300 may be mounted on the top surface 500a of the substrate 500. The third semiconductor package 300 may be arranged to be spaced apart from the first semiconductor package 100 and each second semiconductor package 200 in a plan view. The third semiconductor package 300 may be a different type of semiconductor package from the first and second semiconductor packages 100 and 200. The third semiconductor package 300 may be provided as a single piece as shown in FIG. 1A. As another example, a plurality of third semiconductor packages 300 may be provided as shown in FIG. 1B. In this case, the third semiconductor packages 300 may be spaced apart from each other. The number and planar arrangement of the third semiconductor packages 300 may vary. Third connection terminals 350 may be interposed between the substrate 500 and each third semiconductor package 300, as shown in FIG. 1C. The third semiconductor package 300 may be electrically connected to the substrate 500 through third connection terminals 350. The third connection terminals 350 may include solder balls, pillars, bumps, or ball grid arrays. The height H3 of the mounted third semiconductor package 300 may include the height of the third connection terminals 350. The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the third semiconductor package 300 mounted. For example, the top surface 100a of the first semiconductor package 100 may be placed at a higher level than the top surface 300a of the third semiconductor package 300.

The first semiconductor package 100 may be electrically connected to the second and third semiconductor packages 200 and 300 and the conductive terminals 550 through the wiring 505 of the substrate 500. The second semiconductor package 200 may be electrically connected to the first and third semiconductor packages 100 and 300 and the conductive terminals 550 through the substrate 500. The third semiconductor package 300 may be electrically connected to the first and second semiconductor packages 100 and 200 and the conductive terminals 550 through the substrate 500.

The first passive element 400 may be mounted on the top surface 500a of the substrate 500. The first passive element 400 may be arranged to be spaced apart from the first to third semiconductor packages 100, 200, and 300 in a plan view. The first passive element 400 may include any one of an inductor, a resistor, and a capacitor. As shown in Figure 1d, first connection terminal parts 410 may be further provided between the substrate 500 and the first passive element 400. In this case, the height H4 of the mounted first passive element 410 is It may be defined as including the height of the first connection terminal parts 410. For example, the height H4 of the mounted first passive element 410 is the height H41 of the first connection terminal parts 410. ) and the height H40 of the first passive element 400' before mounting. The first connection terminal portions may include solder, pillars, or bumps. Drawings excluding FIG. 1D In the illustration, the first connection terminal portions 401 are omitted for simplicity, but the present invention is not limited thereto.

A heat dissipation structure 600 may be provided on the first to third semiconductor packages 100, 200, and 300 and the first passive element 400. The heat dissipation structure 600 may be spaced apart from the substrate 500 . The heat dissipation structure 600 may have an upper surface 600a and a first lower surface 601b that face each other. The first lower surface 601b of the heat dissipation structure 600 may be parallel to the upper surface 500a of the substrate 500. The first lower surface 601b of the heat dissipation structure 600 may be provided on the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300. The heat dissipation structure 600 may include a thermally conductive material. The thermally conductive material may include a metal (e.g., copper and/or aluminum, etc.) or a carbon-containing material (e.g., graphene, graphite, and/or carbon nanotubes, etc.). The heat dissipation structure 600 may have relatively high thermal conductivity. As an example, a single metal layer or a plurality of stacked metal layers may be used as the heat dissipation structure 600. As another example, the heat dissipation structure 600 may include a heat sink or heat pipe. As another example, the heat dissipation structure 600 may use a water cooling method.

The first heat-conducting layer 710 may be interposed between the first semiconductor package 100 and the heat dissipation structure 600. The first heat-conducting layer 710 may physically contact the upper surface 100a of the first semiconductor package 100 and the first lower surface 601b of the heat dissipation structure 600. The first heat-conducting layer 710 may include a thermal interface material (TIM). Thermal interface materials may include polymers and thermally conductive particles, for example. The thermally conductive particles may be dispersed within the polymer. When the first semiconductor package 100 is operated, heat generated in the first semiconductor package 100 may be emitted to the outside through the first heat-conducting layer 710 and the heat dissipation structure 600.

A second heat-conducting layer 720 may be provided between the second semiconductor package 200 and the heat dissipation structure 600. The second heat-conducting layer 720 may be in physical contact with the upper surface 200a of the second semiconductor package 200 and the first lower surface 601b of the heat dissipation structure 600. The second heat-conducting layer 720 may include, for example, a thermal interface material (TIM). When the second semiconductor package 200 operates, heat generated in the second semiconductor package 200 may be transferred to the heat dissipation structure 600 through the second heat-conducting layer 720.

A third heat-conducting layer 730 may be provided between the third semiconductor package 300 and the heat dissipation structure 600. The third heat-conducting layer 730 may be in physical contact with the upper surface 300a of the third semiconductor package 300 and the first lower surface 601b of the heat dissipation structure 600. The third heat-conducting layer 730 may include, for example, a thermal interface material (TIM). When the third semiconductor package 300 is operated, heat generated in the third semiconductor package 300 may be transferred to the heat dissipation structure 600 through the third heat-conducting layer 730.

When the package system 1 operates, a lot of heat may be generated in the first semiconductor package 100. For example, the first semiconductor package 100 may generate more heat than the second semiconductor package 200, the third semiconductor package 300, and the first passive element 400. The thermal characteristics of the first semiconductor package 100 may have a greater impact on the operating performance of the package system 1 than the thermal characteristics of the second and third semiconductor packages 200 and 300. As the thermal characteristics of the first semiconductor package 100 improve, the operating characteristics of the package system 1 may improve. The first to third heat conductive layers 710, 720, and 730 may have a lower thermal conductivity than the heat dissipation structure 600. As the height A1 of the first heat-conducting layer 710 decreases, heat generated in the first semiconductor package 100 can be dissipated more quickly to the heat dissipation structure 600. According to embodiments, the height A1 of the first heat-conducting layer 710 may be the smallest among the heights of heat-conducting layers in contact with the lower surface of the heat dissipation structure 600 (for example, the first lower surface 601b). there is. At this time, the heat-conducting layers may include first to third heat-conducting layers 710, 720, and 730. As another example, the heat-conducting layer may further include adhesive patterns 741 and 742, which will be described later in FIGS. 2A and 2B. For example, the height A1 of the first heat-conducting layer 710 may be smaller than the height A2 of the second heat-conducting layer 720 and the height A3 of the third heat-conducting layer 730. Accordingly, heat generated in the first semiconductor package 100 can be transferred to the heat dissipation structure 600 more quickly. Packaged system 1 may exhibit improved operating characteristics.

The heat dissipation structure 600 may have a trench. The trench may extend from the first lower surface 601b of the heat dissipation structure 600 toward the upper surface 600a. The trench may overlap at least one of the first passive element 400, the second semiconductor package 200, and the third semiconductor package 300 from a plan view. According to embodiments, the trench may be a first trench 691 provided on the first lower surface 601b of the heat dissipation structure 600. A first trench 691 is provided so that the heat dissipation structure 600 can have a second lower surface 602b. The second lower surface 602b of the heat dissipation structure 600 may correspond to the bottom surface of the first trench 691. The second lower surface 602b may be placed at a higher level than the first lower surface 601b and may be placed at a lower level than the upper surface 600a. The second lower surface 602b of the heat dissipation structure 600 is provided on the first passive element 400 and may overlap the second passive element 400 in a plan view. The second lower surface 602b of the heat dissipation structure 600 may face the upper surface of the first passive element 400. The top surface of the first passive element 400 may be provided at the same or lower level than the second bottom surface 602b.

According to embodiments, the height H4 of the mounted first passive element 400 is the sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat-conducting layer 710. It may be equal to or greater than . The top surface of the first passive element 400 may be disposed at the same or higher level than the top surface of the first heat-conducting layer 710. When the heat dissipation structure 600 does not have the first trench 691, the upper surface 500a of the substrate 500 and the first lower surface 601b of the heat dissipation structure 600 due to the mounting of the first passive element 400. The distance between them can be increased. In this case, the height A1 of the first heat-conducting layer 710, the height A2 of the second heat-conducting layer 720, and the height A3 of the third heat-conducting layer 730 may be increased. According to embodiments, as shown in FIG. 1A, the first trench 691 may overlap the first passive element 400 from a plan view. Even if the first passive element 400 is mounted on the top surface 500a of the substrate 500, the first heat-conducting layer 710 may have a small height A1. Accordingly, the thermal characteristics of the first semiconductor package 100 may be improved. Likewise, thermal characteristics of the second and third semiconductor packages 200 and 300 may be improved. The level of the second lower surface 602b of the heat dissipation structure 600 may be adjusted according to the height H4 of the mounted first passive element 400.

The first passive element 400 may be provided in plural numbers. The first passive elements 400 may be spaced apart from each other. 1A and 1D, the first trench 691 may overlap a plurality of first passive elements 400. The first passive elements 400 may include a first sub-passive element 401, a second sub-passive element 402, and a third sub-passive element 403. Height (H4) of the mounted first sub-passive element 401, height (H4') of the mounted second sub-passive element (402), height (H4'') of the mounted and third sub-passive elements (403). ) may be different. For example, the height (H4) of the mounted first sub-passive element 401 is the height (H4') of the mounted second sub-passive element 402, and the height (H4') of the mounted third sub-passive element 403 ( H4''). The height H4 of the mounted first sub-passive element 401 is equal to or greater than the sum of the height H1 of the first semiconductor package 100 and the height A1 of the first heat-conducting layer 710 described above. You can. The first trench 691 may overlap the first to third sub-passive elements 401, 402, and 403 in a plan view. The level of the second lower surface 602b of the heat dissipation structure 600 is the highest among the heights H4, H4', and H4'' of the first to third sub-passive elements 401, 402, and 403 mounted. can be determined by For example, the second lower surface 602b of the heat dissipation structure 600 may be disposed at the same level as or higher than the upper surface of the first sub-passive element 401. As shown in FIG. 1B, a plurality of first trenches 691 may be provided. The first trenches 691 may overlap the second semiconductor packages 200, respectively. Hereinafter, the single first passive element 400 and the first trench 691 will be described.

Electronic devices 430 may be further provided on the top surface 500a of the substrate 500. The electronic device 430 may include an oscillator such as a crystal oscillator or a real-time clock. As shown in FIG. 1E, a conductive connection terminal 413 is further provided between the electronic device 430 and the upper surface 500a of the substrate 500, so that it can be electrically connected to the electronic device 430 and the substrate 500. In this case, the height H7 of the mounted electronic device 430 may be defined as including the height H71 of the conductive connection terminal 413. For example, the height H7 of the mounted electronic device 430 may be equal to the sum of the height H71 of the conductive connection terminal 413 and the height H70 of the electronic device 430' before mounting. there is. The sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat-conducting layer 710 may be greater than the height of the mounted electronic device 430. The top surface of the electronic device 430 may be provided at the same or lower level than the top surface of the first heat-conducting layer 710. Even if the electronic device 430 is provided on the upper surface 500a of the substrate 500, heat generated in the first semiconductor package 100 may be emitted to the heat dissipation structure 600 through the first heat-conducting layer 710. there is. As another example, the electronic device 430 may not be provided on the top surface 500a of the substrate 500. In the drawings except FIG. 1E, the conductive connection terminal 403 is omitted for simplicity, but the present invention is not limited thereto.

The first underfill film 160 may be provided in the gap between the substrate 500 and the first semiconductor package 100 to seal the first connection terminals 150. The second underfill film 260 may be provided in the gap between the substrate 500 and the second semiconductor package 200 to seal the second connection terminals 250. A third underfill film 360 may be provided in the gap between the substrate 500 and the second semiconductor package 200 to seal the third connection terminals 350. The first to third underfill layers 160, 260, and 360 may include an insulating polymer such as an epoxy-based polymer. As the first to third underfill films 160, 260, and 360 are provided, the joint reliability of the first to third connection terminals 150, 250, and 350 can be improved. Unlike shown, at least one of the first to third underfill layers 160, 260, and 360 may be omitted.

A dam structure 590 may be further provided on the upper surface 500a of the substrate 500. The dam structure 590 may be disposed between the third semiconductor package 300 and the first passive element 400. A dam structure 590 is provided, so that even if the underfill material of the third underfill film 360 flows, it may not interfere with the mounting of the first passive element 400. The dam structure 590 may include liquid resin. Although not shown, the substrate 500 may include a plurality of layers, and the top layer of the layers may include an insulating polymer such as a solder resist material. As an example, the dam structure 590 may be formed integrally with the uppermost layer of the substrate 500. In this case, the dam structure 590 may be connected to the uppermost layer of the substrate 500 without an interface. As another example, the dam structure 590 may include a material different from that of the substrate 500. For example, the dam structure 590 may be formed of the same material as any one of the first to third underfill films 160, 260, and 360. The height of the dam structure 590 may be equal to or smaller than the sum of the height H1 of the first semiconductor package 100 and the height A1 of the first heat-conducting layer 710.

The arrangement and number of dam structures 590 may be modified. For example, a plurality of dam structures 590 may be provided. As another example, the dam structure 590 may be disposed between the first semiconductor package 100 and the first passive element 400. As another example, the dam structure 590 may be disposed between the second semiconductor package 200 and the first passive element 400.

FIG. 1G is a diagram for explaining a first semiconductor package according to an embodiment, and corresponds to an enlarged view of area IV of FIG. 1A. FIG. 1H is a cross-sectional view taken along line I'-II' of FIG. 1G and an enlarged view of area V of FIG. 1C.

1C, 1G, and 1H, the first semiconductor package 100 may include a first package substrate 110, a first semiconductor chip 120, and a first molding film 130. For example, a printed circuit board (PCB) or a redistribution layer may be used as the first package substrate 110 . The first semiconductor chip 120 may be flip-chip mounted on the first package substrate 110. Interposers may be provided between the first semiconductor chip 120 and the first package substrate 110. Interposers may include solder balls, pillars, bumps, or ball grid arrays. Interposers may include conductive materials such as metals. The first semiconductor chip 120 may be a system-on-chip (SOC), logic chip, or application processor (AP) chip. The first semiconductor chip 120 may include circuits that perform different functions. For example, the first semiconductor chip 120 may include a logic circuit and a memory circuit. The first semiconductor chip 120 may further include at least one of a digital integrated circuit (IC), a wireless radio frequency integrated circuit (RFIC), and an input/output circuit. When the first semiconductor package 100 operates, heat being generated from the first semiconductor package 100 may mean that heat is generated from the first semiconductor chip 120.

The first molding film 130 may be disposed on the first package substrate 110 to seal the first semiconductor chip 120. The first molding film 130 may cover the side and top surfaces of the first semiconductor chip 120. In this case, the top surface 100a of the first semiconductor package 100 may correspond to the top surface of the first molding film 130. The first molding film 130 may include an insulating polymer such as an epoxy-based molding compound. The first molding film 130 may further extend into the gap between the first package substrate 110 and the first semiconductor chip 120. Unlike shown, a separate underfill pattern may be provided in the gap between the first package substrate 110 and the first semiconductor chip 120. The underfill pattern may be formed by thermal compression of a non-conductive paste or a non-conductive film, or a capillary underfill process. The height H1 of the mounted first semiconductor package 100 is equal to the sum of the height of the first connection terminals 150, the height of the first package substrate 110, and the height of the first molding film 130. can do.

A first marker 190 may be provided on the first molding film 130. For example, the first marker 190 may be provided on the top surface of the first molding film 130. Alternatively, the first marker 190 may be provided on the side of the first molding film 130. The first marker 190 may be a recessed portion on the first molding film 130. Formation of the first marker 190 may include removing a portion of the first molding film 130. When the first marker 190 is formed on the first semiconductor chip 120, the first semiconductor chip 120 may be damaged during the formation of the first marker 190. For example, cracks may form on or in the first semiconductor chip 120. According to embodiments, as the first marker 190 is provided on the first molding film 130, damage to the first semiconductor chip 120 can be prevented during the formation of the first marker 190. . The first marker 190 may display information about the first semiconductor package 100. In drawings other than FIGS. 1G to 1H, the first marker 190 is omitted for convenience, but the present invention is not limited thereto.

The first heat-conducting layer 710 may be provided on the top surface 100a of the first semiconductor package 100. Forming the first heat-conducting layer 710 may include providing a thermal interface material on the first semiconductor package 100 and curing the thermal interface material. The thermal interface material prior to curing may have fluidity. In the process of forming the first heat-conducting layer 710, even if the thermal interface material on the edge region of the top surface 100a of the first semiconductor package 100 flows down to the side surface 100c of the first semiconductor package 100, the first heat-conducting layer 710 is formed. 1 The thermal interface material on the center area of the upper surface 100a of the semiconductor package 100 may not flow. The first heat-conducting layer 710 can satisfactorily fill the gap between the heat dissipation structure 600 and the center region of the upper surface 100a of the first semiconductor package 100. For example, the top surface 710a of the first heat-conducting layer 710 in the center area of the first semiconductor package 100 may be in physical contact with the heat dissipation structure 600. Since the first molding film 130 is provided, the center area of the first semiconductor package 100 may correspond to the area where the first semiconductor chip 120 is provided. Even if some of the thermal interface material flows during the formation of the first heat-conducting layer 710, the first heat-conducting layer 710 can well transfer the heat generated in the first semiconductor chip 120. When the first marker 190 is provided on the first molding film 130, the first heat-conducting layer 710 may extend into the first marker 190.

FIG. 1I is a diagram illustrating a first semiconductor package according to embodiments, and corresponds to an enlarged cross-section of area V in FIG. 1C and a cross-section taken along line I-II in FIG. 1E.

1C, 1G, and 1I, the first semiconductor package 100 includes a first package substrate 110, a first semiconductor chip 120, and a first molding film 130, and a first It may include a heat-conducting layer 710 and a first heat-conducting structure 140.

The first heat-conducting structure 140 includes the heat-conductive material described in the examples of FIGS. 1A to 1C and may have relatively high heat conductivity. The first heat-conducting structure 140 may include a metal layer, a heat sink, or a heat pipe. A first adhesive layer 141 may be provided between the first molding film 130 and the first heat-conducting structure 140. The first adhesive layer 141 may attach the first heat-conducting structure 140 to the first molding film 130. The first adhesive layer 141 may include a thermal interface material. When the first semiconductor package 100 is operated, heat generated from the first semiconductor chip 120 passes through the first adhesive layer 141, the first heat conduction structure 140, and the first heat conduction layer 710 to the heat dissipation structure ( 600).

According to embodiments, the top surface 100a of the first semiconductor package 100 may correspond to the top surface of the first heat-conducting structure 140. The height H1 of the mounted first semiconductor package 100 is the height of the first connection terminals 150, the height of the first package substrate 110, the height of the first molding film 130, and the first adhesive layer ( It may be equal to the sum of the height of 141) and the height of the first heat-conducting structure 140. For example, even if the top surface of the first molding film 130 is disposed at a lower level than the top surface 200a of the second semiconductor package 200 and the top surface 300a of the third semiconductor package 300, the first adhesive layer ( 141) and the provision of the first heat conduction structure 140, the height H1 of the mounted first semiconductor package 100 is equal to the height H2 of the second semiconductor package 200 and the third semiconductor package 140. It may be larger than the height (H3) of the package 300. Accordingly, the height A1 of the first heat-conducting layer 710 may be smaller than the height A2 of the second heat-conducting layer 720 and the height A3 of the third heat-conducting layer 730. The thermal characteristics of the first semiconductor package 100 may be improved.

FIG. 1J is a diagram for explaining a first semiconductor package according to an embodiment, and is an enlarged view of a cross-section taken along line I'-II' of FIG. 1G and area V of FIG. 1C.

1C, 1G, and 1J, the first semiconductor package 100 includes, in addition to the first package substrate 110, the first semiconductor chip 120, and the first molding film 130, a first semiconductor package 100. It may include a heat-conducting layer 710 and a first heat-conducting structure 140. The first molding film 130 may cover the side surfaces of the first semiconductor chip 120 and expose the top surface. In this case, the top surface 100a of the first semiconductor package 100 corresponds to the top surface of the first molding film 130 and the top surface of the first semiconductor chip 120 exposed by the first molding film 130. You can. The exposed upper surface of the first semiconductor chip 100 may be in direct physical contact with the first adhesive layer 141. Accordingly, the heat dissipation characteristics of the first semiconductor chip 100 can be further improved.

FIG. 1K is a diagram illustrating a second semiconductor package according to embodiments, and is an enlarged cross-section of area V' of FIG. 1C.

Referring to FIGS. 1C and 1K , the second semiconductor package 200 may include a second package substrate 210, a second semiconductor chip 220, and a second molding film 230. A printed circuit board (PCB) or a redistribution layer may be used as the second package board 210. The second semiconductor chip 220 may be mounted using a flip chip method or a wire bonding method. The second semiconductor chip 220 may be a different type of semiconductor chip than the first semiconductor chip 120. For example, the second semiconductor chip 220 may function as a memory chip. Memory chips may include DRAM chips. As another example, the memory chip may include SRAM, MRAM, and/or NAND flash memory. When the second semiconductor package 200 operates, heat being generated from the second semiconductor package 200 may mean that heat is generated from the second semiconductor chip 220. The second semiconductor package 200 may include a plurality of second semiconductor chips 220. As another example, the second semiconductor package 200 may include a single second semiconductor chip 220. Hereinafter, for simplicity of explanation, a single second semiconductor chip 220 will be described.

A second molding film 230 may be provided on the second semiconductor chip 220 to cover the second semiconductor chip 220. The second molding film 230 may include an insulating polymer such as an epoxy-based polymer. When the second semiconductor chip 220 is flip-chip mounted, the second molding film 230 may further extend into the gap between the second semiconductor chip 220 and the second package substrate 210. Alternatively, an underfill pattern (not shown) may be further provided to fill the gap between the first package substrate 110 and the first semiconductor chip 120. The second molding film 230 may cover the sidewall of the second semiconductor chip 220 and expose the top surface. In this case, the top surface 200a of the second semiconductor package 200 may correspond to the top surface of the second molding film 230. As another example, the second molding film 230 may cover the side surfaces of the second semiconductor chip 220 and expose the top surface. In this case, the top surface 200a of the second semiconductor package 200 corresponds to the top surface of the second molding film 230 and the top surface of the second semiconductor chip 220 exposed by the second molding film 230. You can. The height H2 of the mounted second semiconductor package 200 is defined as the sum of the height of the second connection terminals 250, the height of the second package substrate 210, and the height of the second molding film 230. It can be.

A second marker 290 may be further provided on the second molding film 230 . The second marker 290 may be a recessed portion of the second molding film 230. The second marker 290 may display information about the second semiconductor package 200.

The second heat-conducting layer 720 may be formed on the upper surface of the second molding film 230. The second heat-conducting layer 720 may be formed by the same method as the previous example of forming the first heat-conducting layer 710. Even if some of the thermal interface material flows during the formation of the second heat-conducting layer 720, the second heat-conducting layer 720 is between the center region of the upper surface 200a of the second semiconductor package 200 and the heat dissipation structure 600. The gap can be filled satisfactorily. The center area of the upper surface 200a of the second semiconductor package 200 may correspond to an area where the second semiconductor chip 220 is provided. Accordingly, the second heat-conducting layer 720 can effectively receive heat generated from the second semiconductor chip 220. The second heat-conducting layer 720 may extend further into the second marker 290.

FIG. 1L is a diagram illustrating a second semiconductor package according to embodiments, and is an enlarged cross-section of area V' of FIG. 1C.

1C and 1L, the second semiconductor package 200 includes a second package substrate 210, a second semiconductor chip 220, and a second molding film 230, as well as a second adhesive layer 241. And it may include a second heat conduction structure 240. The second heat-conducting structure 240 may include a heat-conductive material and have relatively high heat conductivity. The second heat-conducting structure 240 may include a metal layer, a heat sink, or a heat pipe. A second adhesive layer 241 may be provided between the second molding film 230 and the second heat-conducting structure 240. The second adhesive layer 241 may include a thermal interface material. When the second semiconductor package 200 is operated, heat generated from the second semiconductor chip 220 may be transferred to the second heat-conducting layer 720 through the second adhesive layer 241 and the second heat-conducting structure 240. there is.

The top surface 200a of the second semiconductor package 200 may correspond to the top surface of the second heat-conducting structure 240. The height H2 of the mounted second semiconductor package 200 is the height of the second connection terminals 250, the height of the second package substrate 210, the height of the second molding film 230, and the second adhesive layer ( 241) and the height of the second heat-conducting structure 240 may be equal to the sum of the height.

FIG. 1M is a diagram illustrating a third semiconductor package according to embodiments, and corresponds to an enlarged view of area V'' of FIG. 1C.

Referring to FIGS. 1C and 1M , the third semiconductor package 300 may include a third package substrate 310, a third semiconductor chip 320, and a third molding film 330. A redistribution layer or a printed circuit board may be used as the third package substrate 310. The third semiconductor chip 320 may be a different type of semiconductor chip from the first semiconductor chip 120 and the second semiconductor chip 220. For example, the third semiconductor chip 320 may include a power management integrated circuit (PMIC) and function as a power management chip. When the third semiconductor package 300 operates, heat being generated from the third semiconductor package 300 may mean that heat is generated from the third semiconductor chip 320. A third molding film 330 may be provided on the third semiconductor chip 320 to cover the third semiconductor chip 320. The third molding film 330 may cover the top and side surfaces of the third semiconductor chip 320. The top surface 300a of the third semiconductor package 300 may correspond to the top surface of the third molding film 330. As another example, the third molding film 330 may cover the side surfaces of the third semiconductor chip 320 and expose the top surface. The top surface 300a of the third semiconductor package 300 may correspond to the top surface of the third molding film 330 and the top surface of the third semiconductor chip 320 exposed by the third molding film 330. The third molding film 330 may include an insulating polymer such as an epoxy polymer. The height H3 of the mounted third semiconductor package 300 is defined as the sum of the height of the third connection terminals 350, the height of the third package substrate 310, and the height of the third molding film 330. It can be.

The third semiconductor package 300 may be manufactured as a fan-out panel level package or a fan-out wafer level package. Formation of the third semiconductor package 300 includes providing a third semiconductor chip 320 on a carrier substrate (not shown) and forming a third molding film 330 covering the third semiconductor chip 320. , exposing the lower surface of the third semiconductor chip 320 by removing the carrier substrate, and forming a redistribution layer on the exposed lower surface of the third semiconductor chip 320 and the lower surface of the third molding film 330. It may include forming. The redistribution layer may be used as the third package substrate 310.

FIG. 1N is a diagram illustrating a third semiconductor package according to embodiments, and corresponds to an enlarged view of area V'' of FIG. 1C.

1C and 1N, the third semiconductor package 300 includes a third package substrate 310, a third semiconductor chip 320, and a third molding film 330, as well as a third heat-conducting layer 730. ) and a third heat conduction structure 340. The third heat-conducting structure 340 includes a heat-conductive material and may have relatively high heat conductivity. The third heat-conducting structure 340 may include a metal layer, a heat sink, or a heat pipe. A third adhesive layer 341 may be provided between the third molding film 330 and the second heat-conducting structure 240. The third adhesive layer 341 may include a thermal interface material. When the third semiconductor package 300 operates, heat generated from the third semiconductor chip 320 may be transferred to the third heat-conducting layer 730 through the third adhesive layer 341 and the third heat-conducting structure 340. there is.

The top surface 300a of the third semiconductor package 300 may correspond to the top surface of the third heat-conducting structure 340. The height H3 of the mounted third semiconductor package 300 is the height of the third connection terminals 350, the height of the third package substrate 310, the height of the third molding film 330, and the third adhesive layer ( 141) and the height of the third heat-conducting structure 340 may be equal to the sum of the height.

A third marker 390 may be further provided on the third molding film 330 . The third marker 390 may be a recessed portion of the third molding film 330.

Referring to FIGS. 1C, 1JM, and 1N, a third heat-conducting layer 730 may be formed on the top surface 300a of the third semiconductor package 300. The third heat-conducting layer 730 may be formed by the same method as the previous example of forming the first heat-conducting layer 710. At this time, even if some of the thermal interface material on the edge area of the upper surface 300a of the third semiconductor package 300 flows down, the third heat-conducting layer 730 is located at the center of the upper surface 300a of the third semiconductor package 300. The gap between the region and the heat dissipation structure 600 can be satisfactorily filled. The center area of the upper surface 300a of the third semiconductor package 300 may correspond to an area where the third semiconductor chip 320 is provided. Accordingly, the third heat-conducting layer 730 can well transfer heat generated in the third semiconductor package 300.

Figure 2A is a plan view showing a package system according to embodiments. Figure 2b is a cross-section taken along line I-II of Figure 2a.

Referring to FIGS. 2A and 2B, the package system 1a includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. Substrate 500, first to third semiconductor packages (100, 200, 300), first passive element 400, first to third heat conductive layers (710, 720, 730), and heat dissipation structure (600) ) may be the same as the previous description of FIGS. 1A to 1N.

A ground pad 510G may be provided on the top surface 500a of the substrate 500. At least one of the conductive terminals 550 may function as a ground terminal. A ground voltage may be applied to the ground pad 510G through the ground terminal and the substrate 500.

The heat dissipation structure 600 may include a body portion 601 and a leg portion 602. The body portion 601 of the heat dissipation structure 600 may be similar to the heat dissipation structure 600 previously described in FIGS. 1A to 1C. For example, the body portion 601 may be provided on the first to third semiconductor packages 300, 300, 300 and the first passive element 400. A trench may be formed on the first lower surface 601b of the body portion 601. The trench may be the first trench 691 described in FIGS. 1A to 1C. A first lower surface 601b and a second lower surface 602b of the heat dissipation structure 600 may be provided on the body portion 601. The first heat-conducting layer 710 may be in physical contact with the second lower surface 602b of the heat dissipation structure 600.

The leg portion 602 of the heat dissipation structure 600 may be provided between the edge area of the body portion 601 and the substrate 500. The leg portion 602 of the heat dissipation structure 600 may be connected to the body portion 601. As shown in FIG. 2A , the first to third semiconductor packages 300 , 300 , 300 and the first passive element 400 may be spaced apart from the leg portion 602 of the heat dissipation structure 600 . The leg portion 602 may be provided in an edge area of the substrate 500 from a plan view.

Adhesion patterns 741 and 742 are provided between the substrate 500 and the leg portion 602 of the heat dissipation structure 600 to fix the heat dissipation structure 600 to the substrate 500. The adhesive patterns 741 and 742 may include a conductive adhesive pattern 741 and an insulating adhesive pattern 742. The conductive adhesive pattern 741 may be provided between the ground pad 510G and the lower surface of the leg portion 602 of the heat dissipation structure 600. The heat dissipation structure 600 may be connected to the ground pad 510G through a conductive adhesive pattern 741.

If a certain amount of charge or more is accumulated in the heat dissipation structure 600, the charge may flow from the heat dissipation structure 600 to other electrically conductive components and damage the electrically conductive components. The electrically conductive components include integrated circuits and wiring in the first to third semiconductor chips 310, 320, and 330, wiring in the first to third package substrates 310, 320, and 330, and first to third semiconductor chips 310, 320, and 330. It may include at least one of the third connection terminals 150, 250, and 350, and wiring within the substrate 500. According to embodiments, a ground voltage may be applied to the heat dissipation structure 600 by the conductive adhesive pattern 741. Accordingly, the heat dissipation structure 600 can prevent electrical damage to the package system 1a due to electrostatic discharge (ESD).

The heat dissipation structure 600 has electrical conductivity and can shield electromagnetic interference (EMI) of the first to third semiconductor packages 100, 200, and 300. Electromagnetic interference means that electromagnetic waves radiated or conducted from an electrical element cause interference in the reception/transmission function of other electrical elements. By the heat dissipation structure 600, the operations of the first to third semiconductor packages 100, 200, and 300 and the operation of the first passive element 400 interfere with the operations of other packages or are interrupted by other packages. You may not receive it.

An insulating adhesive pattern 742 may be provided between the substrate 500 and the heat dissipation structure 600. Accordingly, the heat dissipation structure 600 is insulated from 500 and the occurrence of an electrical short can be prevented. The height of the insulating adhesive pattern 742 may be the same as the height A5 of the conductive adhesive pattern 741.

Referring to FIG. 2B, the height B of the leg portion 602 of the heat dissipation structure 600 may be equal to the maximum vertical spacing of the inner surface of the heat dissipation structure 600. The height B of the leg portion 602 of the heat dissipation structure 600 may be smaller than the height H1 of the mounted first semiconductor package 100. Accordingly, the height A1 of the first heat-conducting layer 710 may be smaller than the heights of the adhesive patterns 741 and 742 (eg, the thickness A5 of the conductive adhesive pattern 741). Since the first heat-conducting layer 710 has a small height H1, heat generated in the first semiconductor package 100 can be more quickly transferred to the heat dissipation structure 600 through the first heat-conducting layer 710.

Figure 2C is a plan view showing a package system according to embodiments. FIG. 2D is a cross-section taken along line I-II of FIG. 2C.

Referring to FIGS. 2C and 2D, the package system 1b includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The heat dissipation structure 600 may be the same as the description in FIGS. 2A and 2B. For example, the heat dissipation structure 600 may include a body portion 601 and a leg portion 602.

A conductive adhesive pattern 741 may be provided between the ground pad 510G and the leg portion 602 of the heat dissipation structure 600 to be electrically connected to the heat dissipation structure 600 and the ground pad 510G. The height A1 of the first heat-conducting layer 710 may be smaller than the height A5 of the conductive adhesive pattern 741. Unlike the examples of FIGS. 2A and 2B, a separate insulating adhesive pattern 742 may not be provided.

FIG. 2E is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II in FIG. 2C.

Referring to FIGS. 2C and 2E, the package system 1c includes a substrate 500, first to third semiconductor chips 310, 320, and 330, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600.

The heat dissipation structure 600 may include a first heat dissipation structure 610, a second heat dissipation structure 620, and a heat dissipation adhesive layer 630. The first heat dissipation structure 610 may be the same as the example of FIGS. 2A and 2B or the example of FIGS. 2C and 2D. For example, the second heat dissipation structure 620 may include a body portion 601 and a leg portion 602. A first trench 691 may be provided on the first lower surface 601b of the first heat dissipation structure 610. A conductive adhesive pattern 741 may be provided between the ground pad 510G and the first heat dissipation structure 610. As another example, an insulating adhesive pattern 742 as described in the examples of FIGS. 2A and 2B may be further provided.

The second heat dissipation structure 620 may be provided on the first heat dissipation structure 610. The second heat dissipation structure 620 may be the same as the heat dissipation structure 600 previously described with reference to FIGS. 1A to 1C. However, the second heat dissipation structure 620 may not have a trench. The lower surface of the second heat dissipation structure 620 may be flat.

A heat dissipation adhesive layer 630 may be interposed between the first heat dissipation structure 610 and the second heat dissipation structure 620. The second heat dissipation structure 620 may be attached to the first heat dissipation structure 610 by a heat dissipation adhesive layer 630. The heat dissipation adhesive layer 630 may include, for example, a thermal interface material.

FIG. 3A is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II in FIG. 2C.

Referring to FIGS. 2C and 3A, the package system 1d includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600. The width of the first heat dissipation structure 610 may be the same as or wider than the width of the second heat dissipation structure 620.

The height H2 of the mounted second semiconductor package 200 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. For example, the top surface 200a of the second semiconductor package 200 may be disposed at the same or higher level than the top surface 100a of the first semiconductor package 100.

A second trench 692 may be provided on the first lower surface 601b of the heat dissipation structure 600. The heat dissipation structure 600 may have a third lower surface 603b disposed at a higher level than the first lower surface 601b. The third lower surface 603b may correspond to the bottom surface of the second trench 692. The third lower surface 603b of the heat dissipation structure 600 may be provided on the second semiconductor package 200 . The second trench 692 may overlap the second semiconductor package 200 from a plan view. The second heat-conducting layer 720 is provided on the upper surface 200a of the second semiconductor package 200 and may be in physical contact with the third lower surface 603b of the second trench 692. At least a portion of the side surface of the second heat-conducting layer 720 may face the sidewall of the second trench 692. According to embodiments, even if the height H2 of the second semiconductor package 200 is large, the height A1 of the first heat-conducting layer 710 increases as the second trench 692 is provided. 720) may be smaller than the height (A2). Accordingly, the thermal characteristics of the package system 1d can be improved.

When a plurality of second semiconductor packages 200 are provided, a plurality of second trenches 692 may be provided. The second trenches 692 may overlap the second semiconductor packages 200, respectively. As another example, the second trenches 692 may overlap at least two or more second semiconductor packages 200 .

The sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat-conducting layer 710 may be greater than the height H4 of the first passive element 400. For example, the top surface of the first heat-conducting layer 710 may be disposed at a higher level than the top surface of the first passive element 400. The first trench 691 may not be provided. The upper surface of the first passive element 400 may face the first lower surface 601b of the heat dissipation structure 600.

FIG. 3B is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II in FIG. 2C.

Referring to FIGS. 2C and 3B, the package system 1e includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. It may include layers 710, 720, and 730, and a heat dissipation structure 600.

The height H3 of the mounted third semiconductor package 300 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. For example, the top surface 300a of the third semiconductor package 300 may be disposed at the same or higher level than the top surface 100a of the first semiconductor package 100.

A third trench 693 may be provided on the first lower surface 601b of the heat dissipation structure 600. The heat dissipation structure 600 may have a fourth lower surface 604b disposed at a higher level than the first lower surface 601b. The fourth lower surface 604b may correspond to the bottom surface of the third trench 693. The fourth lower surface 604b of the heat dissipation structure 600 may be provided on the third semiconductor package 300. The third trench 693 may overlap the third semiconductor package 300 from a plan view. The third heat-conducting layer 730 is provided on the upper surface 300a of the third semiconductor package 300 and may be in physical contact with the fourth lower surface 604b of the third trench 693. At least a portion of the side surface of the third heat-conducting layer 730 may face the sidewall of the third trench 693. According to embodiments, even if the height H3 of the third semiconductor package 300 is large, as the third trench 693 is provided, the height A1 of the first heat-conducting layer 710 is greater than the third heat-conducting layer 710. It may be smaller than the height (A3) of (730). Accordingly, the thermal characteristics of the package system 1e can be improved.

The height H1 of the first semiconductor package 100 may be greater than the height H2 of the second semiconductor package 200. The height A1 of the first heat-conducting layer 710 may be smaller than the height A2 of the second heat-conducting layer 720.

The sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat-conducting layer 710 may be greater than the height H4 of the first passive element 400. The first trench 691 is not provided, and the upper surface of the first passive element 400 may face the first lower surface 601b of the heat dissipation structure 600.

FIG. 3C is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II in FIG. 2C. FIG. 3D is a cross-sectional view showing a package system according to embodiments, and corresponds to a cross-section taken along line I-II in FIG. 2C.

Referring to FIGS. 2C, 3C, and 3D, the package system 1f, 1g includes a substrate 500, first to third semiconductor packages 100, 200, and 300, a first passive element 400, It may include first to third heat conductive layers 710, 720, and 730, and a heat dissipation structure 600.

The trench may include a first trench 691 and a second trench 692. The first trench 691 and the second trench 692 may be provided on the first lower surface 601b of the heat dissipation structure 600. Accordingly, the heat dissipation structure 600 may have a first lower surface (601b), a second lower surface (602b), and a third lower surface (603b).

The height H4 of the mounted first passive element 400 may be equal to or greater than the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat-conducting layer 710. As the first trench 691 is provided, even if the first passive element 400 is mounted on the top surface 500a of the substrate 500, the height A1 of the first heat-conducting layer 710 may be small.

The height H2 of the mounted second semiconductor package 200 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. The second trench 692 may overlap the second semiconductor package 200 in a plan view. The second heat-conducting layer 720 may be in physical contact with the third lower surface 603b of the heat dissipation structure 600. The height A1 of the first heat-conducting layer 710 may be smaller than the height A2 of the second heat-conducting layer 720. The third lower surface 603b of the heat dissipation structure 600 may be provided at the same or different level from the second lower surface 602b.

The height H1 of the mounted first semiconductor package 100 is greater than the height H3 of the mounted third semiconductor package 300, and the third trench 693 may not be provided.

Referring to FIG. 3D, the trench may include a third trench 693 in addition to the first trench 691 and the second trench 692. First to third trenches 691, 692, and 693 may be provided on the first lower surface 601b of the heat dissipation structure 600. Accordingly, the heat dissipation structure 600 may have a first lower surface (601b), a second lower surface (602b), a third lower surface (603b), and a fourth lower surface (604b).

The height H3 of the mounted third semiconductor package 300 may be equal to or greater than the height H1 of the mounted first semiconductor package 100. The third heat-conducting layer 730 may be in physical contact with the fourth lower surface 604b of the heat dissipation structure 600. The height A1 of the first heat-conducting layer 710 may be smaller than the height A4 of the fourth heat-conducting layer 740. The level of the fourth lower surface 604b of the heat dissipation structure 600 is the height H1 of the mounted first semiconductor package 100, the height H3 of the mounted third semiconductor package 300, and the first heat conductive layer. It can be determined according to the height (A1) of 710. The fourth lower surface 604b of the heat dissipation structure 600 is shown as being provided at a different level from the second lower surface 602b, but the fourth lower surface 604b may be disposed at the same level as the second lower surface 602b. . In this case, the first trench 691 and the third trench 693 may be formed integrally.

According to embodiments, the first to third trenches 691, 692, and 693 are provided according to the height H4 of the mounted first passive element 400 and the height H4 of the mounted second semiconductor package 200, respectively. (H2), can be adjusted according to the mounted third semiconductor package 300. For example, when the height H4 of the mounted first passive element 400 is smaller than the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat-conducting layer 710, The first trench 691 may not be provided. When the height H1 of the mounted first semiconductor package 100 is greater than the height H2 of the mounted second semiconductor package 200, the second trench 692 may not be provided. If the height H1 of the mounted first semiconductor package 100 is greater than the height H3 of the mounted third semiconductor package 300, the third trench 693 may not be provided.

FIG. 4 is a cross-sectional view showing a package system according to embodiments, taken along line I-II of FIG. 2C.

Referring to FIGS. 2C and 3B, the package system 1i includes a substrate 500, first to third semiconductor packages 100, 200, and 300, first passive elements 400, and first to third heat conduction devices. In addition to the layers 710, 720, and 730 and the heat dissipation structure 600, it may include a third heat-conducting layer 740. The height H4 of the mounted first passive element 400 may be equal to or greater than that of the mounted first semiconductor package 100. A first trench 691 may be provided on the first lower surface 601b of the heat dissipation structure 600.

The fourth heat-conducting layer 740 may be provided between the first passive element 400 and the heat dissipation structure 600. The fourth heat-conducting layer 740 may include a thermal interface material. The fourth heat-conducting layer 740 may contact the second lower surface 602b of the heat dissipation structure 600. Heat generated from the first passive element 400 may be transferred to the heat dissipation structure 600 through the fourth heat-conducting layer 740. When the package system 1i operates, the first semiconductor package 100 may emit more heat than the first passive element 400. Since the first trench 691 is provided, the height A1 of the first heat-conducting layer 710 may be smaller than the height A4 of the fourth heat-conducting layer 740.

Unlike shown, when the height H4 of the mounted first passive element 400 is smaller than the mounted first semiconductor package 100, the first trench 691 may not be provided. In this case, the fourth heat-conducting layer 740 may physically contact the first lower surface 601b of the heat dissipation structure 600. As another example, a second trench 692 or a third trench 693 may be further provided on the first lower surface 601b of the heat dissipation structure 600.

In the description of FIGS. 3A to 3D and FIG. 4 , the second heat dissipation structure 620 and the heat dissipation adhesive layer 630 may be omitted. As another example, the leg portion 602 of the first heat dissipation structure 610 may not be provided, and the first heat dissipation structure 610 may be spaced apart from the substrate 500 . In this case, the conductive adhesive pattern 741 may not be provided. As another example, the second heat dissipation structure 620, the heat dissipation adhesive layer 630, and the leg portion 602 of the heat dissipation structure 600 may not be provided.

5A is a cross-sectional view showing a semiconductor module according to embodiments. FIG. 5B is a diagram for explaining a second passive element according to embodiments, and is an enlarged cross-section of region C of FIG. 5A. FIG. 5C is a diagram for explaining lower pads and conductive terminals according to embodiments, and is an enlarged view of area VI of FIG. 5A. FIG. 5D is a diagram for explaining lower pads according to embodiments, and corresponds to an enlarged view of region VI of FIG. 5A.

Referring to FIGS. 1A, 5A, and 5B, the semiconductor module 10 may include a board 1000 and a package system 1. For example, a printed circuit board may be used as the board 1000. Conductive pads 1500 may be provided on the top surface 1000a of the board 1000. The conductive pads 1500 may be electrically connected to internal wiring of the board 1000.

The package system 1 described in FIGS. 1A to 1C may be mounted on the board 1000 to form the semiconductor module 10. As another example, the package system 1a of FIGS. 2A and 2B, the package system 1b of FIGS. 2C and 2D, the package system 1c of FIG. 2E, the package system 1d of FIG. 3A, and the package system of FIG. 3B. (1e), the package system 1f of FIG. 3C, the package system 1g of FIG. 3D, or the package system 1h of FIG. 4 may be mounted on the board 1000 to form the semiconductor module 10. there is. For convenience, the package system 1 of FIGS. 1A to 1C is illustrated and described with respect to the semiconductor module 10 mounted on the board 1000, but the present invention is not limited thereto.

Mounting the package system 1 involves providing the package system 1 on the board 1000 so that the conductive terminals 550 face the board 1000, and attaching the conductive terminals 550 to the conductive pads ( 1500) and may include connecting each. The pitch of the conductive terminals 550 may be substantially the same as the pitch P4 of the conductive pads 1500. The pitch P4 of the conductive pads 1500 may be standardized. For example, the pitch P4 of the conductive pads 1500 may satisfy the JEDEC standard. The pitch P4 of the conductive pads 1500 may be relatively large. For example, the pitch P4 of the conductive pads 1500 may be 0.65 mm or more.

When the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 are mounted directly on the board 1000, the pitch P1 of the first connection terminals 150, Each of the pitch P2 of the two connection terminals 250 and the pitch P3 of the third connection terminals 350 may be required to be substantially equal to the pitch P4 of the conductive pads 1500. . According to embodiments, the first to third semiconductor packages 100, 200, and 300 may be connected to the board 1000 through the substrate 500. Accordingly, the pitch (P1) of the first connection terminals 150, the pitch (P2) of the second connection terminals 250, and the pitch (P3) of the third connection terminals 350 are conductive pads ( It can be designed more freely without being restricted by the pitch (P4) of 1500).

The pitch P1 of the first connection terminals 150 may be smaller than the pitch P4 of the conductive pads 1500. For example, the pitch P1 of the first connection terminals 150 may be 0.4 mm or less. Accordingly, the first connection terminals 150 are provided more densely, so the planar area of the first semiconductor package 100 can be reduced. Each of the pitch P2 of the second connection terminals 250 and the pitch P3 of the third connection terminals 350 may be smaller than the pitch P4 of the conductive pads 550 . For example, the pitch (P2) of the second connection terminals 250 and the pitch (P3) of the third connection terminals 350 may each be 0.4 mm or less. Accordingly, the second semiconductor package 200 and the third semiconductor package 300 can be miniaturized. Since the first to third semiconductor packages 100, 200, and 300 are miniaturized, the distances between the first to third semiconductor packages 100, 200, and 300 may be reduced. Accordingly, the lengths of electrical signal paths between the first to third semiconductor packages 100, 200, and 300 may be reduced. The operating speed and reliability of the package system 1 can be improved.

A fourth semiconductor package 800 may be further provided on the lower surface 1000b of the board 1000. The fourth semiconductor package 800 may include a fourth substrate 810, a fourth semiconductor chip 820, and a fourth molding film 830. Fourth connection terminals 850 may be interposed between the board 1000 and the fourth semiconductor package 800. The fourth semiconductor package 800 may be electrically connected to the board 1000 through fourth connection terminals 850. The fourth connection terminals 850 may include at least one of solder balls, bumps, and pillars. The height H5 of the mounted fourth semiconductor package 800 may be defined to include the height of the fourth connection terminals 850. For example, the height H5 of the fourth semiconductor package 800 is equal to the height of the fourth connection terminals 850, the height of the fourth substrate 810, and the height of the fourth molding film 830. It may be equal to the sum. The height H5 of the mounted fourth semiconductor package 800 may be greater than the height H1 of the mounted first semiconductor package 100. Even if the height H5 of the mounted fourth semiconductor package 800 is large, the fourth semiconductor package 800 can be electrically connected to the package system 1 through the board 1000.

The fourth semiconductor package 800 may be electrically connected to any one of the first to third semiconductor packages 100, 200, and 300 or the first passive element 400. The fourth semiconductor package 800 may be provided overlapping or adjacent to any of the first to third semiconductor packages 100, 200, and 300 or the first passive element 400. Accordingly, the signal length between the fourth semiconductor package 800 and one of the first to third semiconductor packages 100, 200, and 300 or the first passive element 400 may be reduced. A plurality of fourth semiconductor packages 800 may be provided. In this case, the heights H4 of the fourth semiconductor packages 800 may be the same or different from each other.

The second passive element 420 may be mounted on the bottom of the board 1000. Second connection terminal units may be further provided between the board 1000 and the second passive element 420. The second passive element 420 may be connected to the board 1000 through the second connection terminal portions 412. The second connection terminal portions 412 may include solder material. The height H6 of the mounted second passive element 420 may be defined to include the height H61 of the second connection terminal portions 412. For example, the height H6 of the second passive element 420 is equal to the height H61 of the second connection terminals 412 and the height H60 of the first passive element 420' before mounting. It may be equal to the sum of . The height H6 of the mounted second passive element 420 may be greater than the sum of the height H1 of the mounted first semiconductor package 100 and the height A1 of the first heat-conducting layer 710. Even if the height H6 of the mounted second passive element 420 is large, the second passive element 420 may be electrically connected to the package system 1 through the board 1000.

The second passive element 420 may be electrically connected to any one of the first to third semiconductor packages 100, 200, and 300. The second passive element 420 may be provided to overlap or be adjacent to one of the semiconductor packages 100, 200, and 300 from a plan view. Accordingly, the signal length between the second passive element 420 and one of the semiconductor packages 100, 200, and 300 may be reduced. The second passive element 420 may be provided in plural numbers. In this case, the heights H6 of the second passive elements 420 may be the same or different from each other. Hereinafter, the conductive terminals 550 and the lower pads 540 will be described with reference to FIGS. 5C and 5D.

Referring to FIGS. 5A to 5C , lower pads 540 may be provided on the lower surface 500b of the substrate 500 . The lower pads 540 may include a connection pad 541 and a test pad 542. During the manufacturing process of the package system 1 or before the package system 1 is mounted on the board 1000, the electrical characteristics of the package system 1 may be evaluated. Evaluation of the electrical characteristics can be performed using a test pad 542. For example, a probe (not shown) contacts the test pad 542 to detect among the first to third semiconductor packages 100, 200, 300, the first passive device 400, and the electronic device 430. At least one electrical property can be evaluated. Afterwards, conductive terminals 550 are formed, and the package system 1 can be mounted on the board 1000.

As shown in FIG. 5C, conductive terminals 550 may be provided on the lower surfaces of the lower pads 540, respectively. The conductive terminal 550 may include a first terminal 551 and a second terminal 552. The first terminal 551 can be connected to the connection pad 541. The first terminal 551 may electrically connect at least one of the first to third semiconductor packages 100, 200, and 300 to the board 1000. The first terminal 551 may function as a signal transmission path.

The second terminal 552 can be connected to a test terminal. For example, the second terminal 552 may function as a ground terminal, and a ground voltage may be applied to the second terminal 552. The test pad 542 may serve as a supply path for ground voltage. As another example, the second terminal 552 may function as a dummy terminal, so that the second terminal 552 may not be electrically connected to the conductive pads 1500.

As shown in FIG. 5D, the second terminal 552 may not be provided. The test pad 542 may not be physically or electrically connected to the board 1000. Although not shown, underfill material may further fill the gap between the board 1000 and the test terminal. The underfill material may include an insulating polymer.

The detailed description of the invention above is not intended to limit the invention to the disclosed embodiments, and can be used in various other combinations, changes, and environments without departing from the gist of the invention.

Claims (20)

Board;
a first semiconductor package mounted on the upper surface of the substrate and including a first semiconductor chip, the first semiconductor chip including logic circuits;
a first heat-conducting layer provided on the first semiconductor package;
a second heat-conducting layer provided on the second semiconductor package;
a second semiconductor package mounted on the upper surface of the substrate;
a first passive element mounted on the top surface of the substrate; and
A heat dissipation structure provided on the first heat-conducting layer, the second semiconductor package, and the first passive element,
The heat dissipation structure is:
a first lower surface in physical contact with the first heat-conducting layer; and
It has a second lower surface disposed at a higher level than the first lower surface,
The second lower surface is provided on the first passive element,
Among the lower surfaces of the heat dissipation structure, the level of the second lower surface on the first passive element is the highest,
A semiconductor package system wherein the level of the top surface of the first heat-conducting layer is the same as the level of the top surface of the second heat-conducting layer.
According to clause 1,
A semiconductor package system wherein the height of the first heat-conducting layer is smaller than the height of the second heat-conducting layer. According to clause 2,
A semiconductor package system wherein the height of the second semiconductor package is equal to or greater than the height of the first semiconductor package. According to clause 3,
A semiconductor package system wherein the first passive element is in physical contact with the second lower surface. According to clause 2,
A package system wherein the second semiconductor package includes a package substrate, a second semiconductor chip, and a molding film, and the second semiconductor chip includes a memory circuit or a power management integrated circuit. According to clause 1,
The height of the mounted first passive element is equal to or greater than the sum of the height of the mounted first semiconductor package and the height of the first heat-conducting layer,
The second lower surface of the heat dissipation structure is provided on the first passive element. According to clause 1,
Further comprising a dam structure between the first semiconductor package and the first passive element,
The height of the dam structure is equal to or smaller than the sum of the height of the first semiconductor package and the height of the first heat-conducting layer. According to clause 1,
a ground pattern provided on the upper surface of the substrate and to which a ground voltage is applied; and
Further comprising a conductive adhesive film interposed between the ground pattern and the heat dissipation structure,
A semiconductor package system wherein the heat dissipation structure is electrically connected to the ground pattern through the conductive adhesive film. According to clause 1,
a board provided on the lower surface of the substrate; and
A semiconductor package system further comprising conductive terminals connected to the substrate and the board. According to clause 9,
It further includes a second passive element mounted on the bottom of the board,
A semiconductor package system wherein the height of the mounted second passive element is greater than the sum of the height of the mounted first semiconductor package and the height of the first heat-conducting layer.
Board;
a first semiconductor package mounted on the substrate;
a second semiconductor package mounted on the substrate;
Passive elements mounted on the board;
a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the passive element; and
Includes a plurality of heat-conducting layers each physically contacting the heat dissipation structure,
The heat-conducting layers include a first heat-conducting layer provided on the upper surface of the first semiconductor package, and
It includes a second heat-conducting layer provided on the upper surface of the second semiconductor package, wherein the first heat-conducting layer has the thinnest thickness among the heat-conducting layers,
A trench is provided on the first lower surface of the heat dissipation structure, and the trench overlaps at least one of the second semiconductor package and the passive element in a plan view,
The level of the top surface of the first heat-conducting layer is the same as the level of the top surface of the second heat-conducting layer,
A semiconductor package system wherein the level of the lower surface of the heat dissipating structure on the passive element is the highest among the lower surfaces of the heat dissipating structure. According to clause 11,
A semiconductor package system wherein the height of the passive element is equal to or greater than the sum of the height of the mounted first semiconductor package and the height of the first heat-conducting layer, and the trench overlaps the passive element in a plan view. According to clause 11,
A semiconductor package system wherein the heat-conducting layers include a second heat-conducting layer provided on an upper surface of the second semiconductor package. According to clause 13,
A semiconductor package system wherein the height of the second semiconductor package is equal to or greater than the height of the first semiconductor package, and the trench overlaps the second semiconductor package in plan view. According to clause 11,
The first semiconductor package further includes a first substrate, a first semiconductor chip, and a first molding film, and the first semiconductor chip includes a system-on-chip. According to clause 15,
A semiconductor package system wherein the second semiconductor package includes a power semiconductor chip or a memory chip. According to clause 11,
The trench is:
a first trench overlapping the passive element in plan view; and
A semiconductor package system comprising a second trench overlapping the second semiconductor package, wherein the bottom of the second trench is provided at a different level from the bottom of the first trench. Board;
a first semiconductor package mounted on the substrate;
a second semiconductor package mounted on the substrate;
Passive elements mounted on the board;
a heat dissipation structure provided on the first semiconductor package, the second semiconductor package, and the passive element;
a first heat-conducting layer interposed between the first semiconductor package and the heat dissipation structure; and
It includes a second heat-conducting layer interposed between the second semiconductor package and the cylindrical heat dissipation structure,
The height of the mounted passive element is equal to or greater than the sum of the height of the mounted first semiconductor package and the height of the first heat-conducting layer,
The level of the top surface of the first heat-conducting layer is the same as the level of the top surface of the second heat-conducting layer,
The heat dissipation structure is:
a first lower surface in physical contact with the first heat-conducting layer; and
It has a second lower surface disposed at a higher level than the first lower surface,
The second lower surface of the heat dissipation structure is provided on the passive element,
A semiconductor package system wherein the level of the lower surface of the heat dissipating structure on the passive element is the highest among the lower surfaces of the heat dissipating structure. According to clause 18,
The first semiconductor package is a semiconductor package system including a system-on-chip. According to clause 18,
a second semiconductor package mounted on the substrate; and
Further comprising a second heat-conducting layer provided on the second semiconductor package,
A semiconductor package system wherein the height of the first heat-conducting layer is smaller than the height of the second heat-conducting layer.