TWI778249B - Semiconductor package system - Google Patents

Abstract

Provided is a semiconductor package system. The system includes a substrate, a first semiconductor package on the substrate, a second semiconductor package on the substrate, a first passive element on the substrate, a heat dissipation structure on the first semiconductor package, the second semiconductor package, and the first passive element, and a first heat conduction layer between the first semiconductor package and the heat dissipation structure. A sum of a height of the first semiconductor package and a height of the first heat conduction layer may be greater than a height of the first passive element. The height of the first semiconductor package may be greater than a height of the second semiconductor package.

Description

Semiconductor Packaging System

This article is about a semiconductor packaging system, and more specifically, a semiconductor packaging system having a heat dissipation structure.

[Cross-reference to related applications]

This US non-provisional patent application claims priority to Korean Patent Application No. 10-2018-0054304, filed on May 11, 2018; Korean Patent Application No. 10-, filed May 11, 2018 Priority of 2018-0054305; Priority of Korean Patent Application No. 10-2018-0054307 filed on May 11, 2018; Korean Patent Application No. 10- filed on May 14, 2018 Priority to 2018-0055081; and Korean Patent Application No. 10-2018-0110511, filed on September 14, 2018, each of which is incorporated in its entirety This case is for reference.

Semiconductor packages are implemented in a form suitable for use in electronic products. In general, semiconductor packages are typically mounted with semiconductor chips on a printed circuit board (PCB) and are electrically connected to each other using bonding wires or bumps. As semiconductor packaging increases in speed and capacity The increase in power consumption of semiconductor packaging has increased. Therefore, the thermal characteristics of the semiconductor package become more important.

The inventive concept relates to a semiconductor package with improved thermal characteristics and a semiconductor module including the same.

According to an embodiment of the inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package on the substrate; a second semiconductor package on the substrate; a first passive element on the substrate; The structure is disposed on the first semiconductor package, the second semiconductor package and the first passive element; and a first heat conduction layer is located between the first semiconductor package and the heat dissipation structure. The sum of the height of the first semiconductor package and the thickness of the first thermally conductive layer may be greater than the height of the first passive element. The height of the first semiconductor package may be greater than the height of the second semiconductor package.

In an embodiment of the inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package on an upper surface of the substrate, and the first semiconductor package includes a first semiconductor die, the first semiconductor die including one or more logic circuits; a second semiconductor package located on the upper surface of the substrate; passive components located on the upper surface of the substrate; a heat dissipation structure located on the first semiconductor package, the on the second semiconductor package and the passive element; and a plurality of thermally conductive layers, each of which physically contacts the lower surface of the heat dissipation structure. The plurality of thermally conductive layers may include a first thermally conductive layer on the upper surface of the first semiconductor package, and the first thermally conductive layer may have the most thermally conductive layer among the plurality of thermally conductive layers. thin thickness.

In an embodiment of the inventive concept, a semiconductor packaging system may include: a substrate; a first semiconductor package on the substrate, the first semiconductor package including a first semiconductor die including one or more a logic circuit; a second semiconductor package on the substrate; a passive element on the substrate; a heat dissipation structure on the first semiconductor package, the second semiconductor package and the passive element; a first a thermally conductive layer on the first semiconductor package, the first thermally conductive layer physically in contact with the heat dissipation structure; and a second thermally conductive layer on the second semiconductor package, the second thermally conductive layer in physical contact the heat dissipation structure. The thickness of the first thermally conductive layer may be smaller than the thickness of the second thermally conductive layer. The upper surface of the first heat conduction layer may be disposed at a higher level than the upper surface of the passive element.

1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j: Package system

10: Semiconductor module

100: Semiconductor Package/First Semiconductor Package

100c: side surface

110: The first substrate

120: First semiconductor wafer

130: First molding layer

139: First Mark

140: The first thermal conductive structure

141: The first adhesive layer

150: The first connection terminal

160: First underfill film

200: Semiconductor Packaging/Second Semiconductor Packaging

210: Second substrate

220: Second semiconductor wafer

230: Second molding layer

240: Second thermal conductive structure

241: Second Adhesive Layer

250: Second connection terminal

260: Second underfill film

300: Semiconductor Packaging/Third Semiconductor Packaging

310: Third substrate

320: Third Semiconductor Wafer

330: Third molding layer

340: The third thermal conductive structure

341: Third Adhesive Layer

350: The third connection terminal

360: Third Underfill Film

400: First Passive Component/Installed First Passive Component

400': The first passive component before being installed

401: The first connection terminal part

402: Second connection terminal part

403: Conductive connection terminal

420: Second Passive/Installed Second Passive

420': Second passive component before being installed

430: Electronic Components/Mounted Electronic Components

430': Electronic components before being installed

500: Substrate

500a, 710a, 1000a: upper surface

505: Interconnects

510G: Ground Pad

540: Lower pad

541: Connection pad

542: Test pads

550: Conductive terminal

551: first terminal

552: second terminal

590: Dam Structure

600: heat dissipation structure

500b, 600b, 1000b: lower surface

610: The first heat dissipation structure

620: Second heat dissipation structure

621: Body part

622: Leg Section

630: heat dissipation layer

710: The first heat conduction layer

720: Second heat conduction layer

730: Third heat conduction layer

740: Fourth heat conduction layer

741: Bonding Pattern/Conductive Bonding Pattern

742: Bonding Pattern/Insulating Bonding Pattern

1000: Board

1500: Conductive pads

A, B, C, III, VI: Zones

A1, A2, A3, A4, A5: Thickness

H1, H2, H3, H4, H40, H41, H5, H50, H51, H6, H60, H61, H7: Height

I-II, I'-II': line

P1, P2, P3, P4: pitch

The accompanying drawings are included to provide a further understanding of the inventive concepts, and are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concepts and, together with the description, serve to explain the principles of the inventive concepts. In the drawings: FIG. 1A is a plan view illustrating a packaging system according to an exemplary embodiment.

FIG. 1B is a plan view illustrating a packaging system according to an exemplary embodiment.

FIG. 1C is a cross-sectional view taken along line I-II shown in FIG. 1A .

FIG. 1D is an enlarged view of the area A shown in FIG. 1C. FIG. 1E is an enlarged view of area B shown in FIG. 1C.

FIG. 1F is a diagram illustrating a packaging system according to an exemplary embodiment.

FIG. 1G corresponds to an enlarged view of region III shown in FIG. 1A.

Fig. 1H is a cross-sectional view taken along the line I'-II' shown in Fig. 1G.

FIG. 1I is a diagram for explaining a first semiconductor package according to an exemplary embodiment.

FIG. 2A is a plan view illustrating a packaging system according to an exemplary embodiment.

FIG. 2B is a cross-sectional view taken along the line I-II shown in FIG. 2A.

FIG. 2C is a plan view illustrating a packaging system according to an exemplary embodiment.

2D is a cross-sectional view taken along line I-II shown in FIG. 2C.

2E is a cross-sectional view illustrating a packaging system according to an exemplary embodiment.

3A is a cross-sectional view illustrating a packaging system according to an exemplary embodiment.

3B is a cross-sectional view illustrating a packaging system according to an exemplary embodiment.

3C is a cross-sectional view illustrating a packaging system according to an exemplary embodiment.

4A is a cross-sectional view illustrating a packaging system according to an exemplary embodiment.

4B is a cross-sectional view illustrating a packaging system according to an exemplary embodiment.

4C is a cross-sectional view illustrating a packaging system according to an exemplary embodiment.

FIG. 5A is a cross-sectional view illustrating a semiconductor module according to an exemplary embodiment.

FIG. 5B is a diagram for explaining a second passive element according to an exemplary embodiment, and is a cross-sectional view showing an enlarged view of a region C shown in FIG. 5A .

FIG. 5C is a diagram for explaining lower pads and conductive terminals according to an exemplary embodiment.

FIG. 5D is a diagram for explaining a lower pad according to an exemplary embodiment.

In this specification, the same reference numerals refer to the same components throughout the specification. Hereinafter, a packaging system according to the inventive concept and a semiconductor module including the packaging system will be explained. The semiconductor packaging system may be a packaging system or a semiconductor module including the packaging system.

FIG. 1A is a plan view illustrating a packaging system according to an exemplary embodiment. FIG. 1B is a plan view illustrating a packaging system according to an exemplary embodiment. FIG. 1C is a cross-sectional view taken along line I-II shown in FIG. 1A . FIG. 1D is an enlarged view of the area A shown in FIG. 1C. FIG. 1E is an enlarged view of area B shown in FIG. 1C.

1A , 1B, 1C, 1D and 1E, the packaging system 1 includes a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 , a third semiconductor package 300 , a first passive element 400 , and a heat dissipation structure 600 and the first thermal conduction layer 710 . As an example, a printed circuit board (PCB) having circuit patterns may be used as the substrate 500 . Conductive terminals 550 may be provided on the lower surface of the substrate 500 . The conductive terminals 550 may include at least one of solder balls, bumps, and pillars. The conductive terminals 550 may comprise metal, for example.

The first semiconductor package 100 may be mounted on the upper surface 500 a of the substrate 500 . The first semiconductor package 100 may include a logic die or a system-on-chip (SOC) as described later. The first connection terminal 150 may be interposed between the substrate 500 and the first semiconductor package 100 . The first semiconductor package 100 may be electrically connected to the substrate 500 through the first connection terminal 150 . In this specification, being electrically connected to the substrate 500 may mean that it is connected to an interconnection 505 in the substrate 500 Electrical connection. The first connection terminals 150 may include solder balls, pillars, bumps or ball grid arrays. The height H1 of the mounted first semiconductor package 100 may be defined as a height including the first connection terminal 150 . In this specification, the height of any component may mean the maximum distance of the component measured in a direction perpendicular to the upper surface 500a of the substrate 500 . The pitch of the first connection terminals 150 may be smaller than the pitch of the conductive terminals 550 .

The second semiconductor package 200 may be mounted on the upper surface 500 a of the substrate 500 . In a plan view, the second semiconductor package 200 may be spaced apart from the first semiconductor package 100 . The second semiconductor package 200 may be a different type of semiconductor package from the first semiconductor package 100 . The second connection terminal 250 may be interposed between the substrate 500 and the second semiconductor package 200 . The second semiconductor package 200 may be electrically connected to the substrate 500 via the second connection terminals 250 . The second connection terminals 250 may include solder balls, posts, bumps, or ball grid arrays. The pitch of the second connection terminals 250 may be smaller than the pitch of the conductive terminals 550 . The height H2 of the mounted second semiconductor package 200 may be defined as a height including the second connection terminal 250 . A plurality of second semiconductor packages 200 may be provided. The second semiconductor packages 200 may be spaced apart from each other. However, various modifications can be made to the number and plane arrangement of the second semiconductor packages 200 .

The third semiconductor package 300 may be mounted on the substrate 500 . In a plan view, the third semiconductor package 300 may be spaced apart from the first semiconductor package 100 and the second semiconductor package 200 . The third semiconductor package 300 may be a different type of semiconductor package from the first semiconductor package 100 and the second semiconductor package 200 . As shown in FIG. 1A, a single third semiconductor package 300 may be provided. As another example, as shown in FIG. 1B , a plurality of third semiconductor packages 300 may be provided. In this case, the third semiconductor The body packages 300 may be spaced apart from each other. Various modifications can be made to the number and planar arrangement of the third semiconductor packages 300 and are not limited to those shown in FIGS. 1A and 1B . In the following, a single third semiconductor package 300 will be explained. As shown in FIG. 1C , a third connection terminal 350 may be interposed between the substrate 500 and the third semiconductor package 300 . The third semiconductor package 300 may be electrically connected to the substrate 500 via the third connection terminals 350 . The third connection terminals 350 may include solder balls, posts, bumps, or ball grid arrays. The pitch of the third connection terminals 350 may be smaller than the pitch of the conductive terminals 550 . The height H3 of the mounted third semiconductor package 300 may be defined as a height including the third connection terminal 350 . The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the mounted third semiconductor package 300 .

The first passive element 400 may be mounted on the upper surface 500 a of the substrate 500 . In a plan view, the first passive element 400 may be spaced apart from the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 . The first passive element 400 may include any one of an inductor, a resistor, and a capacitor. As shown in FIG. 1D , a first connection terminal portion 401 may be further provided between the substrate 500 and the first passive element 400 . The first connection terminal portion 401 may include, for example, solder balls, posts, bumps, or ball grid arrays. The height H4 of the mounted first passive element 400 may be defined as including the height of the first connection terminal portion 401 . For example, the height H4 of the first passive element 400 may be equal to the sum of the height H41 of the first connection terminal portion 401 and the height H40 of the first passive element 400 ′ before being mounted. The height H4 of the mounted first passive element 400 may be substantially equal to the distance between the upper surface 500 a of the substrate 500 and the uppermost surface of the first passive element 400 . A plurality of first passive elements 400 may be provided. As shown As shown in 1A and 1B, the first passive elements 400 may be spaced apart from each other. Various modifications can be made to the number and plane arrangement of the first passive elements 400 . In the following, a single first passive element 400 will be explained. In the drawings other than FIG. 1D , the first connection terminal portion 401 is omitted for simplicity, but the inventive concept is not limited thereto.

A heat dissipation structure 600 may be disposed on the first semiconductor package 100 , the second semiconductor package 200 , the third semiconductor package 300 and the first passive element 400 . The lower surface 600b of the heat dissipation structure 600 may face the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 . The lower surface 600b of the heat dissipation structure 600 may be substantially flat. For example, the lower surface 600b of the heat dissipation structure 600 located on the first semiconductor package 100, the lower surface 600b of the heat dissipation structure 600 located on the second semiconductor package 200, the lower surface 600b located on the third semiconductor package 300 of the heat dissipation structure 600 600b and the lower surface 600b on the first passive element 400 may be disposed at substantially the same level. Additional processing performed on the lower surface 600b of the heat dissipation structure 600 is omitted so that the manufacture of the heat dissipation structure 600 can be simplified. The machining may include forming trenches or forming protrusions. The heat dissipation structure 600 may include thermally conductive material. Thermally conductive materials may include metals (eg, copper and/or aluminum) or carbon-containing materials (eg, graphene, graphite, and/or carbon nanotubes). The heat dissipation structure 600 may have relatively high thermal conductivity. As an example, a single metal layer or multiple stacked metal layers may be used as heat dissipation structure 600 . As another example, the heat dissipation structure 600 may include a heat sink or a heat pipe. As another example, the heat dissipation structure 600 may use a water cooling method. The heat dissipation structure 600 may include a first heat dissipation structure 610 . The first heat dissipation structure 610 may be spaced apart from the substrate 500 .

The first thermally conductive layer 710 may be interposed between the first semiconductor package 100 and the heat dissipation structure 600 . The first thermally conductive layer 710 may physically contact the upper surface of the first semiconductor package 100 and the lower surface 600b of the heat dissipation structure 600 . The first thermally conductive layer 710 may include a thermal interface material (TIM). Thermal interface materials can include, for example, polymers and thermally conductive particles. Thermally conductive particles can be dispersed within the polymer. During operation of the first semiconductor package 100 , heat generated from the first semiconductor package 100 may be transferred to the heat dissipation structure 600 via the first thermally conductive layer 710 .

According to exemplary embodiments, the sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first thermal conduction layer 710 may be greater than the height H4 of the mounted first passive element 400 . Even though the first passive element 400 is disposed on the upper surface 500 a of the substrate 500 , the first thermally conductive layer 710 can still physically contact the first semiconductor package 100 and the heat dissipation structure 600 .

A second thermal conduction layer 720 may be disposed between the second semiconductor package 200 and the heat dissipation structure 600 . The second thermally conductive layer 720 may physically contact the upper surface of the second semiconductor package 200 and the lower surface 600b of the heat dissipation structure 600 . For example, the second thermally conductive layer 720 may include a thermal interface material. During operation of the second semiconductor package 200 , heat generated from the second semiconductor package 200 may be transferred to the heat dissipation structure 600 via the second thermally conductive layer 720 .

A third heat conduction layer 730 may be disposed between the third semiconductor package 300 and the heat dissipation structure 600 . The third thermally conductive layer 730 may physically contact the upper surface of the third semiconductor package 300 and the lower surface 600b of the heat dissipation structure 600 . For example, the third heat Conductive layer 730 may include thermal interface material. During operation of the third semiconductor package 300 , heat generated from the third semiconductor package 300 may be transferred to the heat dissipation structure 600 via the third thermally conductive layer 730 .

During operation of the packaging system 1 , a large amount of heat may be generated from the first semiconductor package 100 . For example, the first semiconductor package 100 may generate more heat than the heat generated from the second semiconductor package 200 , the third semiconductor package 300 and the first passive element 400 . The thermal characteristics of the first semiconductor package 100 may have a greater effect on the operating characteristics of the packaging system 1 than the thermal characteristics of the second semiconductor package 200 and the third semiconductor package 300 have on the operating characteristics of the packaging system 1 . Since the thermal characteristics of the first semiconductor package 100 are improved, the operational characteristics of the packaging system 1 may be improved. Each of the first thermally conductive layer 710 , the second thermally conductive layer 720 and the third thermally conductive layer 730 may have a thermal conductivity lower than that of the heat dissipation structure 600 . As the thickness A1 of the first thermal conduction layer 710 decreases, the heat generated from the first semiconductor package 100 can be dissipated to the heat dissipation structure 600 more quickly. According to an exemplary embodiment, the thickness A1 of the first heat conduction layer 710 may be the smallest among the thicknesses of the heat conduction layers contacting the lower surface 600b of the heat dissipation structure 600 . Here, the thermal conduction layer may include a first thermal conduction layer 710 , a second thermal conduction layer 720 and a third thermal conduction layer 730 . The thermally conductive layer may further include a conductive adhesive pattern 741 which will be described later with reference to FIGS. 2A to 2D . For example, the thickness A1 of the first thermally conductive layer 710 may be smaller than the thickness A2 of the second thermally conductive layer 720 and the thickness A3 of the third thermally conductive layer 730 . Therefore, the heat generated from the first semiconductor package 100 can be transferred to the heat dissipation structure 600 more quickly. The packaging system 1 may exhibit improved operating characteristics.

Electronic components may be further disposed on the upper surface 500a of the substrate 500 430. The electronic component 430 may include an oscillator (eg, a crystal oscillator) or a real-time clock. As shown in FIG. 1E , a conductive connection terminal 403 may be further disposed between the electronic element 430 and the upper surface 500 a of the substrate 500 to be electrically connected to the electronic element 430 and the substrate 500 . The height H5 of the mounted electronic component 430 may be defined as the height H51 including the conductive connection terminals 403 . The height H5 of the mounted electronic component 430 may be equal to the sum of the height H51 of the conductive connection terminal 403 and the height H50 of the electronic component 430 ′ before being mounted. The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first thermal conductive layer 710 may be greater than the height H5 of the mounted electronic component 430 . Although the electronic components 430 are disposed on the upper surface 500 a of the substrate 500 , the heat generated from the first semiconductor package 100 can be smoothly discharged to the heat dissipation structure 600 through the first heat conduction layer 710 . As another example, the electronic components 430 may not be provided. In the drawings other than FIG. 1E , the conductive connection terminals 403 are omitted for simplicity, but the inventive concept is not limited thereto. In the following, the electrical connection of the semiconductor packages 100, 200 and 300 will be explained.

As shown in FIG. 1C , the first semiconductor package 100 is electrically connected to the second semiconductor package 200 , the third semiconductor package 300 and the conductive terminals 550 via the interconnects 505 of the substrate 500 . The second semiconductor package 200 may be electrically connected to the first semiconductor package 100 , the third semiconductor package 300 and the conductive terminals 550 via the interconnects 505 of the substrate 500 . The third semiconductor package 300 may be electrically connected to the first semiconductor package 100 , the second semiconductor package 200 and the conductive terminals 550 via the interconnects 505 of the substrate 500 .

may be disposed in the gap between the substrate 500 and the first semiconductor package 100 There is a first underfill film 160 to seal the first connection terminals 150 . A second underfill film 260 may be disposed in the gap between the substrate 500 and the second semiconductor package 200 to seal the second connection terminal 250 . A third underfill film 360 may be disposed in the gap between the substrate 500 and the third semiconductor package 300 to seal the third connection terminal 350 . The first underfill film 160 , the second underfill film 260 and the third underfill film 360 may include insulating polymers such as epoxy-based polymers. Since the first underfill film 160 , the second underfill film 260 and the third underfill film 360 are provided, the bonding reliability of the first connection terminal 150 , the second connection terminal 250 and the third connection terminal 350 can be improved. Unlike the illustrated embodiment, at least one of the first underfill film 160, the second underfill film 260, and the third underfill film 360 may be omitted.

A dam structure 590 may be further provided on the upper surface 500a of the substrate 500 . The dam structure 590 may be disposed between the third semiconductor package 300 and the first passive element 400 . The dam structure 590 may be formed using liquid resin. Although not shown in the drawings, the substrate 500 may include multiple layers, and an uppermost layer of the layers may include an insulating polymer such as a solder resist material. In one example, the dam structure 590 may be integrally formed with the uppermost layer of the substrate 500 . In this case, the dam structure 590 can be connected to the uppermost layer of the substrate 500 without an interface. As another example, the dam structure 590 may comprise a different material than that of the substrate 500 . For example, the dam structure 590 may be formed of the same material as any of the first underfill film 160 , the second underfill film 260 , and the third underfill film 360 . The height of the dam structure 590 may be equal to or smaller than the height H1 of the mounted first semiconductor package 100 and the thickness of the first thermal conduction layer 710 The sum of A1.

Various modifications can be made to the arrangement and number of dam structures 590 . For example, the dam structure 590 may be disposed between the first semiconductor package 100 and the first passive device 400 . As another example, the dam structure 590 may be disposed between the second semiconductor package 200 and the first passive element 400 . As shown in FIG. 1A, a plurality of dam structures 590 may be provided. The dam structures 590 may be spaced apart from each other. Hereinafter, each of the first semiconductor package 100 , the second semiconductor package 200 , and the third semiconductor package 300 will be explained in more detail.

FIG. 1F is a diagram illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 1A . Hereinafter, content overlapping the above-mentioned content will be omitted. In the description of FIG. 1F , FIGS. 1A , 1B and 1C are described together.

1F , the packaging system 1 a includes a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 and a third semiconductor package 300 , a first passive element 400 , a first thermal conduction layer 710 , a second thermal conduction layer 720 and a third thermal conduction layer Layer 730 and heat dissipation structure 600 .

The first semiconductor package 100 may include a first substrate 110 , a first semiconductor wafer 120 and a first molding layer 130 . As an example, a printed circuit board (PCB) may be used as the substrate 500 . As another example, a redistribution layer may be used as the substrate 500 . The first semiconductor wafer 120 may be mounted on the first substrate 110 in a flip-chip manner. A connection portion may be provided between the first semiconductor wafer 120 and the first substrate 110 . Connections may include solder balls, posts, bumps or ball grids array. The first semiconductor die 120 may be a system-on-chip (SOC), a logic die, or an application processor (AP) die. The first semiconductor wafer 120 may include circuits having different functions. The first semiconductor chip 120 may include logic circuits and memory circuits. The first semiconductor chip 120 may further include at least one of a digital integrated circuit (IC), a radio frequency integrated circuit (RFIC) and an input/output circuit. Generating heat from the first semiconductor package 100 may mean generating heat from the first semiconductor wafer 120 .

The first molding layer 130 may be disposed on the first substrate 110 to cover the first semiconductor wafer 120 . The first molding layer 130 covers the side surface and the upper surface of the first semiconductor wafer 120 to seal the first semiconductor wafer 120 . In this case, the upper surface of the first semiconductor package 100 may correspond to the upper surface of the first molding layer 130 . The first molding layer 130 may include an insulating polymer such as an epoxy molding compound. The first molding layer 130 may further extend into the gap between the first substrate 110 and the first semiconductor wafer 120 . Different from what is shown, additional underfill patterns may be filled in the gap between the first substrate 110 and the first semiconductor wafer 120 . The underfill pattern may be formed by a method of thermally compressing a non-conductive paste or a non-conductive film or by a capillary underfill process. The height H1 of the mounted first semiconductor package 100 is defined as the sum of the height of the first connection terminal 150 , the height of the first substrate 110 and the height of the first molding layer 130 .

The second semiconductor package 200 may include a second substrate 210 , a second semiconductor die 220 and a second molding layer 230 . Printed circuit board (PCB) or redistribution layers available The substrate 500 is used. The second semiconductor wafer 220 may be a different type of semiconductor wafer from the first semiconductor wafer 120 . For example, the second semiconductor chip 220 may function as a memory chip. The memory chips may include dynamic random access memory (DRAM) chips. As another example, the memory chip may include static random access memory (SRAM), magnetic random access memory (MRAM), and/or NAND flash memory (NAND). flash memory). Generating heat from the second semiconductor package 200 may mean generating heat from the second semiconductor wafer 220 . The second semiconductor wafer 220 may be mounted by a flip-chip method or a bonding wire method. When the second semiconductor wafer 220 is flip-chip mounted, an additional underfill pattern may be filled in the gap between the second substrate 210 and the second semiconductor wafer 220 . The second semiconductor package 200 may include a plurality of second semiconductor wafers 220 . As another example, the second semiconductor package 200 may include a single second semiconductor die 220 . The second molding layer 230 covers the side surface of the second semiconductor wafer 220 and the upper surface of the second semiconductor wafer 220 to seal the second semiconductor wafer 220 . In this case, the upper surface of the second semiconductor package 200 may correspond to the upper surface of the second molding layer 230 . Unlike what is shown, the second molding layer 230 covers the side surfaces of the second semiconductor wafer 220 and may expose the upper surface. In this case, the upper surface of the second semiconductor package 200 may correspond to the upper surface of the second molding layer 230 and the upper surface of the second semiconductor chip 220 exposed by the second molding layer 230 . The second molding layer 230 may include an insulating polymer such as an epoxy-based polymer. The height H2 of the mounted second semiconductor package 200 is defined as the height of the second connection terminal 250, the second base The sum of the height of the board 210 and the height of the second molding layer 230 .

The third semiconductor package 300 may include a third substrate 310 , a third semiconductor die 320 and a third molding layer 330 . A redistribution layer or a printed circuit board may be used as the third substrate 310 . When the redistribution layer is used as the third substrate 310, the third semiconductor package 300 can be fabricated in a fan-out panel level package or a fan-out wafer level package. . The third semiconductor wafer 320 may be a different type of semiconductor wafer from the first semiconductor wafer 120 and the second semiconductor wafer 220 . For example, the third semiconductor chip 320 may include a power management integrated circuit (PMIC) to function as a power management chip. Generating heat from the third semiconductor package 300 may mean generating heat from the third semiconductor wafer 320 . The third molding layer 330 may be disposed on the third substrate 310 to cover the upper surface and the side surface of the third semiconductor wafer 320 . In this case, the upper surface of the third semiconductor package 300 may correspond to the upper surface of the third molding layer 330 . Unlike what is shown, the third molding layer 330 covers the side surfaces of the third semiconductor wafer 320 and may expose the upper surface. In this case, the upper surface of the third semiconductor package 300 may correspond to the upper surface of the third molding layer 330 and the upper surface of the third semiconductor wafer 320 exposed by the third molding layer 330 . The third molding layer 330 may include an insulating polymer such as an epoxy-based polymer. The height H3 of the mounted third semiconductor package 300 is defined as the sum of the height of the third connection terminal 350 , the height of the third substrate 310 and the height of the third molding layer 330 . The formation of the third semiconductor package 300 may include: disposing the third semiconductor die 320 on the carrier substrate; forming a third molding layer 330 covering the third semiconductor die 320; removing the carrier substrate to expose exposing the lower surface of the third semiconductor wafer 320; and forming a redistribution layer on the exposed lower surface of the third semiconductor wafer 320 and the lower surface of the molding layer. In this case, the redistribution layer may be the third substrate 310 .

FIG. 1G corresponds to an enlarged view of region III shown in FIG. 1A. Fig. 1H is a cross-sectional view taken along the line I'-II' shown in Fig. 1G. In the following description, FIG. 1A , FIG. 1B , FIG. 1C , and FIG. 1D are referred to together.

Referring to FIGS. 1G and 1H , a first mark 139 may be disposed on the first molding layer 130 . For example, the first mark 139 may be disposed on the upper surface of the first molding layer 130 . Unlike this, the first mark 139 may be disposed on the side surface of the first molding layer 130 . The first marks 139 may be recessed portions on one surface of the first molding layer 130 . The formation of the first mark 139 may include removing a portion of the first mold layer 130 . When the first marks 139 are formed on the first semiconductor wafer 120 , the first semiconductor wafer 120 may be damaged during formation of the first marks 139 . For example, cracks may be formed on or in the first semiconductor wafer 120 . According to an exemplary embodiment, the first marks 139 may be disposed on the first molding layer 130 so that the first semiconductor wafer 120 may not be damaged during the formation process of the first marks 139 . The first indicia 139 may provide and display information about the first semiconductor package 100 . In the drawings other than FIGS. 1G to 1I , the first reference numeral 139 is omitted for convenience, but the inventive concept is not limited thereto.

A first thermal conduction layer 710 may be formed on the upper surface of the first semiconductor package 100 . The formation of the first thermally conductive layer 710 may include disposing a thermal interface material on the first semiconductor package 100 and then curing the thermal interface material. before being cured The thermal interface material can have fluidity. During the formation process of the first thermal conduction layer 710 , even if the thermal interface material located on the edge region of the upper surface of the first semiconductor package 100 flows down to the side surface 100 c of the first semiconductor package 100 , the thermal interface material located on the side surface 100 c of the first semiconductor package 100 The thermal interface material on the central region of the upper surface may still not flow down. Therefore, the first heat conduction layer 710 may well fill the gap between the central region of the upper surface of the first semiconductor package 100 and the heat dissipation structure 600 . For example, the upper surface 710 a of the first thermally conductive layer 710 located in the central region of the first semiconductor package 100 may physically contact the heat dissipation structure 600 . According to exemplary embodiments, since the first molding layer 130 is provided, the first semiconductor wafer 120 may be disposed in the central region of the first semiconductor package 100 in a plan view. Therefore, even if the thermal interface material partially flows downward during the forming process of the first thermal conduction layer 710 , the first thermal conduction layer 710 can still conduct the heat of the first semiconductor wafer 120 to the first heat dissipation structure 610 well. When the first molding layer 130 includes the first marks 139 , the first heat conduction layer 710 may extend into the first marks 139 . Referring to FIG. 1C , a second heat conduction layer 720 may be disposed on the upper surface of the second molding layer 230 . The formation of the second thermally conductive layer 720 may be performed by substantially the same method as set forth in the formation of the first thermally conductive layer 710 . Although the thermal interface material partially flows downward during the formation of the second thermally conductive layer 720 , the second thermally conductive layer 720 may well fill the gap between the central region of the upper surface of the second semiconductor package 200 and the heat dissipation structure 600 . The central region of the second semiconductor package 200 may be the region where the second semiconductor wafer 220 is disposed. Therefore, the heat generated from the second semiconductor package 220 can be well dissipated to the heat dissipation structure 600 through the second heat conduction layer 720 .

Although not shown in the drawings, second marks may be further provided on the second molding layer 230 . The second mark may be a recessed portion of the second molding layer 230 .

A third heat conduction layer 730 may be formed on the upper surface of the third molding layer 330 . The formation of the third thermally conductive layer 730 may be performed by substantially the same method as set forth in the formation of the first thermally conductive layer 710 . At this time, although the thermal interface material partially flows downward during the formation of the third thermal conduction layer 730 , the third thermal conduction layer 730 can still well fill the space between the central region of the upper surface of the third semiconductor package 300 and the heat dissipation structure 600 . gap between. The central area of the third semiconductor package 300 may be the area where the third semiconductor wafer 320 is disposed. Accordingly, thermal characteristics of the third semiconductor package 300 may be improved. Although not shown in the drawings, a third mark may be further provided on the third molding layer 330 . The third mark may be a recessed portion of the third molding layer 330 .

FIG. 1I is a diagram for explaining a first semiconductor package according to an exemplary embodiment, and corresponds to a cross-section taken along the line I′-II′ shown in FIG. 1G .

Referring to FIGS. 1G and 1I , the first semiconductor package 100 may include a first substrate 110 , a first semiconductor chip 120 and a first molding layer 130 . The first molding layer 130 covers the side surface of the first semiconductor wafer 120 and may expose the upper surface of the first semiconductor wafer 120 . In this case, the upper surface of the first semiconductor package 100 may correspond to the upper surface of the first molding layer 130 and the upper surface of the first semiconductor wafer 120 exposed by the first molding layer 130 . The exposed upper surface of the first semiconductor wafer 120 may directly physically contact the first thermally conductive layer 710 . The heat generated from the first semiconductor wafer 120 may be transferred to the heat dissipation structure 600 through the first thermal conduction layer 710 . because Therefore, the heat dissipation characteristics of the first semiconductor wafer 120 can be further improved.

FIG. 2A is a plan view illustrating a packaging system according to an exemplary embodiment. FIG. 2B is a cross-sectional view taken along the line I-II shown in FIG. 2A. Hereinafter, content overlapping the above-mentioned content will be omitted.

2A and 2B, the packaging system 1b includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200 and a third semiconductor package 300, a first passive element 400, a first thermally conductive layer 710, a second thermally conductive layer 720 and The third heat conduction layer 730 and the heat dissipation structure 600 . The substrate 500 , the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 , the first passive element 400 and the first thermally conductive layer 710 , the second thermally conductive layer 720 and the third thermally conductive layer 730 may be the same as those described above with reference to FIG. 1A Substantially the same as described to Figure II.

A ground pattern may be provided on the upper surface 500a of the substrate 500 . The ground pattern may include ground pads 510G. At least one of the conductive terminals 550 may serve as a ground terminal. A ground voltage may be applied to the ground pad 510G via the ground terminal and the substrate 500 .

The heat dissipation structure 600 may include a second heat dissipation structure 620 . The second heat dissipation structure 620 may include a body portion 621 and a leg portion 622 . The body portion 621 of the second heat dissipation structure 620 may be similar to the first heat dissipation structure 610 previously described with reference to FIGS. 1A to 1C . The lower surface 600b of the heat dissipation structure 600 may include the lower surface of the body portion 621 of the second heat dissipation structure 620 . For example, the body portion 621 may be disposed on the upper surface of the first semiconductor package 100 , the upper surface of the second semiconductor package 200 , and the upper surface of the third semiconductor package 300 . The first thermally conductive layer 710 may physically contact the second The lower surface of the body portion 621 of the heat dissipation structure 620 .

The leg portion 622 of the second heat dissipation structure 620 may be disposed between the edge region of the body portion 621 and the substrate 500 . The leg portion 622 of the second heat dissipation structure 620 may be connected to the body portion 621 . As shown in FIG. 2A , the first semiconductor package 100 , the second semiconductor package 200 , the third semiconductor package 300 , and the first passive element 400 may be spaced apart from the leg portions 622 of the second heat dissipation structure 620 . In plan view, the leg portion 622 may be disposed in an edge region of the substrate 500 . The second heat dissipation structure 620 may include a thermally conductive material.

The second heat dissipation structure 620 has conductivity and can shield the electromagnetic interference (EMI) of the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 . Electromagnetic interference means that electromagnetic waves radiated or conducted from one electrical component interfere with the receiving/transmitting function of other electrical components. With the second heat dissipation structure 620 , the operations of the first semiconductor package 100 , the second semiconductor package 200 , the third semiconductor package 300 and the first passive element 400 may not interfere with the operation of other packages or may not be interfered by other packages.

Adhesive patterns 741 and 742 may be disposed between the substrate 500 and the leg portions 622 of the second heat dissipation structure 620 to fix the second heat dissipation structure 620 to the substrate 500 . The adhesive patterns 741 and 742 may include a conductive adhesive pattern 741 and an insulating adhesive pattern 742 . The conductive adhesive pattern 741 may be disposed between the ground pad 510G and the leg portion 622 of the second heat dissipation structure 620 . The second heat dissipation structure 620 may be connected to the ground pad 510G via the conductive adhesive pattern 741 .

If more than a certain amount of charges are accumulated in the heat dissipation structure 600, the Charges can flow from the heat dissipation structure 600 into another conductive component and damage the conductive component. The conductive components include at least one of the following: integrated circuits and wires in the first semiconductor chip 120 , the second semiconductor chip 220 and the third semiconductor chip 320 , the first substrate 110 , the second substrate 210 and the third substrate 310 The wires, the first connection terminals 150 , the second connection terminals 250 , the third connection terminals 350 , and the interconnects in the substrate 500 . According to an exemplary embodiment, a ground voltage may be applied to the second heat dissipation structure 620 through the conductive adhesive pattern 741 . Therefore, the second heat dissipation structure 620 can limit and/or prevent electrical damage to the packaging system 1b due to electrostatic discharge (ESD).

An insulating adhesive pattern 742 may be disposed between the substrate 500 and the heat dissipation structure 600 . Therefore, the heat dissipation structure 600 is insulated from the substrate 500 to limit and/or prevent the occurrence of electrical shorts. The thickness A5 of the conductive adhesive pattern 741 may be substantially the same as the thickness of the insulating adhesive pattern 742 .

The height H7 of the leg portion 622 of the second heat dissipation structure 620 may be smaller than the height H1 of the mounted first semiconductor package 100 . At this time, the height H7 of the leg portion 622 may be equal to the height of the inner surface of the second heat dissipation structure 620 . The conductive adhesive pattern 741 may physically contact the lower surface of the leg portion 622 . Therefore, the thickness A1 of the first thermally conductive layer 710 may be smaller than the thicknesses of the adhesive patterns 741 and 742 (eg, the thickness A5 of the conductive adhesive pattern 741 ). Since the thickness A1 of the first thermal conduction layer 710 is small, the heat generated from the first semiconductor package 100 can be transferred to the heat dissipation structure 600 more quickly through the first thermal conduction layer 710 .

FIG. 2C is a plan view illustrating a packaging system according to an exemplary embodiment. 2D is a cross-sectional view taken along line I-II shown in FIG. 2C. Hereinafter, content overlapping the above-mentioned content will be omitted.

2C and 2D, the packaging system 1c includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200 and a third semiconductor package 300, a first passive element 400, a first thermally conductive layer 710, a second thermally conductive layer 720 and The third heat conduction layer 730 and the heat dissipation structure 600 . The heat dissipation structure 600 may include the second heat dissipation structure 620 described with reference to FIGS. 2A and 2B . For example, the second heat dissipation structure 620 may include a body portion 621 and a leg portion 622 .

A conductive adhesive pattern 741 may be disposed between the ground pad 510G and the leg portion 622 of the second heat dissipation structure 620 to connect with the second heat dissipation structure 620 and the ground pad 510G. Unlike the example shown in FIGS. 2A and 2B , the insulating adhesive pattern 742 may not be provided. The thickness A1 of the first thermally conductive layer 710 may be smaller than the thickness A5 of the conductive adhesive pattern 741 .

The substrate 500 , the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 , the first passive element 400 and the first thermally conductive layer 710 , the second thermally conductive layer 720 and the third thermally conductive layer 730 may be the same as those described above with reference to FIG. 1A Substantially the same as described to Figure II.

FIG. 2E is a diagram illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 2C . Hereinafter, content overlapping the above-mentioned content will be omitted.

2C and 2E, the packaging system 1d includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200, a third semiconductor package 300, a first semiconductor package 100, The passive element 400 , the first thermal conduction layer 710 , the second thermal conduction layer 720 , the third thermal conduction layer 730 , and the heat dissipation structure 600 . The substrate 500 , the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 , the first passive element 400 and the first thermally conductive layer 710 , the second thermally conductive layer 720 and the third thermally conductive layer 730 may be the same as those described above with reference to FIG. 1A Substantially the same as described to Figure 1E.

The heat dissipation structure 600 may include a first heat dissipation structure 610 , a second heat dissipation structure 620 and a heat dissipation layer 630 . The first heat dissipation structure 610 may be substantially the same as that described above with reference to FIGS. 1A-1C . However, the first heat dissipation structure 610 may be disposed on the upper surface of the second heat dissipation structure 620 . The second heat dissipation structure 620 may be substantially the same as the second heat dissipation structure 620 described with reference to FIGS. 2A to 2D . For example, the second heat dissipation structure 620 may include a body portion 621 and a leg portion 622 . The width of the first heat dissipation structure 610 may be equal to or wider than the width of the second heat dissipation structure 620 . The conductive adhesive pattern 741 may be disposed between the ground pad 510G and the second heat dissipation structure 620 . As another example, an insulating adhesive pattern 742 as described in the example shown in FIGS. 2A and 2B may be further provided. The heat dissipation layer 630 may be interposed between the first heat dissipation structure 610 and the second heat dissipation structure 620 . The heat dissipation layer 630 may include, for example, a thermal interface material.

3A is a cross-sectional view illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 2A . Hereinafter, content overlapping the above-mentioned content will be omitted.

2C and 3A, the packaging system 1e includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200 and a third semiconductor package 300, a first passive element 400, a first thermally conductive layer 710, a second thermally conductive layer 720 and third heat transfer The conductive layer 730 and the heat dissipation structure 600 .

In addition to the first substrate 110 , the first semiconductor chip 120 and the first molding layer 130 , the first semiconductor package 100 also includes a first adhesive layer 141 and a first thermally conductive structure 140 . The first thermally conductive structure 140 may have a relatively high thermal conductivity. The first thermally conductive structure 140 may include the thermally conductive materials described in the examples shown in FIGS. 1A-1C . In one example, the first thermally conductive structure 140 may include a metal layer, a heat slot, or a heat pipe. As another example, the first thermally conductive structure 140 may use a water cooling method. The first adhesive layer 141 may be disposed between the first molding layer 130 and the first thermally conductive structure 140 . The first adhesive layer 141 may include a thermal interface material. During operation of the first semiconductor package 100 , heat generated from the first semiconductor wafer 120 may be transferred to the first thermally conductive layer 710 via the first adhesive layer 141 and the first thermally conductive structure 140 .

According to example embodiments, the upper surface of the first semiconductor package 100 may correspond to the upper surface of the first thermally conductive structure 140 . The height H1 of the mounted first semiconductor package 100 is defined as the height of the first connection terminal 150 , the height of the first substrate 110 , the height of the first molding layer 130 , the height of the first adhesive layer 141 and the first thermally conductive structure The sum of the heights of 140. Even if the upper surface of the first molding layer 130 is disposed at a lower level than the upper surface of the second semiconductor package 200 or the upper surface of the third semiconductor package 300, by providing the first adhesive layer 141 and the first thermally conductive structure 140 , the height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200 and the height H3 of the mounted third semiconductor package 300 . The thickness A1 of the first thermally conductive layer 710 may be smaller than the thickness A2 of the second thermally conductive layer 720 and the thickness A3 of the third thermally conductive layer 730 . Therefore, the thermal characteristics of the first semiconductor package 100 Sex can be improved.

The substrate 500 , the second semiconductor package 200 and the third semiconductor package 300 , the first passive element 400 , the first thermally conductive layer 710 , the second thermally conductive layer 720 and the third thermally conductive layer 730 , and the heat dissipation structure 600 can be similar to those shown in FIGS. 1A to 1A . IF and those described in Figures 2A-2E are substantially the same.

3B is a cross-sectional view illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 2C . Hereinafter, content overlapping the above-mentioned content will be omitted.

2C and 3B, the packaging system 1f includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200 and a third semiconductor package 300, a first passive element 400, a first thermally conductive layer 710, a second thermally conductive layer 720 and The third heat conduction layer 730 and the heat dissipation structure 600 . The substrate 500 , the first semiconductor package 100 , the first passive element 400 , the first thermally conductive layer 710 , the second thermally conductive layer 720 and the third thermally conductive layer 730 and the heat dissipation structure 600 may be substantially the same as those described above.

Besides the second substrate 210 , the second semiconductor chip 220 and the second molding layer 230 , the second semiconductor package 200 also includes a second adhesive layer 241 and a second thermally conductive structure 240 . The second thermally conductive structure 240 may include a thermally conductive material and may have a relatively high thermal conductivity. The second thermally conductive structure 240 may include a metal layer, a heat slot or a heat pipe. The second adhesive layer 241 may be disposed between the second molding layer 230 and the second thermally conductive structure 240 . The second adhesive layer 241 may include a thermal interface material. During operation of the second semiconductor package 200 , heat generated from the second semiconductor die 220 may be transferred to the second thermally conductive layer 720 via the second adhesive layer 241 and the second thermally conductive structure 240 .

The upper surface of the second semiconductor package 200 may correspond to the upper surface of the second thermally conductive structure 240 . The height H2 of the mounted second semiconductor package 200 is defined as the height of the second connection terminal 250 , the height of the second substrate 210 , the height of the second molding layer 230 , the height of the second adhesive layer 241 and the second heat conduction structure The sum of the heights of 240. The height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200 . Therefore, the thickness A1 of the first thermally conductive layer 710 may be smaller than the thickness A2 of the second thermally conductive layer 720 .

In addition to the third substrate 310 , the third semiconductor chip 320 and the third molding layer 330 , the third semiconductor package 300 also includes a third adhesive layer 341 and a third thermally conductive structure 340 . The third thermally conductive structure 340 may include a thermally conductive material and may have a relatively high thermal conductivity. The third thermally conductive structure 340 may include a metal layer, a heat slot or a heat pipe. The third adhesive layer 341 may be disposed between the third molding layer 330 and the third thermally conductive structure 340 . The third adhesive layer 341 may include a thermal interface material. During the operation of the third semiconductor package 300 , the heat generated from the third semiconductor die 320 may be transferred to the third thermally conductive layer 730 via the third adhesive layer 341 and the third thermally conductive structure 340 .

The upper surface of the third semiconductor package 300 may correspond to the upper surface of the third thermally conductive structure 340 . The height H3 of the mounted third semiconductor package 300 is defined as the height of the third connection terminal 350 , the height of the third substrate 310 , the height of the third molding layer 330 , the height of the third adhesive layer 341 and the third thermally conductive structure The sum of the heights of 340. The height H1 of the mounted first semiconductor package 100 may be greater than the height H3 of the mounted third semiconductor package 300 . Therefore, the thickness A1 of the first heat conduction layer 710 may be smaller than the thickness A3 of the third heat conduction layer 730 .

Different from what is shown, the second adhesive layer 241 and the second thermally conductive structure 240 are omitted, and as shown in FIG. 2D , the second thermally conductive layer 720 may directly contact the upper surface of the second molding layer 230 . As another example, the third adhesive layer 341 and the third thermally conductive structure 340 are omitted, and the third thermally conductive layer 730 may directly contact the upper surface of the third molding layer 330 .

3C is a cross-sectional view illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 2C . Hereinafter, content overlapping the above-mentioned content will be omitted.

2C and 3C , the packaging system 1g includes a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 and a third semiconductor package 300 , a first passive element 400 , a first thermally conductive layer 710 , a second thermally conductive layer 720 and The third heat conduction layer 730 and the heat dissipation structure 600 . The substrate 500 , the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 , the first passive element 400 , the first thermal conduction layer 710 , the second thermal conduction layer 720 and the third thermal conduction layer 730 , and the heat dissipation structure 600 and above Said are substantially the same.

The first semiconductor package 100 may be substantially the same as that described in the example shown in FIG. 3A. For example, the first semiconductor package 100 includes a first substrate 110 , a first semiconductor chip 120 , a first molding layer 130 , a first adhesive layer 141 and a first thermally conductive structure 140 . The second semiconductor package 200 and the third semiconductor package 300, respectively, may be substantially the same as those described in the example shown in FIG. 3B. The second semiconductor package 200 includes a second substrate 210 , a second semiconductor chip 220 , a second molding layer 230 , a second adhesive layer 241 and a second thermally conductive structure 240 . The third semiconductor package 300 includes a third substrate 310, The third semiconductor wafer 320 , the third molding layer 330 , the third adhesive layer 341 and the third thermally conductive structure 340 .

The height H1 of the mounted first semiconductor package 100 may be greater than the height H2 of the mounted second semiconductor package 200 and the height H3 of the mounted third semiconductor package 300 . The thickness A1 of the first thermally conductive layer 710 may be smaller than the thickness A2 of the second thermally conductive layer 720 and the thickness A3 of the third thermally conductive layer 730 .

4A is a cross-sectional view illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 2C . 4B is a cross-sectional view illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 2C . Hereinafter, content overlapping the above-mentioned content will be omitted.

2C, 4A and 4B, the packaging system 1h or 1i includes a substrate 500, a first semiconductor package 100, a second semiconductor package 200 and a third semiconductor package 300, a first passive element 400, a first thermally conductive layer 710, and a heat sink Structure 600. The substrate 500 , the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 , the first passive element 400 , the first thermally conductive layer 710 and the heat dissipation structure 600 are substantially the same as those described above.

As shown in FIG. 4A , the packaging system 1 h may not include the second thermally conductive layer 720 . The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first thermal conduction layer 710 may be greater than the height H2 of the mounted second semiconductor package 200 .

As shown in FIG. 4B , the packaging system 1i may not include the third thermally conductive layer 730 . The sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first thermal conduction layer 710 may be greater than the height H3 of the mounted third semiconductor package 300 .

4C is a cross-sectional view illustrating a packaging system according to an exemplary embodiment, which corresponds to a cross-section taken along line I-II shown in FIG. 2C. Hereinafter, content overlapping the above-mentioned content will be omitted.

2C and 4C , the packaging system 1j includes a substrate 500 , a first semiconductor package 100 , a second semiconductor package 200 and a third semiconductor package 300 , a first passive element 400 , a first thermally conductive layer 710 , a second thermally conductive layer 720 and The third heat conduction layer 730 and the heat dissipation structure 600 . The thickness A1 of the first thermally conductive layer 710 may be smaller than the thickness A2 of the second thermally conductive layer 720 and the thickness A3 of the third thermally conductive layer 730 .

A fourth heat conduction layer 740 is disposed between the first passive element 400 and the heat dissipation structure 600 , so that the fourth heat conduction layer 740 can physically contact the upper surface of the first passive element 400 and the lower surface 600b of the heat dissipation structure 600 . The fourth thermally conductive layer 740 may include a thermal interface material. The heat generated from the first passive element 400 may be transferred to the heat dissipation structure 600 through the fourth thermal conduction layer 740 . The height H1 of the mounted first semiconductor package 100 may be greater than the height H4 of the mounted first passive element 400 . For example, the upper surface of the first semiconductor package 100 may be disposed at a higher level than the upper surface of the first passive element 400 . Therefore, the thickness A1 of the first thermally conductive layer 710 may be smaller than the thickness A4 of the fourth thermally conductive layer 740 .

As another example, the second thermally conductive layer 720 or the third thermally conductive layer 730 may be omitted.

In the descriptions shown in FIGS. 3A to 3C and FIGS. 4A to 4C , the first heat dissipation structure 610 or the second heat dissipation structure 620 may be omitted. In this case, the heat dissipation layer 630 may not be provided.

In the illustration shown in FIGS. 4A to 4C , the first semiconductor package 100 may further include a first adhesive layer 141 and a first thermally conductive structure 140 . The second semiconductor package 200 may further include a second adhesive layer 241 and a second thermally conductive structure 240 . The third semiconductor package 300 may further include a third adhesive layer 341 and a third thermally conductive structure 340 .

FIG. 5A is a cross-sectional view illustrating a semiconductor module according to an exemplary embodiment. FIG. 5B is a diagram for explaining a second passive element according to an exemplary embodiment, and is a cross-sectional view showing an enlarged view of a region C shown in FIG. 5A . FIG. 5C is a diagram for explaining lower pads and conductive terminals according to an exemplary embodiment, and shows an enlarged region VI shown in FIG. 5A . FIG. 5D is a diagram for explaining a lower pad according to an exemplary embodiment. Hereinafter, content overlapping the above-mentioned content will be omitted.

Referring to FIGS. 1A , 5A and 5B , a semiconductor module 10 may include a board 1000 and a packaging system 1 . For example, a printed circuit board can be used as the board 1000 . Conductive pads 1500 may be disposed on the upper surface 1000a of the board 1000 . The conductive pads 1500 may be electrically connected to internal wires (not shown in the figure) of the board 1000 . In this specification, being electrically connected with the board 1000 may mean being electrically connected with the internal wires of the board 1000 .

The packaging system 1 described with reference to FIGS. 1A to 1C may be mounted on a board 1000 so that a semiconductor module 10 may be formed. As another example, the packaging system 1a shown in FIG. 1F, the packaging system 1b shown in FIGS. 2A and 2B, the packaging system 1c shown in FIGS. 2C and 2D, the packaging system 1d shown in FIG. 2E, and the packaging system 1e shown in FIG. 3A , the package system 1f shown in FIG. 3B, the package system 1g shown in FIG. 3C, the package system 1h shown in FIG. 4A, the package system 1i shown in FIG. 4B, or the package system 1j shown in FIG. The semiconductor module 10 . For convenience, Figures 1A to 1C show The packaging system 1 is shown and described with respect to the semiconductor module 10 mounted on the board 1000, but the inventive concept is not limited thereto.

Packaging the package system 1 includes disposing the package system 1 on the board 1000 in such a manner that the conductive terminals 550 face the board 1000 and electrically connecting the conductive terminals 550 to the conductive pads 1500 . The pitch of the conductive terminals 550 may be substantially the same as the pitch P4 of the conductive pads 1500 . The pitch P4 of the conductive pads 1500 may be standardized. For example, the pitch P4 of the conductive pads 1500 can meet the Joint Electron Device Engineering Council (JEDEC) standard. The pitch P4 of the conductive pads 1500 may be large. For example, the pitch P4 of the conductive pads 1500 may be 0.65 millimeters (mm) or greater.

When the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 are directly mounted on the board 1000 , the pitch P1 of the first connection terminal 150 , the pitch P2 of the second connection terminal 250 and the third connection terminal Each of the pitches P3 of 350 may need to be substantially the same as the pitch P4 of the conductive pads 1500 . According to exemplary embodiments, the first semiconductor package 100 , the second semiconductor package 200 , and the third semiconductor package 300 may be connected to the board 1000 via the substrate 500 . Therefore, the pitch P1 of the first connection terminal 150 , the pitch P2 of the second connection terminal 250 and the pitch P3 of the third connection terminal 350 are freely designed without being restricted by the pitch P4 of the conductive pads 1500 .

The pitch P1 of the first connection terminals 150 may be smaller than the pitch P4 of the conductive pads 1500 . For example, the pitch P1 of the first connection terminals 150 may be 0.4 mm or less. Therefore, the first connection terminals 150 are more closely arranged so that the first The planar area of the semiconductor package 100 can be reduced. The pitch P2 of the second connection terminals 250 and the pitch P3 of the third connection terminals 350 may be smaller than the pitch P4 of the conductive pads 1500 . For example, each of the pitch P2 of the second connection terminals 250 and the pitch P3 of the third connection terminals 350 may be 0.4 mm or less. Therefore, the second semiconductor package 200 and the third semiconductor package 300 can be miniaturized. Since the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 are miniaturized, the distance between the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 can be reduced. Therefore, the length of the electrical signal paths between the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 can be reduced. The operating speed and reliability of the packaging system 1 can be improved.

The second passive element 420 may be mounted on the lower surface 1000b of the board 1000 . As shown in FIG. 5B , a second connection terminal portion 402 may be further provided between the board 1000 and the second passive element 420 . The second passive element 420 may be connected to the board 1000 via the second connection terminal portion 402 . The second connection terminal portion 402 may include, for example, solder balls, posts, bumps, or ball grid arrays. The height H6 of the mounted second passive element 420 may be defined as including the height H61 of the second connection terminal portion 402 . For example, the height H6 of the mounted second passive element 420 is equal to the sum of the height H61 of the second connection terminal portion 402 and the height H60 of the second passive element 420 ′ before being mounted. For example, the height H6 of the mounted second passive element 420 may be greater than the sum of the height H1 of the mounted first semiconductor package 100 and the thickness A1 of the first thermally conductive layer 710 . Even if the height H6 of the mounted second passive element 420 is large, the second passive element 420 can still be electrically connected to the packaging system 1 through the substrate 500 .

The second passive element 420 may be electrically connected to one of the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 . In plan view, the second passive element 420 may be disposed to overlap or be adjacent to the one of the first semiconductor package 100 , the second semiconductor package 200 , and the third semiconductor package 300 . Therefore, the signal length between the second passive element 420 and the one of the semiconductor packages 100, 200 and 300 can be reduced. Therefore, the electrical characteristics of the semiconductor module 10 can be improved.

A plurality of second passive elements 420 may be provided. In this case, the heights H6 of the second passive elements 420 may be equal to or different from each other. Various modifications can be made to the number of second passive elements 420 . Hereinafter, referring to FIGS. 5C and 5D , the conductive terminals 550 and the lower pads 540 will be explained.

The lower pads 540 may be disposed on the lower surface of the substrate 500 . The lower pads 540 may include connection pads 541 and test pads 542 . The electrical characteristics of the packaging system 1 may be evaluated during the manufacturing process of the packaging system 1 or before the packaging system 1 is mounted on the board 1000 . Evaluation of electrical characteristics may be performed using test pads 542 . For example, when the probes (not shown in the figure) contact the test pads 542 , the first semiconductor package 100 , the second semiconductor package 200 and the third semiconductor package 300 , the first passive device 400 and the electronic device 430 At least one of electrical properties and connection relationships can be evaluated. Thereafter, the conductive terminals 550 are formed, and the package system 1 can be mounted on the board 1000 .

As shown in FIG. 5C , the conductive terminal 550 may include a first terminal 551 and a second terminal 552 exposed by the lower surface of the substrate 500 . The first terminal 551 is connected to The lower surface of the pads 541 is connectable to a corresponding one of the connection pads 541 and the conductive pads 1500 . The first terminals 551 can electrically connect the packaging system 1 to the board 1000 . The first terminal 551 can serve as a signal transmission path.

The second terminal 552 is disposed on the lower surface of the test pad 542 and can be connected to the test pad 542 . For example, the second terminal 552 may serve as a ground terminal. The ground voltage is transmitted to the packaging system 1 via the board 1000 and the second terminal 552 . As another example, the second terminal 552 may be a dummy terminal. For example, the second terminals 552 may not be electrically connected to internal wires in the board 1000 . Alternatively, the second terminal 552 may not be electrically connected to the packaging system 1 .

As shown in Figure 5D, the second terminal (552 in Figure 5C) may not be provided. The test pads 542 may be spaced apart and electrically insulated from the board 1000 . Although not shown in the drawings, the gaps between the board 1000 and the test pads 542 may be filled with an underfill material. The underfill material may include an insulating polymer.

According to the inventive concept, the first semiconductor package may generate a large amount of heat during operation of the packaging system. The thickness of the first heat conduction layer may be smaller than the thickness of the second heat conduction layer and the thickness of the third heat conduction layer. As the thickness of the first thermally conductive layer is reduced, thermal characteristics of the first semiconductor package may be improved. The packaged system may exhibit improved operating characteristics.

While some exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these embodiments, but rather may be within the spirit and scope of the inventive concept as set forth below by one of ordinary skill in the art Make various changes and retouches.

1: Packaging system

100: Semiconductor Package/First Semiconductor Package

200: Semiconductor Packaging/Second Semiconductor Packaging

300: Semiconductor Packaging/Third Semiconductor Packaging

400: First Passive Component/Installed First Passive Component

430: Electronic Components/Mounted Electronic Components

500: Substrate

590: Dam Structure

600: heat dissipation structure

610: The first heat dissipation structure

I-II: Line

III: District

Claims (21)

A semiconductor packaging system, comprising: a substrate; a first semiconductor package located on the substrate; a second semiconductor package located on the substrate; a third semiconductor package located on the substrate; a first passive element located on the substrate on the substrate; a dam structure arranged between the third semiconductor package and the first passive element; a heat dissipation structure located on the first semiconductor package, the second semiconductor package and the first passive element and a first thermally conductive layer, located between the first semiconductor package and the heat dissipation structure, the sum of the height of the first semiconductor package and the thickness of the first thermally conductive layer is greater than the height of the first passive element , the height of the first passive element is greater than the height of the dam structure, and the height of the first semiconductor package is greater than the height of the second semiconductor package. The semiconductor packaging system according to claim 1, further comprising: a second heat conduction layer disposed between the second semiconductor package and the heat dissipation structure, wherein The thickness of the first thermally conductive layer is smaller than the thickness of the second thermally conductive layer. The semiconductor packaging system of claim 2, wherein the first thermally conductive layer and the second thermally conductive layer physically contact the heat dissipation structure. The semiconductor packaging system of claim 1, wherein the first semiconductor package includes a first substrate, a first semiconductor die, and a first mold layer, and the first semiconductor die is a system die. The semiconductor packaging system of claim 4, wherein the first semiconductor package further comprises a first thermally conductive structure on the first molding layer. The semiconductor packaging system of claim 5, wherein the upper surface of the first molding layer is located at a lower level than the upper surface of the second semiconductor package. The semiconductor packaging system of claim 1, wherein the second semiconductor package includes a second substrate, a second semiconductor die, a second mold layer, and a second thermally conductive layer on the second mold layer structure. The semiconductor packaging system of claim 1, further comprising: a ground pattern on the upper surface of the substrate; and a conductive adhesive pattern between the ground pattern and the heat dissipation structure, wherein the The heat dissipation structure includes a body part and a leg part, The body portion extends parallel to the upper surface of the base plate, the leg portion is connected to the body portion, the leg portion is located between the base plate and the body portion, and the heat dissipation structure passes through The conductive adhesive pattern is electrically connected to the ground pattern. The semiconductor packaging system of claim 8, wherein a thickness of the first thermally conductive layer is smaller than a thickness of the conductive adhesive pattern. The semiconductor packaging system of claim 1, further comprising: a board located on the lower surface of the substrate; conductive terminals connected to the substrate and the board; and a second passive element located on the substrate on the lower surface of the board, wherein the height of the second passive element is greater than the height of the first semiconductor package. The semiconductor packaging system of claim 10, further comprising: a first connection terminal located between the substrate and the first semiconductor package, wherein the pitch of the first connection terminal is smaller than that of the conductive Terminal pitch. A semiconductor packaging system, comprising: a substrate; a first semiconductor package located on an upper surface of the substrate, the first semiconductor package The bulk package includes a first semiconductor die including one or more logic circuits; a second semiconductor package on the upper surface of the substrate; and a third semiconductor package on the upper surface of the substrate on the upper surface; a passive element on the upper surface of the substrate; a dam structure on the upper surface of the substrate and disposed between the third semiconductor package and the passive element; heat dissipation a structure on the first semiconductor package, the second semiconductor package and the passive element; and a plurality of thermally conductive layers each physically contacting the lower surface of the heat dissipation structure, the plurality of thermally conductive layers including a first heat conduction layer on the upper surface of the first semiconductor package, and the first heat conduction layer has the thinnest thickness among the plurality of heat conduction layers, and the height of the passive element is greater than the height of the dam structure . The semiconductor packaging system of claim 12, wherein a height of the first semiconductor package is greater than a height of the second semiconductor package. The semiconductor packaging system of claim 13, wherein the first semiconductor package further comprises a first substrate, a first molding layer and a first thermally conductive structure, and the first semiconductor chip is located on the first substrate above, the first mold layer is configured to cover the first semiconductor wafer, and the first thermally conductive structure is located on the first mold layer. The semiconductor packaging system of claim 12, wherein the sum of the height of the first semiconductor package and the thickness of the first thermally conductive layer is greater than the height of the passive element. The semiconductor packaging system of claim 12, wherein the plurality of thermally conductive layers further comprises a second thermally conductive layer on an upper surface of the second semiconductor package. The semiconductor packaging system of claim 16, wherein the second semiconductor package comprises a power management chip or a memory chip. A semiconductor packaging system, comprising: a substrate; a first semiconductor package on the substrate, the first semiconductor package comprising a first semiconductor die, the first semiconductor die comprising one or more logic circuits; a second semiconductor package , located on the substrate; a third semiconductor package, located on the substrate; a passive element, located on the substrate; a dam structure, located between the third semiconductor package and the passive element; a heat dissipation structure, on the first semiconductor package, the second semiconductor package and the passive element; a first thermally conductive layer on the first semiconductor package, the first thermally conductive layer physically contacting the heat dissipation structure; and a second heat conduction layer on the second semiconductor package, the second heat conduction layer The conductive layer physically contacts the heat dissipation structure, the thickness of the first thermal conductive layer is smaller than the thickness of the second thermal conductive layer, and the upper surface of the first thermal conductive layer is disposed higher than the upper surface of the passive element. at the horizontal height. The semiconductor packaging system of claim 18, further comprising: a third thermally conductive layer on the third semiconductor package, wherein the third thermally conductive layer physically contacts the heat dissipation structure, and the first thermally conductive layer The thickness of a thermally conductive layer is smaller than the thickness of the third thermally conductive layer. The semiconductor packaging system of claim 18, wherein the second semiconductor package includes a second substrate, a second semiconductor die, and a second mold layer, and the second semiconductor die is connected to the first Semiconductor wafers Different types of semiconductor wafers. The semiconductor packaging system of claim 20, wherein the second semiconductor package further comprises a second thermally conductive structure on the second molding layer, and the second thermally conductive layer is located on the second thermally conductive structure.

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