CN107611043A - A kind of fan-out package method - Google Patents
A kind of fan-out package method Download PDFInfo
- Publication number
- CN107611043A CN107611043A CN201710740477.7A CN201710740477A CN107611043A CN 107611043 A CN107611043 A CN 107611043A CN 201710740477 A CN201710740477 A CN 201710740477A CN 107611043 A CN107611043 A CN 107611043A
- Authority
- CN
- China
- Prior art keywords
- layer
- wiring layer
- silicon wafer
- basic unit
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a kind of fan-out package method, methods described includes：Package substrate is provided, the package substrate includes Silicon Wafer basic unit, pad and the first wiring layer again, and the pad is arranged at Silicon Wafer basic unit side, described first again wiring layer be arranged at the opposite side of the Silicon Wafer basic unit, wherein, the pad and the described first wiring layer electrical connection again；Chip is electrically connected with the pad of the package substrate.By the above-mentioned means, the present invention can prevent chip from shifting, while make again the line width of wiring layer and line-spacing narrower.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of fan-out package method.
Background technology
With the development of semiconductor technology, the size of chip is less and less, I/O (input/output) pin of chip surface
Density also arise at the historic moment by more and more higher, fan-out package, and the highdensity I/O pins of chip are fanned out to as low-density by fan-out package
Packaging pin.
At present, existing fan-out package method includes following flow：Support plate is provided, one layer of double faced adhesive tape is attached on support plate
Film, the front of chip is attached on glued membrane, after chip is carried out into plastic packaging, peels off glued membrane and support plate, formed in the front of chip
Wiring layer, plant ball, cutting again.
The present inventor has found in chronic study procedure, as a result of glue in above-mentioned fan-out package method
Film, in chip plastic packaging, temperature change causes glued membrane when occurring flexible, plastic packaging due to the thermal expansion of capsulation material, chip and support plate
Situations such as warpage occurs for coefficient (CTE) difference, causes chip to produce skew in plastic packaging.The skew of chip causes successive process such as
Photoetching contraposition occurs difficult.；In addition, with above-mentioned fan-out package method prepare wiring layer again on narrow linewidth/line-spacing all by
To a definite limitation.
The content of the invention
The present invention solves the technical problem of a kind of fan-out package method is provided, it is inclined can to prevent that chip from occurring
Move；Simultaneously the line width of wiring layer and line-spacing can be made again narrower.
In order to solve the above technical problems, one aspect of the present invention is：A kind of fan-out package method is provided,
Methods described includes：Package substrate is provided, the package substrate includes Silicon Wafer basic unit, pad and the first wiring layer again, described
Pad is arranged at Silicon Wafer basic unit side, described first again wiring layer be arranged at the opposite side of the Silicon Wafer basic unit, its
In, the pad and the described first wiring layer electrical connection again；Chip is electrically connected with the pad of the package substrate.
The beneficial effects of the invention are as follows：It is different from the situation of prior art, fan-out package method of the present invention
In package substrate include Silicon Wafer basic unit, pad and the first wiring layer again, pad and first again wiring layer be located at silicon wafer respectively
The both sides of physa layer, pad with first again wiring layer electrically connect, chip electrically connects with pad；On the one hand, package substrate includes weldering
Disk, chip electrically connect with the pad of package substrate, so as to avoid chip temperature in plastic packaging caused by the method for packing using glued membrane
Stuck up when spending flexible glued membrane caused by changing, plastic packaging because the thermal coefficient of expansion (CTE) of capsulation material, chip and support plate is different
Situations such as bent, chip is caused to produce the situation of skew in plastic packaging；On the other hand, package substrate includes Silicon Wafer basic unit, silicon wafer
The thermal conductivity of physa layer is preferable, so as to be advantageous to the radiating of fan-out package device；Another further aspect, the pad of package substrate and
Wiring layer is located at the opposite sides of Silicon Wafer basic unit again and again, is carried subsequently to provide the two-sided fan-out package structure for having ball structure
For technical support；Another aspect, fan-shaped method for packing provided by the present invention are being made on wiring layer again again first to do again wiring layer
Standby chip, the line width and line-spacing of the wiring layer again for the method that this method is connected up again on chip again than first doing chip are narrower.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the embodiment of fan-out package method one of the present invention；
Fig. 2 is the top view of the embodiment of field of semiconductor package wafer one；
Fig. 3 is the structural representation that Silicon Wafer basic unit sets the embodiment of silicon hole one；
Fig. 4 is the schematic flow sheet of the embodiment of fan-out package method one of the present invention；
Fig. 5 is the structural representation of the embodiment of fan-out package device one corresponding to step S201-S206 in Fig. 4；
Fig. 6 is the structural representation of the embodiment of fan-out package device one corresponding to step S207-S217 in Fig. 4；
Fig. 7 is the structural representation of another embodiment of fan-out package device corresponding to step S207 in Fig. 4；
Fig. 8 is the structural representation of another embodiment of fan-out package device corresponding to step S217 in Fig. 4；
Fig. 9 is the schematic flow sheet of another embodiment of fan-out package method of the present invention；
Figure 10 is the structural representation of the embodiment of fan-out package device one corresponding to step S301-S309 in Fig. 9；
Figure 11 is the structural representation of another embodiment of fan-out package device corresponding to step S307 in Fig. 9；
Figure 12 is the schematic flow sheet of another embodiment of fan-out package method of the present invention；
Figure 13 is the structural representation of the embodiment of fan-out package device one corresponding to step S407-S422 in Figure 12；
Figure 14 is the structural representation of another embodiment of fan-out package device corresponding to step S412 in Figure 12；
Figure 15 is the structural representation of another embodiment of fan-out package device corresponding to step S422 in Figure 12；
Figure 16 is the schematic flow sheet of another embodiment of fan-out package method of the present invention；
Figure 17 is the structural representation of the embodiment of fan-out package device one corresponding to step S507-S519 in Figure 16；
Figure 18 is the structural representation of the embodiment of fan-out package device one of the present invention；
Figure 19 is the structural representation of another embodiment of fan-out package device of the present invention；
Figure 20 is the structural representation of another embodiment of fan-out package device of the present invention；
Figure 21 is the structural representation of another embodiment of fan-out package device of the present invention.
Embodiment
Referring to Fig. 1, Fig. 1 is the schematic flow sheet of the embodiment of fan-out package method one of the present invention, this method includes：
S101：Package substrate is provided, wiring layer, pad are set package substrate again including Silicon Wafer basic unit, pad and first
In Silicon Wafer basic unit side, first again wiring layer be arranged at the opposite side of Silicon Wafer basic unit, wherein, pad and the first wiring layer again
Electrical connection.
In an application scenarios, Silicon Wafer basic unit can be provided directly with pad, as shown in Fig. 2 Fig. 2 is semiconductor package
The top view of the embodiment of dress field wafer one.The wafer 10 includes basic unit 120 and pad 100, and basic unit 120 is provided with front and the back of the body
Face, pad 100 are formed at the front of basic unit 120, relatively, follow-up first again wiring layer be formed at the back side of basic unit 120；At this
In embodiment, the material of basic unit 120 is silicon, because the thermal conductivity of silicon is preferable, therefore can strengthen follow-up fan-out package device
Heat dispersion.
Specifically, above-mentioned steps S101 includes：Silicon Wafer basic unit provided with pad is provided, that is, provided such as the wafer in Fig. 2
10；Form the first wiring layer again of wiring layer, second again respectively in the both sides that Silicon Wafer basic unit is oppositely arranged, the second wiring layer shape again
Into on pad and electrical connection pad, i.e., the second cloth again is formed on the positive pad 100 of basic unit 120 as shown in Figure 2
Line layer, the first wiring layer again is formed at the back side of basic unit 120.
Due to Silicon Wafer basic unit, electric conductivity itself is poor, therefore to reach pad and the first mesh that wiring layer electrically connects again
, in one embodiment, include setting the state of Silicon Wafer basic unit to make it have weldering before formation first again wiring layer
The side of disk is located at lower section；Silicon hole is formed in the position back to pad of Silicon Wafer basic unit.Referring to Fig. 3, Silicon Wafer basic unit
20 have face-down, pair using the mode of plasma etching in Silicon Wafer basic unit 20 back to the side of pad 22 of pad 22
Answer the position of pad 22 to form silicon hole 24, in other embodiments, also other modes can be used to form silicon hole or using it
His mode by pad with first again wiring layer electrically connect；In an application scenarios, side a and the Silicon Wafer basic unit of silicon hole 24
Angle between a 20 side b is 60-80 ° (for example, 60 °, 70 °, 80 ° etc.), and the depth-to-width ratio of silicon hole 24 is less than 10:1, i.e.,
H/d ＜ 10 (for example, h/d=0.5,2,5,8,9 etc.).
S102：Chip is electrically connected with the pad of package substrate.
Specifically, when on the positive pad of Silicon Wafer basic unit formed with the second wiring layer again, above-mentioned steps S102 tools
Body is：By chip with second again wiring layer electrically connect, and by second again wiring layer electrically connected with pad；In an application scenarios
In, metal salient point is provided with chip, chip and again by way of wiring layer reflow soldering, are realized metal salient point and second
Two again wiring layer electrically connect, which can be avoided during follow-up chip plastic packaging due to glued membrane core caused by by thermal softening etc.
The situation that piece position shifts.
Below, will be described in further detail with several specific embodiments with regard to above-mentioned method for packing.
In one embodiment, referring to Fig. 4, Fig. 4 is the flow of the embodiment of fan-out package method one of the present invention
Schematic diagram；This method includes：
S201：The Silicon Wafer basic unit for being provided with pad is provided；Specifically, incorporated by reference to Fig. 5 a, in an application scenarios, envelope
Dress substrate includes being provided directly with the Silicon Wafer basic unit 30 of pad 32, i.e., the wafer that general Feng Ce factories can directly take；
S202：The side that pad is provided with Silicon Wafer basic unit forms the first passivation layer, and in the corresponding weldering of the first passivation layer
The position of disk sets the first opening；Specifically, incorporated by reference to Fig. 5 b, in one embodiment, first in Silicon Wafer basic unit 30
Surface coats one layer of first passivation layer 34, and the first passivation layer 34 then is corresponded into pad 32 by exposure imaging or other means
Position formed first opening 340 so that pad 32 exposes；In another embodiment, in the first passivation layer 34 back to silicon
The surface of wafer basic unit 30 can also form a dielectric layer (not shown), and the position that pad 34 is corresponded on dielectric layer is also equipped with being open
(not shown), to cause pad 32 to expose.
S203：In the first passivation layer the first Seed Layer is formed back to the surface of Silicon Wafer basic unit；Specifically, incorporated by reference to figure
5c, in one embodiment, the material of the first Seed Layer 36 is titanium, aluminium, copper, gold, silver one or more of mixing therein
Thing, the technique for forming the first Seed Layer 36 is sputtering technology or physical gas-phase deposition.
S204：The first mask layer is formed back to the surface of Silicon Wafer basic unit in the first Seed Layer, and in the first mask layer pair
Answer the position of pad that the second opening is set；Specifically, incorporated by reference to Fig. 5 d, the material of the first mask layer 38 is photoresist, silica,
Silicon nitride, amorphous carbon one or more therein, in the present embodiment, the material of the first mask layer 38 is photoresist, is utilized
Photoetching process forms the second opening 380 through the first mask layer 38 in the first mask layer 38, and the second opening 380 is located at pad
32 tops.
S205：The second wiring layer again is formed in the second opening；Specifically, Fig. 5 e are referred to, in one embodiment, profit
The second wiring layer 31 again are formed in the second opening 380 with electroplating technology, and the material of the second wiring layer 31 again is copper or other conjunctions
Suitable metal.In the present embodiment second again wiring layer 31 height less than second opening 380 depth, in other embodiment party
In formula second again wiring layer 31 height can also with second opening 380 depth it is identical.
S206：Remove the first mask layer and second the first Seed Layer beyond wiring layer again；Specifically, figure is referred to
5f, in one embodiment, the first mask layer 38 is removed using photoetching process, exposes the first Seed Layer of part 36；So
The first Seed Layer of part 36 exposed is removed using wet-etching technology or dry etch process afterwards, is only retained positioned at second again
First Seed Layer 36 of the lower section of wiring layer 31；Wherein, wiring layer 31 electrically connects again for pad 32, the first Seed Layer 36, second；
S207：Chip is electrically connected with the pad of package substrate；Specifically, in an application scenarios, as shown in Figure 6 a,
The surface of chip 40 is provided with metal salient point 400, by the reflow soldering of wiring layer 31 again of metal salient point 400 and second of chip 40, with
So that chip 40 with second again wiring layer 31 electrically connect, and by second again wiring layer 31 electrically connected with pad 32；At another
In application scenarios, step S207 specifically also includes：Passivation layer 50 is formed on wiring layer 31 again second, and is set on passivation layer 50
Opening 500 (as shown in Figure 7a) is put, the surface of chip 52 is provided with metal salient point 520, by the metal salient point 520 of chip 52 with passing through
Opening 500 and second reflow soldering of wiring layer 31 again, with cause chip 52 with second again wiring layer 31 electrically connect, and pass through second
Wiring layer 31 electrically connects (shown in Fig. 7 b) with pad 32 again；In above-mentioned two embodiment, chip 40 or 52 by the way of upside-down mounting,
In other embodiments, chip 40 or 52 can also take the mode of formal dress, and this is not limited by the present invention.
S208：By the formation of chip and Silicon Wafer basic unit have second again wiring layer side carry out plastic packaging；Specifically, reference can be made to
Fig. 6 b；In one embodiment, there is the face filling liquid or powdered form resin of pad 32 in Silicon Wafer basic unit 30, make
Wiring layer 31 is all covered in resin material chip 40 and second again, and plastic packaging layer 42 is formed after solidification.
S209：Silicon Wafer basic unit is ground back to the side of pad, make it that it is pre- that the thickness of Silicon Wafer basic unit is less than or equal to
Determine thickness；Specifically, Fig. 6 c are referred to, in an application scenarios, the Silicon Wafer for the wafer typically directly taken from Feng Ce factories
The thickness of basic unit 30 is larger, therefore in the present embodiment, it is necessary to which the side back to pad 32 of Silicon Wafer basic unit 30 is ground
Mill, to cause its thickness to be less than or equal to predetermined thickness, such as predetermined thickness is 100um, the thickness of Silicon Wafer basic unit 30 after grinding
For 50,60,80um etc..
S210：The side that the state of setting Silicon Wafer basic unit makes it have pad is located at lower section, in the back of the body of Silicon Wafer basic unit
Silicon hole is formed to the position of pad；Specifically, reference can be made to Fig. 6 d, form in mode above-described embodiment of silicon hole 44 and carried
And it will not be repeated here.
S211：The 3rd mask layer is formed back to the side of pad in Silicon Wafer basic unit, and pad is corresponded in the 3rd mask layer
Position formed the 6th opening；Specifically, Fig. 6 e are referred to, the material of the 3rd mask layer 46 is photoresist, silica, nitridation
Silicon, amorphous carbon one or more therein, in the present embodiment, the material of the 3rd mask layer 46 is photoresist, utilizes photoetching
Technique forms the 6th opening 460 through the 3rd mask layer 46 in the 3rd mask layer 46, to cause pad 32 to expose.
S212：In the 3rd mask layer the third sublayer is formed back to the surface of Silicon Wafer basic unit；Specifically, figure is referred to
6f, in one embodiment, the material of the third sublayer 41 is titanium, aluminium, copper, gold, silver one or more of mixing therein
Thing, the technique for forming the third sublayer 41 are sputtering technology or physical gas-phase deposition.
S213:The 4th mask layer is formed back to the surface of Silicon Wafer basic unit in the third sublayer, and on the 4th mask layer
Form the 7th opening；Specifically, refer to Fig. 6 g, the material of the 4th mask layer 43 is photoresist, silica, silicon nitride, without fixed
Shape carbon one or more therein, in the present embodiment, the material of the 4th mask layer 43 is photoresist, using photoetching process
The 7th opening 430 through the 4th mask layer 43 is formed in four mask layers 43.
S214：The first wiring layer again is formed in the 7th opening；Specifically, Fig. 6 h are referred to, in one embodiment,
Form the first wiring layer 45 again in the 7th opening 430 using electroplating technology, first again wiring layer 45 material for copper or other
Metal.In Fig. 6 h first again wiring layer 45 fill up the 7th opening 430, in other embodiments, first wiring layer 45 also can be again
One layer is paved with 7th opening 430, its thickness can be designed according to actual conditions, and this is not limited by the present invention.
S215：Remove the 4th mask layer and first the third sublayer beyond wiring layer again；Specifically, the step with it is upper
It is similar to state S206, its structure can refer to Fig. 6 i, wherein, first wiring layer 45, the third sublayer 41 electrically connect with pad 32 again.
S216：First again wiring layer back to the surface of Silicon Wafer basic unit, the first barrier layer is set, and on the first barrier layer
It is upper to form the 8th opening；Specifically, Fig. 6 j are referred to, the material on the first barrier layer 47 has insulation characterisitic, in an embodiment party
In formula, the 8th opening 470 is formed on the first barrier layer 47 using the mode of photoetching or other etchings.
S217：Soldered ball is set；In an application scenarios, Fig. 6 k are referred to, directly can be set in the 8th opening 470
Put soldered ball, for example, using ball attachment machine the 8th be open 470 interplantation soldered balls 49, the material of soldered ball 49 is tin or tin alloy.Its
In, wiring layer 45 electrically connects soldered ball 49 and first again；In another application scenarios, Fig. 8 is referred to, can be connected up again first
The mode that ball lower metal layer is formed on layer 45 carries out plant ball；Specifically, the table on the first barrier layer 47 back to Silicon Wafer basic unit 30
Face forms the 4th Seed Layer 60 (as shown in Figure 8 a), and the 4th Seed Layer 60 can use the method for sputtering to be formed and be initially formed one layer of titanium
Layer, then sputter one layer of layers of copper on titanium layer and formed；The surface formation the 5th that 60 pairs of Silicon Wafer basic units 30 are carried on the back in the 4th Seed Layer is covered
Film layer 62, and the position of corresponding 8th opening 470 formed for the 9th 620 (as shown in Figure 8 b) of opening on the 5th mask layer 62；
Ball lower metal layers 64 (as shown in Figure 8 c) are formed in 9th opening 620, the material of ball lower metal layer 64 can be metallic copper, can be with
Formed by the way of plating；The 4th Seed Layer 60 corresponding to the 5th mask layer 62 and the lower section of the 5th mask layer 62 is removed (as schemed
Shown in 8d)；Soldered ball 66 is formed on the correspondence position of ball lower metal layer 64, soldered ball 66 can be fallen on by corresponding ball by ball attachment machine
The position of lower metal layer 64, then formed (as figure 8 e shows) by backflow；Wherein, soldered ball 66, ball lower metal layer 64, the 4th seed
Wiring layer 45 electrically connects layer 60, first again.
In the second embodiment, referring to Fig. 9, Fig. 9 is the stream of another embodiment of fan-out package method of the present invention
Journey schematic diagram, the main distinction of this method and one embodiment are, there is provided package substrate includes：Silicon Wafer basic unit back to
The side fitting reinforcing plate of pad, its idiographic flow are as follows：
S301：The Silicon Wafer basic unit for being provided with pad is provided, and is bonded and strengthens back to the side of pad in Silicon Wafer basic unit
Plate；Specifically, reference can be made to Figure 10 a, can select thickness to be less than or equal to the Silicon Wafer of predetermined thickness when starting according to the actual requirements
Basic unit 70, for example, when predetermined thickness is 100um, can directly select thickness for 50,60,80um etc. Silicon Wafer basic unit 70；For
The insufficient strength of the Silicon Wafer basic unit 70 in subsequent preparation process is prevented, in the present embodiment, in Silicon Wafer basic unit 70 back to weldering
The side fitting reinforcing plate 74 of disk 72, the material of reinforcing plate 74 can be glass, metal, silicon chip etc., reinforcing plate 74 and Silicon Wafer
It can be fixed between basic unit 70 by a two-sided glued membrane fitting.
S302-S308 is identical with S202-S208 in above-described embodiment, will not be repeated here, and its structural representation can be found in
Figure 10 b-10h.
S309：Remove reinforcing plate；Specifically, as shown in Figure 10 i, in one embodiment, reinforcing plate 74 and Silicon Wafer
Basic unit 70 can directly tear two-sided glued membrane off, and then remove the purpose of reinforcing plate 74 by a two-sided glue-film stickup.
S310-S317 is identical with S210-S217 steps in above-described embodiment, and its structure can be found in Fig. 6 d-6k, wherein, step
The mode of rapid S317 setting soldered ball is referring also to Fig. 8.
In the 3rd embodiment, Figure 12 is referred to, Figure 12 is another embodiment of fan-out package method of the present invention
Schematic flow sheet, the main distinction of this method and one embodiment are that the side that Silicon Wafer basic unit has pad can be carried out
Repeatedly wiring, i.e., second again wiring layer at least re-form wiring layer again and again back to the side of Silicon Wafer basic unit, in the present embodiment
In, Silicon Wafer basic unit has the side of pad including wiring layer, its idiographic flow are as follows twice：
S401-S406 is identical with S201-S206 in above-described embodiment, will not be repeated here, and its structure can be found in Fig. 5 a-
5f。
S407：Second again wiring layer form the first dielectric layer back to the surface of Silicon Wafer basic unit, and in the first dielectric layer
It is upper that 3rd opening is set；Specifically, Figure 13 a are referred to, in one embodiment, the material of the first dielectric layer 80 is photoetching
Glue, after second again one layer of photoresist of surface coating of wiring layer 31, formed using the technique of photoetching on the first dielectric layer 80
3rd opening 800.
S408：In the first dielectric layer second of sublayer is formed back to the surface of Silicon Wafer basic unit；Specifically, figure is referred to
13b, in one embodiment, it can be formed using sputtering technology in the first dielectric layer 80 back to the surface of Silicon Wafer basic unit 30
Second of sublayer 82, the material of second of sublayer 82 is the metals such as copper, titanium.
S409：The second mask layer is formed back to the surface of Silicon Wafer basic unit in second of sublayer, and is set in the second mask layer
Put the 4th opening；Specifically, Figure 13 c are referred to, in one embodiment, the material of the second mask layer 84 is photoresist, profit
The 4th opening 840 is formed with the technique of photoetching.
S410：The 3rd wiring layer again is formed in the 4th opening；Specifically, Figure 13 d are referred to, the work of plating can be utilized
Skill forms the 3rd wiring layer 86 again in the 4th opening 840, and the material of the 3rd wiring layer 86 again can be the metals such as copper；Figure 13 d
In the 3rd again wiring layer 86 fill up it is whole 4th opening 840, in other embodiments, the 3rd again wiring layer 86 also can only the 4th
One layer is paved with opening 840, its thickness can be set according to actual conditions.
S411：Remove the second mask layer and the 3rd second of sublayer beyond wiring layer again；Specifically, figure is referred to
13e, after the second mask layer 84 is removed, then second of the sublayer 82 exposed is etched away；Wherein, second again wiring layer 31,
Wiring layer 86 electrically connects second of sublayer the 82, the 3rd again.
S412：Chip is electrically connected with the pad of package substrate；Specifically, the step and step S207 in above-described embodiment
Similar, the surface of chip 88 is provided with metal salient point 880, can take the metal salient point 880 and the 3rd of chip 88 wiring layer again
86 reflow solderings, with cause chip 88 with the 3rd again wiring layer 86 electrically connect, and pass through the 3rd electricity of wiring layer 86 and pad 32 again
Connection (as shown in figure 13f), can also take the mode (as shown in figure 14) for setting passivation layer on wiring layer 86 again the 3rd,
3rd forms the second passivation layer again on wiring layer, and the 5th opening is set on the second passivation layer, and chip surface is provided with metal
Salient point, by the metal salient point of chip with being open and the 3rd wiring layer reflow soldering again by the 5th, to cause chip and the 3rd again
Wiring layer electrically connect, and by the 3rd again wiring layer electrically connected with pad.
S413-S422 is identical with S208-S217 in above-described embodiment, will not be repeated here, and its structure can be found in Figure 13 g-
Shown in 13p, wherein, the mode of plant ball, which can also be taken, in step S422 is initially formed ball lower metal layer, then in ball lower metal layer
The upper mode for planting ball, as shown in figure 15.
In the 4th embodiment, Figure 16 is referred to, Figure 16 is another embodiment of fan-out package method of the present invention
Schematic flow sheet, the main distinction of this method and one embodiment are, first can be connected up again in Silicon Wafer basic unit both sides
After the completion of, then be electrically connected with chip, its idiographic flow is as follows：
S501-S506 is identical with S201-S206 in above-described embodiment, will not be repeated here, and its structure can be found in Fig. 5 a-
5f。
S507-S513 see Figure 17 a-17g with S209-S215 in above-described embodiment, its structure.
S514：Support plate is provided, the side that the formation of Silicon Wafer basic unit has the first wiring layer again is connected with support plate；Specifically
Ground, refers to Figure 17 h, and the material of support plate can be glass, metal etc., support plate and first again wiring layer side can pass through a pair of
Face glued membrane connection.
S515：The side that the state of setting Silicon Wafer basic unit makes it have pad is above, by chip and package substrate
Pad electrical connection；Specifically, the step is identical with step S207 in above-described embodiment, can take flip-chip to second
Mode on wiring layer (as shown in Figure 17 i) again, the mode that passivation layer is set on wiring layer again second can also be taken, herein
Repeat no more.
S516：By the formation of chip and Silicon Wafer basic unit have second again wiring layer side carry out plastic packaging, specifically, the step
It is identical with step S208 in above-described embodiment, as shown in Figure 17 j.
S517：Remove support plate；Specifically, as shown in Figure 17 k, when support plate and first again wiring layer pass through glued membrane and attach and connect
When, support plate can be removed by way of glued membrane is torn off.
S518：First again wiring layer back to the surface of Silicon Wafer basic unit, the first barrier layer is set, and on the first barrier layer
It is upper to form the 8th opening；Specifically, the step is identical with step S216 in above-described embodiment, as shown in Figure 17 l.
S519：First, soldered ball is set on wiring layer again；Specifically, the step and step S217 phases in above-described embodiment
Together, as shown in Figure 17 m or Fig. 8.
Above-mentioned only signal provides four specific embodiments, is connected up again as long as being related to Silicon Wafer basic unit and having back to pad side
Fan-out package method within protection scope of the present invention.
Figure 18 is referred to, Figure 18 is the structural representation of the embodiment of fan-out package device one of the present invention, and the device 9 wraps
Include：Package substrate 90 and chip 92, wherein, package substrate 90 includes Silicon Wafer basic unit 900, pad 902 and first wiring layer again
904, pad 902 is arranged at the side of Silicon Wafer basic unit 900, first again wiring layer 904 be arranged at the another of Silicon Wafer basic unit 900
Side, wherein, wiring layer 904 electrically connects pad 902 and first again, and chip 92 electrically connects with the pad 902 of package substrate 90.
In an application scenarios, the thickness of Silicon Wafer basic unit 900 is less than or equal to predetermined thickness, such as predetermined thickness is
100um, the thickness of Silicon Wafer basic unit 900 can be 50,70,80um etc..Silicon Wafer basic unit 900 can be provided directly with pad 902,
Such as the wafer that Feng Ce factories typically can directly take；The thickness of the Silicon Wafer basic unit for the wafer directly taken may directly be less than
Equal to predetermined thickness, it is also possible to more than predetermined thickness, when the Silicon Wafer groundwork thickness of wafer exceedes predetermined thickness, it is necessary to silicon
The back side of wafer basic unit 900 is ground, to cause the Silicon Wafer basic unit in fan-out package device provided by the present invention
Thickness is less than or equal to predetermined thickness.
In another application scenarios, because the electric conductivity of Silicon Wafer basic unit 900 is poor, it is located at Silicon Wafer basic unit to realize
Wiring layer 904 electrically connects the pad 902 and first of 900 opposite sides again, in above-mentioned Silicon Wafer basic unit 900 back to pad 902
Side sets silicon hole 906, and the position of the position correspondence pad 902 of silicon hole 906, with cause first again wiring layer 904 it is logical
Silicon hole 906 is crossed to electrically connect with pad 902.
In another application scenarios, please continue to refer to Figure 18, above-mentioned package substrate 90 also includes the second wiring layer again
908, second again wiring layer 908 be arranged on pad 902 and electrically connect pad 902.
Below, several specific embodiments will be made to the structure of fan-out package device provided by the present invention further
Explanation.
Please continue to refer to Figure 18, in one embodiment, Silicon Wafer basic unit 900 removes back to the side of pad 902 to be included
First again outside wiring layer 904, and the device also includes：3rd mask layer 901, Silicon Wafer basic unit 900 is arranged at back to pad 902
Side and first is again between wiring layer 904, and the position of corresponding pad 902 is provided with the 6th opening (not indicating)；The third son
Layer 903, the 3rd mask layer 901 and first is arranged at again between wiring layer 904；Wherein, first again wiring layer 904, the third son
Layer 903, pad 902 electrically connect；First barrier layer 905, be arranged at first again wiring layer 904 back to Silicon Wafer basic unit 900 one
Side, and the 8th opening (not indicating) is formed on the first barrier layer 905；Soldered ball 907, it is arranged in the 8th opening (not indicating),
And with first again wiring layer 904 electrically connect.Silicon Wafer basic unit 900 is provided with the side of pad 902 except including the second wiring layer again
Outside 908, the device also includes：First passivation layer 909, it is arranged at the side of pad 902 and the second cloth again of Silicon Wafer basic unit 900
Between line layer 908, and the position of the corresponding pad 902 of the first passivation layer 909 is provided with the first opening (not indicating)；First Seed Layer
910, the first passivation layer 909 and second is arranged at again between wiring layer 908；Wherein, pad 902, the first Seed Layer 910, second
Wiring layer 908 electrically connects again.Metal salient point 920 is provided with chip 92, chip 92 is connected up again by metal salient point 920 with second
Layer 908 passes through reflow soldering；Plastic packaging layer 911, plastic packaging layer 911 covers chip 92 and Silicon Wafer basic unit 900 is provided with pad 902
Side.
Figure 19 is referred to, Figure 19 is the structural representation of another embodiment of fan-out package device of the present invention；In this reality
Apply in example, the difference of the packaging and packaging in above-mentioned Figure 18 is that Silicon Wafer basic unit is set back to the side of pad and welded
The mode of ball, the mode that ball lower metal layer is set is taken in the present embodiment.Specifically, the packaging is removed and included in above-mentioned Figure 18
Structure outside, in addition to：4th Seed Layer 1002, the 8th opening (not indicating) on the first barrier layer 1000 of covering, and be arranged on
First barrier layer 1000 is back to the side of Silicon Wafer basic unit 1004；Ball lower metal layer 1006, it is arranged at the 4th Seed Layer 1002 and carries on the back
To the side of Silicon Wafer basic unit 1004；Soldered ball 1008, ball lower metal layer 1006 is arranged at back to the side of Silicon Wafer basic unit 1004；
Wherein, wiring layer 1001 electrically connects again for soldered ball 1008, ball lower metal layer 1006, the 4th Seed Layer 1002, first.
Figure 20 is referred to, Figure 20 is the structural representation of the another embodiment of fan-out package device of the present invention；In this reality
Apply in example, the difference of the packaging and packaging in figure 19 above is, the side of pad can be set in Silicon Wafer basic unit
Progress repeatedly connects up again, exemplified by the side to be provided with pad in Silicon Wafer basic unit carries out wiring twice, i.e., the second wiring layer again
1102 also include the 3rd wiring layer 1104 again back to the side of Silicon Wafer basic unit 1100.Specifically, the packaging and above-mentioned figure
Identical structure will not be repeated here in 19, and packaging also includes in the present embodiment：First dielectric layer 1106, is arranged at second
Wiring layer 1102 and the 3rd is provided with the 3rd opening (not indicating) again again between wiring layer 1104, and on the first dielectric layer 1106；
Second of sublayer 1108, the first dielectric layer 1106 and the 3rd is arranged at again between wiring layer 1104；Wherein, the second wiring layer again
1102nd, wiring layer 1104 electrically connects second of sublayer the 1108, the 3rd again；The surface of chip 112 is provided with metal salient point 1120, chip
112 pass through the reflow soldering of wiring layer 1104 again of metal salient point 1120 and the 3rd.
Figure 21 is referred to, Figure 21 is the structural representation of fan-out package device a further embodiment of the present invention；In this reality
Apply in example, the difference of the packaging and packaging in figure 20 above is, chip and the 3rd mode that wiring layer electrically connects again.
Specifically, as shown in figure 21, device also includes：Second passivation layer 1200, be arranged at the 3rd again wiring layer 1202 back to Silicon Wafer
The side of basic unit 1204, and the second passivation layer 1200 is provided with the 5th opening, the surface of chip 122 is provided with metal salient point 1220,
The metal salient point 1220 of chip 122 passes through the 5th opening and the 3rd reflow soldering of wiring layer 1202 again.
In other embodiments, or other structures form packaging, this is not limited by the present invention.
Sum it up, the situation of prior art is different from, the encapsulation base in fan-out package method of the present invention
Plate includes Silicon Wafer basic unit, pad and the first wiring layer again, pad and first again wiring layer be located at the two of Silicon Wafer basic unit respectively
Side, pad with first again wiring layer electrically connect, chip electrically connects with pad；On the one hand, package substrate includes pad, chip and envelope
The pad electrical connection of substrate is filled, so as to avoid during follow-up chip plastic packaging due to glued membrane chip position caused by by thermal softening etc.
Put situation about shifting；On the other hand, package substrate includes Silicon Wafer basic unit, and the thermal conductivity of Silicon Wafer basic unit is preferable, so as to
Be advantageous to the radiating of fan-out package device；Another further aspect, the pad of package substrate and first again wiring layer be located at silicon wafer physa
The opposite sides of layer, technical support is provided subsequently to provide the two-sided fan-out package structure for having ball structure.
Embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this
The equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, it is included within the scope of the present invention.
Claims (13)
- A kind of 1. fan-out package method, it is characterised in that methods described includes：Package substrate is provided, wiring layer, the pad are arranged at the package substrate again including Silicon Wafer basic unit, pad and first Silicon Wafer basic unit side, described first again wiring layer be arranged at the opposite side of the Silicon Wafer basic unit, wherein, the pad With the described first wiring layer electrical connection again；Chip is electrically connected with the pad of the package substrate.
- 2. according to the method for claim 1, it is characterised in that the offer package substrate includes：The Silicon Wafer basic unit provided with the pad is provided；Form the described first wiring layer again of wiring layer, second again respectively in the both sides that the Silicon Wafer basic unit is oppositely arranged, it is described Second again wiring layer be formed on the pad and electrically connect the pad.
- 3. according to the method for claim 2, it is characterised in that wiring layer includes before again for the formation described first：Set the state of the Silicon Wafer basic unit to make it have the side of the pad and be located at lower section；Silicon hole is formed in the position back to the pad of the Silicon Wafer basic unit.
- 4. according to the method for claim 3, it is characterised in thatIt is described to include before the position back to the pad of the Silicon Wafer basic unit forms silicon hole：Grind the silicon wafer Physa layer is back to the side of the pad, to cause the thickness of the Silicon Wafer basic unit to be less than or equal to predetermined thickness.
- 5. according to the method for claim 3, it is characterised in thatThe offer package substrate includes：In the Silicon Wafer basic unit reinforcing plate is bonded back to the side of the pad；It is described to include before the position back to the pad of the Silicon Wafer basic unit forms silicon hole：Remove the reinforcement Plate.
- 6. according to the method for claim 2, it is characterised in thatIt is described chip is electrically connected with the pad of the package substrate including：The chip surface is provided with metal salient point, By the metal salient point of the chip and the described second wiring layer reflow soldering again, to cause the chip with described second again Wiring layer electrically connect, and by described second again wiring layer electrically connected with the pad.
- 7. according to the method for claim 6, it is characterised in that it is described by the chip with described second again wiring layer be electrically connected Include after connecing：By the formation of the chip and the Silicon Wafer basic unit have described second again wiring layer side carry out plastic packaging.
- 8. according to the method for claim 7, it is characterised in that it is described by the chip with described second again wiring layer be electrically connected Include before connecing：Support plate is provided, is formationed of the Silicon Wafer basic unit is had into the described first side of wiring layer and support plate again Connection；The formation by the chip and the Silicon Wafer basic unit have described second again wiring layer side carry out plastic packaging after also Including：Remove the support plate.
- 9. according to the method for claim 2, it is characterised in that described to form the described second cloth again in the Silicon Wafer basic unit Line layer, including：The side that the pad is provided with the Silicon Wafer basic unit forms the first passivation layer, and corresponding in first passivation layer The position of the pad sets the first opening；In first passivation layer the first Seed Layer is formed back to the surface of the Silicon Wafer basic unit；The first mask layer is formed back to the surface of the Silicon Wafer basic unit in first Seed Layer, and in first mask layer The position of the corresponding pad sets the second opening；The described second wiring layer again is formed in the described second opening；Remove first mask layer and described second the first Seed Layer beyond wiring layer again；Wherein, wiring layer electrically connects again for the pad, first Seed Layer, described second.
- 10. according to the method for claim 9, it is characterised in that described to form described second again in the Silicon Wafer basic unit After wiring layer, including：Described second again wiring layer at least re-form back to the side of the Silicon Wafer basic unit and connect up again and again Layer；Described second again wiring layer at least re-form again and again wiring layer back to the side of the Silicon Wafer basic unit and include：Described second again wiring layer form the first dielectric layer back to the surface of the Silicon Wafer basic unit, and in first dielectric 3rd opening is set on layer；In first dielectric layer second of sublayer is formed back to the surface of the Silicon Wafer basic unit；The second mask layer is formed back to the surface of the Silicon Wafer basic unit in second of sublayer, and in second mask layer 4th opening is set；The 3rd wiring layer again is formed in the described 4th opening；Remove second mask layer and the described 3rd second of sublayer beyond wiring layer again；Wherein, the described second wiring layer electrical connection again of wiring layer, second of sublayer, the described 3rd again.
- 11. according to the method for claim 10, it is characterised in thatIt is described chip is electrically connected with the pad of the package substrate including：The chip surface is provided with metal salient point, By the metal salient point of the chip and the 3rd wiring layer reflow soldering again, to cause the chip with the described 3rd again Wiring layer electrically connect, and by the described 3rd again wiring layer electrically connected with the pad；OrIt is described chip is electrically connected with the pad of the package substrate including：Second is formed on wiring layer again the described 3rd Passivation layer, and the 5th opening is set on second passivation layer, the chip surface is provided with metal salient point, by the chip The metal salient point with by the described 5th opening with the 3rd wiring layer reflow soldering again, to cause the chip and institute State the 3rd again wiring layer electrically connect, and by the described 3rd again wiring layer electrically connected with the pad.
- 12. according to the method for claim 3, it is characterised in that form described first in the Silicon Wafer basic unit and connect up again Layer includes：The 3rd mask layer is formed back to the side of the pad in the Silicon Wafer basic unit, and institute is corresponded in the 3rd mask layer The position for stating pad forms the 6th opening；In the 3rd mask layer the third sublayer is formed back to the surface of the Silicon Wafer basic unit；The 4th mask layer is formed back to the surface of the Silicon Wafer basic unit in the third described sublayer, and in the 4th mask layer It is upper to form the 7th opening；The described first wiring layer again is formed in the described 7th opening；Remove the 4th mask layer and described first the third sublayer beyond wiring layer again；Wherein, described first wiring layer, the third described sublayer electrically connect with the pad again.
- 13. according to the method for claim 12, it is characterised in that described to form described first again in the Silicon Wafer basic unit Include after wiring layer：Described first again wiring layer back to the Silicon Wafer basic unit surface set the first barrier layer, and The 8th opening is formed on first barrier layer；Soldered ball is set in the described 8th opening；Wherein, the soldered ball, described first Wiring layer electrically connects again；OrDescribed first again wiring layer back to the Silicon Wafer basic unit surface set the first barrier layer, and described first stop The 8th opening is formed on layer；On first barrier layer the 4th Seed Layer is formed back to the surface of the Silicon Wafer basic unit；Institute State the 4th Seed Layer and form the 5th mask layer back to the surface of the Silicon Wafer basic unit, and corresponding the on the 5th mask layer The position of eight openings forms the 9th opening；Ball lower metal layer is formed in the described 9th opening；Remove the 5th mask layer and The 4th Seed Layer beyond the ball lower metal layer；Soldered ball is formed on the ball lower metal layer correspondence position；Wherein, the weldering Wiring layer electrically connects again for ball, the ball lower metal layer, the 4th Seed Layer, described first.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740477.7A CN107611043A (en) | 2017-08-24 | 2017-08-24 | A kind of fan-out package method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710740477.7A CN107611043A (en) | 2017-08-24 | 2017-08-24 | A kind of fan-out package method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107611043A true CN107611043A (en) | 2018-01-19 |
Family
ID=61065915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710740477.7A Pending CN107611043A (en) | 2017-08-24 | 2017-08-24 | A kind of fan-out package method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107611043A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928028A (en) * | 2021-01-22 | 2021-06-08 | 广东佛智芯微电子技术研究有限公司 | Board-level chip packaging method with embedded circuit and packaging structure thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120146216A1 (en) * | 2010-12-09 | 2012-06-14 | Nepes Corporation | Semiconductor package and fabrication method thereof |
| US20130210198A1 (en) * | 2012-02-10 | 2013-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming semiconductor structure |
| CN103258803A (en) * | 2012-02-15 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing same |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| US20170229380A1 (en) * | 2016-02-08 | 2017-08-10 | Mitsubishi Electric Corporation | Semiconductor device |
-
2017
- 2017-08-24 CN CN201710740477.7A patent/CN107611043A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120146216A1 (en) * | 2010-12-09 | 2012-06-14 | Nepes Corporation | Semiconductor package and fabrication method thereof |
| US20130210198A1 (en) * | 2012-02-10 | 2013-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming semiconductor structure |
| CN103258803A (en) * | 2012-02-15 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing same |
| CN103606542A (en) * | 2013-11-30 | 2014-02-26 | 华进半导体封装先导技术研发中心有限公司 | TSV metal interconnection structure and manufacturing method thereof |
| CN105470235A (en) * | 2014-08-12 | 2016-04-06 | 矽品精密工业股份有限公司 | Interposer and method of manufacturing the same |
| US20170229380A1 (en) * | 2016-02-08 | 2017-08-10 | Mitsubishi Electric Corporation | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928028A (en) * | 2021-01-22 | 2021-06-08 | 广东佛智芯微电子技术研究有限公司 | Board-level chip packaging method with embedded circuit and packaging structure thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105679681B (en) | Integrated antenna package pad and forming method | |
| TWI402939B (en) | Through-silicon vias and methods for forming the same | |
| JP5764256B2 (en) | Semiconductor chip having support terminal pads | |
| CN103390600B (en) | Semiconductor package and fabrication method thereof | |
| CN108630676A (en) | Semiconductor package part and forming method thereof | |
| US11217534B2 (en) | Galvanic corrosion protection for semiconductor packages | |
| CN104347528B (en) | Semiconductor package and fabrication method thereof | |
| CN105023906A (en) | Substrate with electrical connection structure and manufacturing method thereof | |
| JP2004152810A (en) | Semiconductor device and laminated semiconductor device | |
| CN102655136A (en) | Semiconductor chip and method for manufacturing the same | |
| TW200903763A (en) | Inter-connecting structure for semiconductor device package and method of the same | |
| US8940585B2 (en) | Single layer BGA substrate process | |
| CN102683309B (en) | Wafer scale plants adapter plate structure of ball indentation brush filling through hole and preparation method thereof | |
| KR20130037204A (en) | Circuit board with anchored underfill | |
| CN109216206A (en) | A kind of wafer scale is fanned out to packaging method and encapsulating structure | |
| CN107611043A (en) | A kind of fan-out package method | |
| CN107564880A (en) | A kind of fan-out package device | |
| JP2002313985A (en) | Method of manufacturing chip size package | |
| CN107564879A (en) | A kind of fan-out package device | |
| CN107516638A (en) | A kind of fan-out package method | |
| CN107611112A (en) | A kind of fan-out package device | |
| JP2013504862A (en) | Semiconductor chip with stepped bump structure | |
| CN107611042A (en) | A kind of fan-out package method | |
| CN107481940A (en) | The preparation method and package substrate of a kind of package substrate | |
| CN107195554A (en) | A kind of wafer packaging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180119 |