JP2002313985A - Method of manufacturing chip size package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a chip size package which allows reduction in the number of manufacturing steps and in the cost without using a die and which can protect an LSI sufficiently. SOLUTION: This method of manufacturing a chip size package includes the step of preparing a semiconductor wafer, which has a plurality of semiconductor chip regions having respective integrated circuits and has a plurality of electrodes 204 and 205 formed on the plurality of semiconductor chip regions respectively, the step of forming a plurality of bumps 304 and 305 connected with the plurality of electrodes 204 and 205 respectively on the plurality of electrodes 204 and 205, the step of totally applying a load to the plurality of bumps 304 and 305 to level practically the upper parts of the plurality of bumps 304 and 305 and make the heights of the plurality of bumps 304 and 305 practically uniform, the step of covering the semiconductor wafer with resin 200, the step of polishing the resin 200 so as to expose the upper surfaces of the plurality of bumps 304 and 305, the step of forming a plurality of solder balls 604 and 605 on the plurality of bumps 304 and 305, and the step of deviding the semiconductor wafer on which the plurality of solder balls 604 and 605 are formed into individual semiconductor chips.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI package, and more particularly to a method for manufacturing a chip size package having substantially the same size as an LSI chip.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, (1) "Nikkei Micro Device", February 1995 issue
P. 96-97 (2) "Chip Size Package Technology" Circuit Technology Vol. 9 No. 7 P475-478.

Conventionally, this type of package has a μ-BG
A, chip size package, CSP, etc. are called by various names, and various types of chip size packages have been developed.

FIG. 8 is a partially cutaway perspective view of such a conventional chip size package.

As shown in FIG. 1, after solder vapor deposition and copper bumps are formed on an LSI chip 1, resin sealing is performed with a mold resin 2 and solder bumps 3 for external terminals are provided. In addition, 4
Is a wiring pattern, and 5 is an electrode pad. as a result,
A package having the same size as that of the LSI can be obtained.

FIG. 9 is a partially cutaway perspective view of a tape carrier type of a conventional chip size package.

In this figure, the surface of an LSI chip 5 is coated with an elastic adhesive 6, a flexible wiring 7 is connected to each pad of the LSI, and a solder bump 9 is formed on the flexible wiring 7. ing. The periphery of the solder bump 9 is formed of a polyimide film 8 or the like, and is fixed to the LSI with the elastic adhesive 6 described above. Reference numeral 10 denotes a protection frame. As a result, approximately LSI
You can get the same size package.

That is, in this package, the LSI is mounted on a polyimide wiring board having bumps, and then mounted on a target wiring board.

In another type of package, an LSI chip with wiring is mounted on a wiring board.

[0010]

However, as described above, in the conventional chip size package, the LSI
After cutting the wafer from the wafer, each chip size package is manufactured, so that a dedicated mold is required, which is an obstacle to cost reduction.

Further, in the conventional chip size package, the LSI is mounted twice to mount it on the wiring board, so that the number of steps is increased, and as a result, the price is high.

Further, after cutting out the LSI from the wafer,
Since each chip size package is manufactured, the manufacturing is complicated and there is a problem in manufacturing reliability.

Conventionally, a mold release agent has been added to an epoxy resin mold. This is for the purpose of preventing the adhesion between the mold and the resin, but the adhesion between the LSI and the surrounding metal is weakened, leading to a decrease in reliability.

Further, a method of directly manufacturing bumps on an LSI and mounting the bumps on a substrate in a face-down manner has been proposed and put to practical use. However, in this method, L
The SI was not protected at all and was mechanically weak.

The present invention is directed to a method of manufacturing a chip size package which eliminates the above-mentioned problems, reduces the number of steps without using a mold, can reduce the cost, and sufficiently protects the LSI. The purpose is to provide.

[0016]

According to a first aspect of the present invention, there is provided a method for manufacturing a chip size package, comprising: a plurality of semiconductor chip regions each having an integrated circuit formed therein; Preparing a semiconductor wafer on which a plurality of electrodes are respectively formed on the semiconductor chip region; forming a plurality of bumps respectively connected to the plurality of electrodes on the plurality of electrodes; A step of applying a weight to the plurality of bumps in the semiconductor chip region in a lump to make the upper portions of the plurality of bumps substantially flat and have substantially the same height,
A step of covering the semiconductor wafer with a resin, a step of polishing the resin so as to expose upper surfaces of the plurality of bumps, a step of forming a plurality of solder balls on the plurality of bumps, and a step of forming the plurality of solders Dividing the semiconductor wafer on which the balls are formed into individual semiconductor chips.

[2] The method for manufacturing a chip size package according to the above [1], further comprising a step of exposing the plurality of electrodes and forming a protective film covering a surface of the semiconductor wafer.

[3] The method for manufacturing a chip size package according to [2], wherein the protective film is formed using PSG.

[4] Any one of the above [1] to [3]
In the method for manufacturing a chip size package described in the paragraph, the plurality of bumps are formed using one of gold, copper, and solder.

[5] Any one of the above [1] to [4]
In the method for manufacturing a chip size package described in the paragraph, the resin is formed using an epoxy resin.

[6] Any one of the above [1] to [5]
In the method of manufacturing a chip size package described in the paragraph, the plurality of electrodes are formed to have a rectangular shape or a square shape with one side of 50 μm to 100 μm, and have a thickness of about 1 μm.

[7] Any one of the above [1] to [6]
In the method of manufacturing a chip size package described in the paragraph, each of the plurality of bumps is formed to have a height of 30 μm to 60 μm.

[8] Any one of the above [1] to [7]
3. The method for manufacturing a chip-size package according to item 1, wherein the plurality of bumps are 6 g to 1 per bump.
It is characterized in that a weight of 0 g is applied.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a wafer showing a first embodiment of the present invention, and FIG. 2 is a sectional view of a chip manufacturing process taken along line AA 'in FIG.

FIG. 1 shows one wafer, which shows a state in which preprocessing has been completed and bumps have been formed on the electrodes of each LSI.

In this figure, 101, 102, 10
Reference numerals 3,104... Denote respective LSIs (semiconductor chips), which are cut from the wafer along solid lines C1, C3, C5, C2, C4, C6, and C8. 201, 202, 203, 2
Reference numerals 04, 205, 206, 207, and 208 denote electrodes in each LSI, and usually aluminum of 1 μm thickness is used. , 308 are bumps,
In this embodiment, a so-called stud method (using a wire bonding technique and using a ball at the time of bonding as a bump) is used.

The electrodes 201, 202, 203, 20
4, 205, 206, 207, and 208 each have one side of 5
The bumps 301, 302, 303... Usually have a maximum diameter of 30 to 60 μm and the same height.

Hereinafter, A- of the LSI 104 shown in FIG.
A method for manufacturing a wafer-size chip along the line A 'will be described with reference to FIG.

(1) First, as shown in FIG.
Reference numeral 00 denotes a PSG film (oxide film) for protecting the LSI 104, and bumps 304 and 3 on the electrodes 204 and 205.
05 is formed by a wire bonding technique and thus has a constricted tip. Before the next step, it is convenient to apply a weight of 6 to 10 g per bump, to make the height of each bump uniform, and to flatten the surface of the tip of each bump.

The material of the bump is preferably gold or copper. Both can be manufactured by ordinary techniques.
In particular, a manufacturing apparatus for a gold stud type bump is also sold, and can be manufactured without changing the previous process of the LSI.

Further, for the copper bump, a gas atmosphere in which hydrogen is added to Ar is required at the time of bonding, and the bonding pressure is slightly higher, so that the thickness of the aluminum electrode of the LSI needs to be larger than usual, about 2 μm. However, by optimizing the conditions, it was possible to obtain a good copper stud type bump.

Recently, a technique of bonding a solder wire containing tin-lead as a main component to form a solder bump on an aluminum electrode of an LSI has been put to practical use. Using this technique, the solder bumps 301, 302, 303, 304,
305 can be formed, and the process to be continued can be facilitated.

(2) Bumps are formed on all aluminum electrodes,
After pressing, as shown in FIG. 2B, an epoxy resin 200 is applied to the entire surface of the wafer, and is cured while being pressed and heated by a hot press. Pressing pressure is 15-20k
g weight / cm ² , temperature was 80 to 100 ° C., and almost one hour was required for curing time. By this pressing step, the bumps 301,
The flat upper surfaces of the projections 302, 303, 304, 305 ... are exposed on the surface of the epoxy resin 200. As the resin, a resin having a low volume change ratio before and after curing, such as Eco Bond (trade name, manufactured by Emerson & Cumming) was used. Depending on the resin and pressing conditions, bumps 301, 302, 303, 3
04, 305 ... flat epoxy on the top surface
May remain thinly. At this time, the surface could be exposed by slightly polishing the surface with sandpaper or sandblasting.

(3) Next, FIG.
As shown in (c), the bumps 301, 302, 303,
The solder balls 60 are placed on the flat projections 304, 305,.
4,605 is installed. A solder resist may be present on the epoxy resin 200. These steps are performed over the entire wafer. After installing the solder balls 604 and 605, the solid lines C1, C3, C5, C2, C4, C6, and C6 in FIG.
Cut the wafer along C8.

The chip size package cut as described above is shown below.

FIG. 3 is a perspective view of a chip size package showing a first embodiment of the present invention.

Reference numeral 50 shown by a dotted line in this figure denotes a reinforcing plate for reinforcing this chip size package. This chip size package has sufficient strength because its surface is coated with an epoxy resin, but may require additional strength before use. By attaching the reinforcing plate 50 before wafer cutting, a chip size package with a reinforcing plate can be obtained with a very small number of steps.

With such a structure, it has the same area as the LSI chip.

According to the present invention, this package is small and has the same reliability as the so-called molded package in terms of strength, moisture resistance and the like.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a plan view of a chip portion of a wafer showing a second embodiment of the present invention. FIG. FIG. 4 is a perspective view of a chip size package according to a second embodiment of the present invention. Note that the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In these figures, 402, 404, 4
Reference numerals 05 and 407 denote wiring metals formed on the epoxy resin 200 for moving the position of the solder ball from a position directly above the aluminum electrode. The step of forming the wiring metal may be performed by, for example, aluminum deposition, photolithography, and etching, and does not use any new technology. The plating technique may be used. Solder balls 601,
A solder resist 500 for forming 602, 603, 604, 605,... Is formed.

In this embodiment, as in the first embodiment, the solder balls for connection are not formed directly above the aluminum electrodes of the LSI, but are formed at places separated in a plane.

That is, as shown in FIG.
As in the embodiment, each aluminum electrode 204,
The stud bumps 304 and 305 are set on the 205, and then the epoxy resin 200 is applied, pressed, and heated. After processing, the wiring metal 404,
405 is formed, and after solder resist 500 is applied, solder balls 604 and 605 are set.

Finally, the wafer is cut to cut out an LSI.

As described above, after forming the solder balls, a portion corresponding to one LSI obtained by cutting one wafer is enlarged as shown in FIG.

In this embodiment, after the formation of the bumps, a wiring metal for moving the solder balls was formed. It is also possible to form a wiring metal for moving the solder balls before forming the epoxy resin.

FIG. 7 is a cross-sectional view of a main part of a chip size package according to a third embodiment of the present invention in which wiring metal is formed first. The same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

In this figure, reference numerals 704 and 705 denote wiring metals for moving the positions of the solder balls 604 and 605,
804 and 805 are bumps.

According to the above embodiment, it is possible to easily obtain a chip size package in which the connection solder balls 604 and 605 are at desired positions.

In particular, as in the first embodiment, since the cutting of the wafer is performed last, the number of steps per package is reduced and the cost can be reduced. Further, a sufficient adhesive force of the epoxy resin to the LSI can be obtained.

In both the first and second embodiments, the bump has been described as a stud bump. However, it was possible to sufficiently implement the present invention even if bumps formed by ordinary plating were used.

The first and second embodiments use a step of sealing the resin after the bumps are formed. However, it has also been effective to apply a resin to the entire surface and then remove the resin by a photolithography technique or the like according to a necessary portion, and form a bump at the removed portion by electroless plating or the like.

FIGS. 10 to 12 are views showing a fourth embodiment of the present invention. FIG. 10 is a cross-sectional view of a manufacturing process of a chip size package (a line CC 'in FIG. 11) showing a fourth embodiment of the present invention. FIG. 11 is a plan view of the chip size package, and FIG. 12 is a perspective view of the chip size package.

The overall plan view of the wafer is the same as that of the first embodiment, so that the illustration is omitted here.

Hereinafter, a method of manufacturing the chip size package will be described with reference to FIG.

(1) First, as shown in FIG.
PSG film (oxide film) 10 for protecting LSI 104
0 is formed. Since the bumps 304 and 305 connected to the aluminum electrodes 204 and 205 are manufactured by a wire bonding technique, the tips have a constricted shape.

The material of the bump is preferably gold or copper. Both can be manufactured by ordinary techniques.
In particular, a manufacturing apparatus for a gold stud type bump is also sold, and can be manufactured without changing the previous process of the LSI.

In addition, since a gas atmosphere in which hydrogen is added to Ar at the time of bonding is required for the copper bump and the bonding pressure is slightly higher, it is necessary to make the thickness of the aluminum electrode of the LSI about 2 μm larger than usual. Although it occurred, it was possible to obtain good copper stud type aluminum by optimizing the conditions.

Recently, a technique of bonding a solder wire containing tin-lead as a main component to form a solder bump on an aluminum electrode of an LSI has been put to practical use. Using this technique, the solder bumps 304, 305,... Can be easily formed, and the process of continuing the process is also facilitated.

(2) Next, as shown in FIG.
After forming bumps 304 and 305 on the aluminum electrodes 204 and 205 of all the LSIs 104 and flattening the tips by pressing,
A copper foil 1400 (eg, 15 μm thick) is brazed to the entire surface of the wafer. The surface of the copper foil 1400 is plated with tin or solder in advance to a thickness of about 1 μm, and the plating film (not shown) and the bumps 304 and 305 are brazed at a low temperature.

Next, the copper foil 1400 and the PSG film 100
An epoxy resin 1200 is poured in between and cured by heating. As the resin, a resin having a low volume change ratio before and after curing, such as Eco Bond (trade name, manufactured by Emerson & Cumming) was used. The distance between the LSI 104 and the copper foil 1400 is 4
Since it is about 0 μm, the resin 1200 can be efficiently and reliably filled by the capillary phenomenon.
Adhesion with 4 surfaces and 1400 copper foils was also very good. In addition, when the bump material was solder, the bump and the copper foil could be easily connected without plating the copper foil with tin, solder, or the like in advance.

(3) Next, as shown in FIG. 10C, the copper foil 1400 was etched to form desired wiring metals 1404 and 1405 on the epoxy resin 1200. The etching process of the copper foil 1400 is performed, for example, by coating the copper foil 1400 with a photosensitive dry film, performing exposure and development processes using a mask, and then selectively etching copper with a ferric chloride solution. went.

(4) Next, after the electrodes 1404 and 1405 are formed, a solder resist 1500 for applying the solder balls 604 and 605 is applied.
605 is set in a predetermined place.

FIG. 11 shows a plan view of the chip size package thus obtained.

In this figure, 1401, 1402, 1
403, 1404, 1405,... Are wiring metals made of copper foil formed on the resin 1200;
Reference numerals 2,603,604,605,... Denote solder balls.

LSI aluminum electrodes 201, 203, 20
For 6,208, a connection point to an external circuit is provided directly above the 6,208. For the aluminum electrodes 204 and 205, the bumps (30
4,305 etc.) to move the connection point with the external circuit.

Solder balls 601, 602, 603, 60
After installation of 4,605,..., As shown in FIG.
3, the wafer is cut along C5, C2, C4, C6, and C8. LSI 104 after cutting
2 is shown.

Reference numeral 700 shown in FIG. 12 is a reinforcing plate for reinforcing the chip size package. This chip size package has sufficient strength because its surface is coated with epoxy resin, but may require additional strength before use. By attaching the reinforcing plate 700 before wafer cutting,
It is possible to obtain a chip size package with the reinforcing plate 700 in a very small number of steps.

Further, since the epoxy resin is applied to the chip surface, substantially the same reliability as that of a so-called resin mold can be guaranteed.

As shown in the conventional literature, a conventional chip size package is packaged after die cutting of an LSI. However, in the present invention, since all packaging operations can be performed in wafer units, the number of steps is small,
The price can be reduced.

In a conventional epoxy resin mold, a mold release agent has been added to the mold. This is for the purpose of preventing the adhesion between the mold and the resin, but the adhesion between the LSI and the surrounding metal is weakened, leading to a decrease in reliability.

However, since a mold is not used in the technique of the present invention, it is not necessary to add a release agent to the epoxy resin. In addition, a silane coupling agent or the like that promotes adhesion to a resin could be effectively used.

According to the present invention, this package remains small and has the same reliability as the so-called molded package in terms of strength, moisture resistance and the like.

In the present invention, the bump is described as a stud type. However, it is naturally possible to use bumps formed by ordinary plating, and other methods may be used. The material of the bump is not limited to copper, gold, and tin-lead solder, and other materials can be used.

Although the description has been given of the case where the foil to be attached to the bumps on the entire surface of the wafer is a copper foil, a good chip size package can be obtained by using a gold foil, a Kovar plate or the like.

Further, the connection with each bump could be made not by low-temperature brazing but also by high-temperature pressure welding, ultrasonic connection or the like. In this case, no solder plating, tin plating, or the like was required on the copper foil.

Although the patterning of the copper foil has been described using a method using a dry film, a method such as a method of coating a resist can sufficiently cope with it.

Although the epoxy resin is injected between the copper foil and the LSI by capillary action, other types of resin such as polyimide resin can be used.

Although the connection with the external circuit has been described as being made by the solder ball, it is also possible to weld a metal piece to a connection planned place to form a connection terminal. Alternatively, a conductive paint may be applied to a necessary portion.

The present invention is not limited to the above embodiments, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0083]

As described above, according to the present invention, the following effects can be obtained.

(1) A chip size package having the same area as the LSI chip can be obtained.

Further, since the resin is adhered to the chip surface, almost the same reliability as a so-called resin mold can be guaranteed.

That is, it is possible to secure the same reliability as a so-called molded package in terms of strength, moisture resistance, etc., while keeping the package small.

(2) In addition to the effect of (1), the strength of the surface of the LSI and the reliability of connection can be improved.

(3) In addition to the effect of (1), the positions of the pad electrodes of the LSI and the solder balls can be arbitrarily changed, and the degree of freedom of connection can be increased.

(4) Since all packaging operations can be performed on a wafer-by-wafer basis, the number of steps is reduced and the cost can be reduced.

As described above, since the wafer is cut at the end, the number of steps per package is reduced.
The price can be reduced.

(5) In addition to the effect of the above (4), before cutting out the LSI from the wafer, the reinforcing plate is bonded to the whole surface of the wafer, so that the LSI can be mechanically reinforced and surely. Cutting can be performed from the wafer.

(6) Since no mold is used, there is no need to add a release agent to the epoxy resin. In addition, a silane coupling agent or the like that promotes adhesion to a resin could be effectively used.

(7) A chip size package similar to the above (6) can be manufactured.

[Brief description of the drawings]

FIG. 1 is a plan view of a wafer showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the chip in the manufacturing process along line AA 'in FIG.

FIG. 3 is a perspective view of a chip size package showing the first embodiment of the present invention.

FIG. 4 is a plan view of a portion serving as a chip of a wafer according to a second embodiment of the present invention.

FIG. 5 is a sectional view (sectional view taken along line BB ′ of FIG. 4) of a chip of a wafer showing a second embodiment of the present invention;

FIG. 6 is a perspective view of a chip size package showing a second embodiment of the present invention.

FIG. 7 is a sectional view of a main part of a chip size package in a case where wiring metal is formed first according to a third embodiment of the present invention.

FIG. 8 is a partially cutaway perspective view of a conventional chip size package.

FIG. 9 is a partially cutaway perspective view of a tape carrier type of a conventional chip size package.

FIG. 10 is a sectional view (sectional view taken along the line CC ′ in FIG. 11) of a chip size package according to a fourth embodiment of the present invention;

FIG. 11 is a plan view of a chip size package according to a fourth embodiment of the present invention.

FIG. 12 is a perspective view of a chip size package showing a fourth embodiment of the present invention.

[Explanation of symbols]

50, 700 Reinforcement plate 100 PSG film (oxide film) protection film 101, 102, 103, 104,... LSI (semiconductor chip) 200, 1200 Epoxy resin 201, 202, 203, 204, 205, 206, 2
07,208 Electrode (aluminum) 301, 302, 303, 304, 305, 306, 3
07, 308, 804, 805 Bump (stud bump) 402, 404, 405, 407, 704, 705, 1
401, 1402, 1404, 1405 Wiring metal 500, 1500 Solder resist 601, 602, 603, 604, 605,... Solder ball 1400 Copper foil

Claims (8)

[Claims] (A) preparing a semiconductor wafer having a plurality of semiconductor chip regions each having an integrated circuit formed thereon, and having a plurality of electrodes formed on each of the plurality of semiconductor chip regions; A) forming a plurality of bumps respectively connected to the plurality of electrodes on the plurality of electrodes; and (c) collectively applying a weight to the plurality of bumps in the plurality of semiconductor chip regions. (D) covering the semiconductor wafer with a resin; and (e) covering the upper surface of the plurality of bumps. Polishing the resin so that the solder balls are exposed; (f) forming a plurality of solder balls on the plurality of bumps; and (g) forming the semiconductor wafer on which the plurality of solder balls are formed. Method of manufacturing a chip size package, wherein a and a step of dividing into individual semiconductor chips. 2. The method of manufacturing a chip size package according to claim 1, further comprising a step of exposing said plurality of electrodes and forming a protective film covering a surface of said semiconductor wafer. Production method. 3. The method of manufacturing a chip size package according to claim 2, wherein said protective film is formed using PSG. 4. The method of manufacturing a chip size package according to claim 1, wherein the plurality of bumps are formed using one of gold, copper, and solder. Manufacturing method of a chip size package. 5. The method of manufacturing a chip size package according to claim 1, wherein said resin is formed using an epoxy resin. 6. The method for manufacturing a chip-size package according to claim 1, wherein the plurality of electrodes have a rectangular shape with a side of 50 μm to 100 μm or a square shape, and have a size of about 1 μm. A method for manufacturing a chip size package, characterized in that the chip size package is formed to have a thickness. 7. The method of manufacturing a chip size package according to claim 1, wherein each of the plurality of bumps has a height of 30 μm to 60 μm. Manufacturing method of chip size package. 8. The method of manufacturing a chip size package according to claim 1, wherein a weight of 6 g to 10 g is applied to each of the plurality of bumps. Manufacturing method of size package.