JP4279224B2 - Chip size package - Google Patents

Description

  The present invention relates to an LSI package, and more particularly to a chip size package that is approximately the same size as an LSI chip.

  Conventionally, as a technique in such a field, for example, there are those described in Non-Patent Documents 1 and 2.

  Conventionally, this type of package is called by various names such as μ-BGA, chip size package, and CSP, and various types of chip size packages have been developed.

  FIG. 8 is a partially broken perspective view of such a conventional chip size package.

  As shown in this figure, solder is vapor-deposited on the LSI chip 1 to form copper bumps, which are then sealed with a mold resin 2 to attach solder bumps 3 for external terminals. In addition, 4 is a wiring pattern and 5 is an electrode pad. As a result, a package having the same size as that of the LSI chip can be obtained.

  FIG. 9 is a sectional view showing a tape carrier system in a conventional chip size package.

  In this figure, an elastic adhesive 6 is coated on the surface of the LSI chip, flexible wiring 7 is connected to each pad of the LSI, and solder bumps 9 are formed on the flexible wiring 7. A polyimide film 8 or the like is formed around the solder bump 9 and fixed to the LSI chip with the elastic adhesive 6 described above. Reference numeral 10 denotes a protective frame. As a result, a package having the same size as that of the LSI chip can be obtained.

  That is, in this package, an LSI chip is mounted on a polyimide wiring board having bumps, and then mounted on a target wiring board.

In other types of packages, the LSI chip to which wiring is applied is mounted on a wiring board.
“Nikkei Microdevice” February, 1995 issue 96-97 “Chip Size Package Technology” Circuit Technology Vol. 9 No. 7 P475-478

  However, as described above, in the conventional chip size package, after the LSI is cut out from the wafer, each chip size package is manufactured. Therefore, a dedicated die is required, which is an obstacle to cost reduction. It was.

  Further, in the conventional chip size package, since the LSI is mounted twice for mounting on the wiring board, the number of processes increases, resulting in high cost.

  Furthermore, since each chip size package is manufactured after the LSI is cut out from the wafer, the manufacturing is complicated and the manufacturing reliability is also a problem.

  Conventional epoxy resin molds have been added with a mold release agent. This is for the purpose of preventing the adhesion between the mold and the resin, but the adhesive strength between the LSI and the surrounding metal is weakened, leading to a decrease in reliability.

  Furthermore, a method for producing bumps directly on an LSI and mounting them on a substrate by a face-down method has been proposed and put into practical use. However, this method does not protect the LSI at all and is mechanically weak.

  An object of the present invention is to provide a chip size package that eliminates the above-mentioned problems, improves the moisture resistance in terms of strength while maintaining a small package, and sufficiently protects an LSI.

In order to achieve the above object, the present invention provides
[1] In a chip size package, a semiconductor chip having a plurality of electrodes formed on a surface thereof, a bump formed by using a stud system formed on the electrode, and the stud system on the surface of the semiconductor chip a resin provided so as to expose the top surface of the bump formed using a this provided on the resin, wiring electrically connecting said bump formed using the stud system, the And a solder ball provided on the center side of the semiconductor chip with respect to the corresponding electrode .

[ 2 ] In the chip size package described in [ 1 ], the back surface of the semiconductor chip is exposed.

[ 3 ] The chip size package according to [1] or [2] , wherein the bump is made of gold.

[ 4 ] The chip size package according to [1] or [2] , wherein the bump is made of copper.

[ 5 ] The chip size package according to any one of [1] to [ 4 ], wherein the bump has a height of 30 μm to 60 μm.

[ 6 ] The chip size package according to any one of [1] to [ 5 ], wherein a protective film is provided between the surface of the semiconductor chip and the resin.

[ 7 ] In the chip size package described in any one of [1] to [ 6 ], the tip of the bump has a constricted shape.

[ 8 ] In the chip size package described in [1], the side surface of the semiconductor chip is exposed.

[ 9 ] The chip size package according to [1], wherein a solder resist covering the wiring is formed.

In [10] a chip size package, a semiconductor chip having a plurality of electrodes are formed on the surface, one end, and a narrow second end width than the one end, a stud system wherein one end is connected on the electrode A gold bump formed using the wiring, a wiring connected to the other end, the wiring extending from the corresponding electrode to the center side of the semiconductor chip, the surface of the semiconductor chip, and the wiring And a resin formed between the two.

[ 11 ] In the chip size package described in [ 10 ], the side surface of the semiconductor chip is exposed.

[ 12 ] The chip size package according to [ 10 ], wherein a solder resist covering the wiring is formed.

  According to the present invention, the following effects can be achieved.

  (1) A chip size package having the same area as the LSI chip can be obtained.

  Further, since the resin is applied to the chip surface, almost the same reliability as a so-called resin mold can be guaranteed.

  That is, the package remains small, and the reliability equivalent to that of a so-called mold package can be ensured in terms of strength and moisture resistance.

  (2) In addition to the effect (1), the strength of the surface of the LSI and the reliability of connection can be improved.

  (3) In addition to the effect of (1), the positions of the LSI pad electrode and the solder ball can be arbitrarily changed, and the degree of freedom of connection can be increased.

  (4) Since all the packaging operations can be performed in units of wafers, man-hours can be reduced and the cost can be reduced.

  In this way, since the wafer is cut last, the number of steps per package is reduced, and the cost can be reduced.

  (5) In addition to the effect of (4) above, since the reinforcing plate is bonded to the entire surface of the wafer before the LSI is cut out from the wafer, the LSI can be mechanically reinforced and reliably cut out from the wafer. It can be performed.

  (6) Since no mold is used, it is not necessary to add a release agent to the epoxy resin. Moreover, the silane coupling agent etc. which accelerate | stimulate adhesion | attachment with resin were able to be used effectively.

  (7) A chip size package having the same effect as the above (6) can be manufactured.

The chip size package of the present invention includes a semiconductor chip having a plurality of electrodes formed on a surface thereof, a bump formed using a stud system formed on the electrodes, and the stud system on the surface of the semiconductor chip. a resin provided so as to expose the top surface of the bump formed using a this provided on the resin, wiring electrically connecting said bump formed using the stud system, the A solder ball formed on the wiring and provided closer to the center of the semiconductor chip than the corresponding electrode . Therefore, it is possible to provide a chip size package that has a small package size, improved moisture resistance and sufficient LSI protection.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan view of a wafer showing a first embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip manufacturing process taken along the line AA 'of FIG.

  In FIG. 1, one wafer is shown, showing a state in which the pre-processing is finished and bumps are formed on the electrodes of each LSI.

  In this figure, reference numerals 101, 102, 103, 104... Denote LSIs, which are cut from the wafer along solid lines C1, C3, C5, C2, C4, C6, and C8.

  201, 202, 203, 204, 205, 206, 207, 208 are electrodes in each LSI, and aluminum of 1 μm thickness is usually used. 301, 302, 303,..., 308,... Are bumps. In this embodiment, a so-called stud method (wire bonding technique is used, and balls during bonding are used as bumps) is used.

  The electrodes 201, 202, 203, 204, 205, 207, 208 each have a rectangular or square shape with one side of 50 to 100 μm, and the bumps 301, 302, 303. The height is almost the same at ˜60 μm.

  Hereinafter, a method for manufacturing a wafer size chip along the line AA ′ of the LSI 104 shown in FIG. 1 will be described with reference to FIG.

  (1) First, as shown in FIG. 2A, reference numeral 100 denotes a PSG film (oxide film) for protecting the LSI 104, and the bumps 304 and 305 on the electrodes 204 and 205 are manufactured by a wire bonding technique. So the tip is constricted. Before the next process, it is convenient to apply a weight of 6 to 10 g per bump, align the heights of the bumps 204 and 205, and make the surface of the tip of each bump 204 and 205 flat.

  The material of the bumps 204 and 205 is preferably gold or copper. Both can be made by conventional techniques. In particular, with respect to gold stud bumps, a manufacturing apparatus is also sold and can be manufactured without changing the previous process of LSI.

  In addition, for copper bumps, a gas atmosphere in which hydrogen is added to Ar is required during bonding, and the bonding pressure is slightly higher, so the thickness of the LSI aluminum electrode needs to be about 2 μm thicker than usual. However, it is possible to obtain a good copper stud bump by optimizing the conditions.

  Recently, a technique for bonding a solder wire mainly composed of tin-lead to form a solder bump on an aluminum electrode of an LSI has been put into practical use. If this technique is used, the solder bumps 304 and 305 can be easily formed, and the process to continue further becomes easier.

(2) After forming and pressing bumps 304 and 305 on all the aluminum electrodes 204 and 205, as shown in FIG. 2B, the epoxy resin 200 is deposited on the entire surface of the wafer and pressed and heated by hot pressing. While curing. The press pressure was 15 to 20 kgf / cm ² , the temperature was 80 to 100 ° C., and the curing time was approximately 1 hour. By this pressing process, the flat upper surfaces of the bumps 301, 302, 303, 304, 305... Are exposed on the surface of the epoxy resin 200. The resin used was a low volume change rate before and after curing, such as Ecobond (trade name, manufactured by Emerson & Cumming). Depending on the resin and pressing conditions, the epoxy resin 200 may remain thin on the upper surfaces of the flat protrusions of the bumps 304 and 305. At this time, the surface could be exposed by slightly polishing with sandpaper or sandblast.

  (3) Next, as shown in FIG. 2C, solder balls 604 and 605 are placed on the upper surfaces of the flat protrusions of the bumps 304 and 305 by a normal process. A solder resist may be present on the epoxy resin 200. These processes are performed over the entire wafer. After the solder balls 604 and 605 are installed, the wafer is cut along the solid lines C1, C3, C5, C2, C4, C6, and C8 in FIG.

  The chip size package that has been cut as described above is shown below.

  FIG. 3 is a perspective view of a chip size package showing the first embodiment of the present invention.

  In this figure, 601, 602, 603, 604, 605,... Are solder balls. Reference numeral 50 shown by a dotted line in this figure is a reinforcing plate for reinforcing the chip size package. This chip size package has sufficient strength because the surface is coated with an epoxy resin, but may require further strength before use. By sticking the reinforcing plate 50 before wafer cutting, a chip size package with a reinforcing plate can be obtained with an extremely small number of steps.

  Because of such a structure, a chip size package having the same area as the LSI chip can be obtained.

  According to the present invention, this semiconductor package remains small and has the same reliability as a so-called mold package in terms of strength, moisture resistance and the like.

  Next, a second embodiment of the present invention will be described.

  FIG. 4 is a plan view of a portion to be a chip of a wafer according to a second embodiment of the present invention, FIG. 5 is a cross-sectional view of the chip of the wafer (cross-sectional view along the line BB 'in FIG. 4), and FIG. It is a perspective view of the chip size package which shows 2nd Example of this. The same parts as those in the first embodiment are denoted by the same reference numerals and their description is omitted.

  In these drawings, 401, 402, 403, 404, 405, 407,... Are wiring metals formed on the epoxy resin 200. In particular, the wiring metals 402, 404, 405, 407 are solder balls 602, 604. , 605,... Are moved from positions directly above the aluminum electrodes 202, 204, 205, 207. The wiring metal 401, 402, 403, 404, 405, 407,... May be formed by, for example, aluminum vapor deposition, photolithography, etching, and no new technique is used. Moreover, you may form by a plating technique. A solder resist 500 is formed to install the solder balls 601, 602, 603, 604, 605,.

  In this embodiment, as in the first embodiment, the solder balls for connection are not formed directly above the aluminum electrodes of the LSI, but are formed in locations separated in a plane.

  That is, as shown in FIG. 5, first, as in the first embodiment, the stud bumps 304 and 305 are formed on the aluminum electrodes 204 and 205 of the LSI 104, and then the epoxy resin 200 is applied and pressed. After heating and processing, wiring metals 404 and 405 are formed on the surface of the epoxy resin 200, and after applying a solder resist 500, solder balls 604 and 605 are installed.

  Finally, the wafer is cut to cut out the LSI.

  As described above, after forming the solder balls, a portion corresponding to one LSI obtained by cutting one wafer is enlarged as shown in FIG.

  In this embodiment, after forming the bumps, a wiring metal for moving the solder balls was formed. It is also possible to form a wiring metal for moving the solder balls before forming the epoxy resin.

  FIG. 7 is a cross-sectional view of the main part of a chip size package when the formation of the wiring metal according to the third embodiment of the present invention is performed first. The same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted.

  In this figure, 704 and 705 are wiring metals for moving the positions of the solder balls 604 and 605, and 804 and 805 are bumps.

  According to the above embodiment, it is possible to easily obtain a chip size package in which the solder balls 604 and 605 for connection are in desired locations.

  In particular, as in the first embodiment, since the wafer is cut last, the number of steps per package is reduced, and the cost can be reduced. In addition, the adhesive strength of the epoxy resin to the LSI can be obtained.

  In both the first and second embodiments, the bump is described as a stud bump. However, the present invention can be sufficiently carried out even if bumps by normal plating are used.

  In the first and second embodiments, a step of resin sealing after bump formation is used. However, after depositing the resin on the entire surface, it is also effective to remove the resin partly by a photolithography technique or the like according to a necessary part and to form a bump at the removed part by electroless plating or the like.

  10 to 12 are views showing a fourth embodiment of the present invention. FIG. 10 is a sectional view of a manufacturing process of a chip size package showing the fourth embodiment of the present invention (cross-sectional view taken along the line CC 'in FIG. 11). 11 is a plan view of the chip size package, and FIG. 12 is a perspective view of the chip size package.

  The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  Hereinafter, the manufacturing method of the chip size package will be described with reference to FIG.

  (1) First, as shown in FIG. 10A, a PSG film (oxide film) 100 for protecting the LSI 104 is formed. Since the bumps 304 and 305 connected to the aluminum electrodes 204 and 205 are manufactured by a wire bonding technique, the tips are constricted.

  The bump material is preferably gold or copper. Both can be made by conventional techniques. In particular, with respect to gold stud bumps, a manufacturing apparatus is also sold and can be manufactured without changing the previous process of LSI.

  In addition, for the copper bump, a gas atmosphere in which hydrogen is added to Ar is required for bonding, and the bonding pressure is slightly higher, so the thickness of the aluminum electrode of the LSI needs to be about 2 μm thicker than usual. By optimizing the conditions, it is possible to obtain good copper stud type aluminum.

  Recently, a technique for bonding a solder wire mainly composed of tin-lead to form a solder bump on an LSI aluminum electrode has been put into practical use. If this technique is used, the solder bumps 304 and 305 can be easily formed, and the process to continue further becomes easier.

  (2) Next, as shown in FIG. 10B, bumps 304 and 305 are formed on the aluminum electrodes 204 and 205 of all the LSIs 104, and after flattening the tip by pressing, a copper foil 1400 ( For example, a thickness of 15 μm) is brazed. The surface of the copper foil 1400 is preliminarily plated with tin or solder to a thickness of about 1 μm, and the plated film (not shown) and the bumps 304 and 305 are brazed at a low temperature.

  Next, an epoxy resin 1200 is injected between the copper foil 1400 and the PSG film 100 and cured by heating. As the resin, a resin having a low volume change rate before and after curing, such as Ecobond (trade name, manufactured by Emerson & Cumming) was used. Since the distance between the LSI 104 and the copper foil 1400 is around 40 μm, the resin 1200 can be efficiently and reliably filled with capillarity, and the adhesion between the LSI 104 surface and the copper foil 1400 surface was extremely good. . When the bump material is solder, the bump and the copper foil can be easily connected without previously plating the copper foil with tin, solder or the like.

  (3) Next, as shown in FIG. 10C, the copper foil 1400 was etched to form desired wiring metals 1404 and 1405 on the epoxy resin 1200. Etching of the copper foil 1400 is performed, for example, by coating the copper foil 1400 with a photosensitive dry film, performing a process such as exposure and development using a mask, and then selectively etching copper with a ferric chloride solution. went.

  (4) Next, after forming the wiring metals 1404 and 1405, the solder resist 1500 is applied to install the solder balls 604 and 605, and then the solder balls 604 and 605 are installed at predetermined positions.

  FIG. 11 shows a plan view of the chip size package thus obtained.

  In this figure, reference numerals 1401, 1402, 1403, 1404, 1405,... Are wiring metals made of copper foil formed on a resin 1200, and reference numerals 601, 602, 603, 604, 605,.

  Connection points (solder balls 601, 603,...) With external circuits are placed directly above the LSI aluminum electrodes 201, 203, 206, 208. The aluminum electrodes 202, 204, 205, 207 are connected to external circuits (solder balls 602, 604, 605) through wiring metals 1402, 1404, 1405,... Formed on the bumps 302, 304, 305, 307. , ...) is designed to move.

  After installing the solder balls 601, 602, 603, 604, 605,..., The wafer is cut along dotted lines C1, C3, C5, C2, C4, C6, C8 as shown in FIG. FIG. 12 shows the LSI 104 after cutting.

  Reference numeral 700 shown in FIG. 12 is a reinforcing plate for reinforcing this chip size package. This chip size package has sufficient strength because the surface is coated with an epoxy resin, but may require further strength before use. By sticking the reinforcing plate 700 before wafer cutting, it is possible to obtain a chip size package with the reinforcing plate 700 in a very small number of steps.

  Further, since the epoxy resin is applied to the surface of the semiconductor chip, it is possible to guarantee substantially the same reliability as a so-called resin mold.

  As shown in Non-Patent Documents 1 and 2, the conventional chip size package is packaged after LSI die-cutting. However, in the present invention, since all the packaging operations can be performed in units of wafers, man-hours can be reduced and the cost can be reduced.

  With regard to a conventional epoxy resin mold, a release agent has been added to the mold. This is for the purpose of preventing adhesion between the mold and the resin, but the adhesion force between the LSI and the surrounding metal is weakened, leading to a decrease in reliability.

  However, since the mold of the present invention does not use a mold, it is not necessary to add a release agent to the epoxy resin. Also, a silane coupling agent that promotes adhesion with the resin can be used effectively.

  The package of the present invention remains small and has the same reliability as a so-called mold package in terms of strength and moisture resistance.

  In the present invention, the bump has been described as a stud type. However, it is naturally possible to use bumps formed by ordinary plating, and other methods may be used. In addition, the material of the bump is not limited to copper, gold, tin-lead solder, and other materials can be used.

  Although the foil attached to the bumps on the entire surface of the wafer has been described as a copper foil, a good chip size package can be obtained even using a gold foil, a Kovar plate, or the like.

  Further, the connection to each bump can be made not by low-temperature brazing but by using high-temperature pressure welding, ultrasonic connection, or the like. In this case, solder plating, tin plating or the like is not required on the copper foil.

  Although the patterning of the copper foil has been described by the method using a dry film, a method such as a method of coating a resist can sufficiently cope with the patterning.

  Epoxy resin is injected between the copper foil and the LSI by capillary action, but other types of resins such as polyimide resin can be used.

  Although it has been described that the connection with the external circuit is performed by the solder ball, it is also possible to weld the metal piece to the planned connection place to form the connection terminal. Or you may apply | coat a conductive paint to a required location.

  In addition, this invention is not limited to the said Example, Based on the meaning of this invention, a various deformation | transformation is possible and these are not excluded from the scope of the present invention.

  The chip size package of the present invention can be used as an LSI package.

It is a top view of the wafer which shows 1st Example of this invention. FIG. 4 is a cross-sectional view of a manufacturing step of the semiconductor chip taken along the line AA ′ in FIG. 1. 1 is a perspective view of a chip size package showing a first embodiment of the present invention. It is a top view of the part used as the chip | tip of the wafer which shows 2nd Example of this invention. It is sectional drawing of the chip | tip of the wafer which shows 2nd Example of this invention (BB 'sectional view taken on the line of FIG. 4). It is a perspective view of the chip size package which shows 2nd Example of this invention. It is principal part sectional drawing of the chip size package at the time of forming the wiring metal which shows 3rd Example of this invention previously. It is a partially broken perspective view of the conventional chip size package. It is sectional drawing which shows a tape carrier system among the conventional chip size packages. FIG. 16 is a sectional view of a manufacturing process of a chip-size package showing the fourth embodiment of the present invention (cross-sectional view taken along the line CC ′ in FIG. 11). It is a top view of the chip size package which shows 4th Example of this invention. It is a perspective view of the chip size package which shows 4th Example of this invention.

Explanation of symbols

50,700 Reinforcement plate 100 PSG film (oxide film)
101, 102, 103, 104,... LSI (semiconductor chip)
200, 1200 Epoxy resin 201, 202, 203, 204, 205, 206, 207, 208 Electrode (aluminum)
301, 302, 303, 304, 305, 306, 307, 308, 804, 805,... Bump (Stud Bump)
401, 402, 403, 404, 405, 406, 407,..., 704, 705, 1401, 1402, 1403, 1404, 1405 Wiring metal 500, 1500 Solder resist 601, 602, 603, 604, 605,. Copper foil

Claims (12)

A semiconductor chip having a plurality of electrodes formed on the surface;
A bump formed using a stud method formed on the electrode;
A resin provided on the surface of the semiconductor chip so as to expose the upper surface of the bump formed using the stud method;
A wiring provided on the resin and electrically connected to the bump formed using the stud method;
A solder ball formed on the wiring and provided closer to the center of the semiconductor chip than the corresponding electrode ;
A chip size package characterized by including. In 1 Symbol mounting a chip size package claims, chip size package back surface of the semiconductor chip is characterized by exposed. 3. The chip size package according to claim 1, wherein the bump is made of gold. 3. The chip size package according to claim 1, wherein the bump is made of copper. In the chip size package according to any one of claims 1-4, chip size package, wherein the height of the bump is 30Myuemu～60myuemu. In the chip size package according to any one of claims 1 to 5 chip size package, wherein a protective film is provided between the surface and the resin of the semiconductor chip. In the chip size package according to any one of claims 1 to 6 chip size package, characterized in that said it has a bump tip constricted shape.   2. The chip size package according to claim 1, wherein a side surface of the semiconductor chip is exposed. 2. The chip size package according to claim 1, wherein a solder resist covering the wiring is formed. A semiconductor chip having a plurality of electrodes formed on the surface;
One end, and a narrow second end width than said one end, and gold bumps formed using a stud system wherein one end is connected on the electrode,
A wiring connected to the other end, the wiring extending from the corresponding electrode to the center side of the semiconductor chip; and
A resin formed between the surface of the semiconductor chip and the wiring;
A chip size package characterized by including. 11. The chip size package according to claim 10 , wherein a side surface of the semiconductor chip is exposed. 11. The chip size package according to claim 10 , wherein a solder resist that covers the wiring is formed.

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