JPH1092865A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH1092865A JPH1092865A JP8238786A JP23878696A JPH1092865A JP H1092865 A JPH1092865 A JP H1092865A JP 8238786 A JP8238786 A JP 8238786A JP 23878696 A JP23878696 A JP 23878696A JP H1092865 A JPH1092865 A JP H1092865A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- electrode
- resin
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子の集積回
路部を保護し、かつ外部装置と半導体素子の電気的接続
を安定に確保し、さらに最も高密度な実装を可能とした
半導体装置およびその製造方法に関するものである。本
発明により、情報通信機器、事務用電子機器、家庭用電
子機器、測定装置、組み立てロボット等の産業用電子機
器、医療用電子機器、電子玩具等の小型化を容易にする
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which protects an integrated circuit portion of a semiconductor device, stably secures an electrical connection between an external device and the semiconductor device, and which can be mounted at the highest density. It relates to a manufacturing method. Industrial Applicability The present invention facilitates miniaturization of industrial electronic devices such as information communication devices, office electronic devices, home electronic devices, measuring devices, and assembly robots, medical electronic devices, and electronic toys.
【０００２】[0002]
【従来の技術】以下、半導体装置としてＣＳＰ（チップ
・サイズ・パッケージ）タイプの半導体装置の従来例に
ついて図面を参照しながら説明する。図２３〜図２５
は、従来のＣＳＰタイプの半導体装置を示す図であり、
図２３は平面図、図２４は底面図、図２５は図２３のＡ
１−Ａ２間の断面図である。2. Description of the Related Art A conventional example of a CSP (chip size package) type semiconductor device will be described below with reference to the drawings. FIG. 23 to FIG. 25
FIG. 1 is a diagram showing a conventional CSP type semiconductor device;
23 is a plan view, FIG. 24 is a bottom view, and FIG.
It is sectional drawing between 1-A2.
【０００３】図２３〜図２５に示すように、半導体素子
１は、半導体キャリア２にフェイスダウンで搭載され、
金属突起３と導電性の接続材料４により電気的に接続さ
れている。さらに、半導体素子１と半導体キャリア２の
隙間は封止樹脂５により充填されている。また、半導体
キャリア２の表面電極６はビア７と内装電極８により裏
面電極９と電気的に接続される。As shown in FIGS. 23 to 25, a semiconductor element 1 is mounted face down on a semiconductor carrier 2;
The metal protrusion 3 is electrically connected to the conductive connection material 4. Further, a gap between the semiconductor element 1 and the semiconductor carrier 2 is filled with a sealing resin 5. The front surface electrode 6 of the semiconductor carrier 2 is electrically connected to the back surface electrode 9 by the via 7 and the internal electrode 8.
【０００４】図２３〜図２５に示したように、従来のＣ
ＳＰタイプの半導体装置は、搭載する半導体素子１に比
べて、半導体キャリア２が大きくなっている。これは、
マイコン等の外部電極端子数が多い半導体素子１を中心
にＣＳＰを構成したため、半導体キャリア２の底面の外
部端子数を十分に確保するためと、ＣＳＰ製造の封止工
程において封止樹脂５を半導体素子１と半導体キャリア
２との隙間に浸透させるために必要な樹脂の塗布エリア
を半導体素子１の存在しない半導体キャリア２の周辺部
にもたせていたからである。これらのことから、場合に
よっては半導体キャリア２の大きさが搭載する半導体素
子１の２倍程度の大きさになることも十分考えられる。As shown in FIGS. 23 to 25, a conventional C
In the semiconductor device of the SP type, the semiconductor carrier 2 is larger than the semiconductor element 1 to be mounted. this is,
Since the CSP is configured around the semiconductor element 1 having a large number of external electrode terminals such as a microcomputer, it is necessary to secure the number of external terminals on the bottom surface of the semiconductor carrier 2 and to use the sealing resin 5 in the sealing process of CSP manufacturing. This is because a resin application area required to permeate the gap between the element 1 and the semiconductor carrier 2 is provided in the peripheral portion of the semiconductor carrier 2 where the semiconductor element 1 does not exist. From these facts, in some cases, the size of the semiconductor carrier 2 may be about twice as large as the size of the semiconductor element 1 to be mounted.
【０００５】また、半導体素子１をＣＳＰ化する際に、
フリップチップ（ＦＣ）実装と称する極めて高度な技術
を用いており、フリップチップを行うための他材料への
制限と工程数の多さにより、製造コストがかなり高価な
ものになっている。When the semiconductor device 1 is formed into a CSP,
It uses a very advanced technology called flip chip (FC) mounting, and the manufacturing cost is considerably high due to the limitation on other materials and the large number of steps for performing flip chip.
【０００６】[0006]
【発明が解決しようとする課題】従来のＣＳＰタイプの
半導体装置においては、外部端子数であるピン数の特に
多いもの、あるいはウェハ状態で半導体素子の入手がで
きないものについては工法的にもコスト的にも十分であ
るが、ピン数の少ないＤＲＡＭ（ダイナミック・ランダ
ム・アクセス・メモリー）素子や汎用マイコン素子など
はＱＦＰ（ＴＳＯＰ）に対して、かなりコスト高になる
とともに、小型化のメリットもそれほど大きくなくなっ
てしまうという課題があった。In a conventional CSP type semiconductor device, a device having a particularly large number of pins as external terminals or a device in which a semiconductor element cannot be obtained in a wafer state is costly in terms of construction method. However, DRAM (Dynamic Random Access Memory) devices and general-purpose microcomputer devices with a small number of pins are considerably more expensive than QFP (TSOP), and the merits of miniaturization are so large. There was a problem that it disappeared.
【０００７】本発明は、製造コストを低減し、ピン数の
少ないＤＲＡＭや汎用マイコン等の半導体素子をより高
密度で実装した半導体装置およびその製造方法を提供す
ることを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which semiconductor elements such as a DRAM and a general-purpose microcomputer having a small number of pins are mounted at a higher density and a manufacturing method thereof is reduced.
【０００８】[0008]
【課題を解決するための手段】従来の課題を解決するた
め本発明の半導体装置は、半導体素子表面のパシベーシ
ョン膜上に前記半導体素子の素子電極部に相当する位置
に開口部を有する第１の樹脂層を有し、前記第１の樹脂
層上に前記半導体素子の前記素子電極部から配線される
金属配線を有し、前記金属配線上と前記第１の樹脂層上
に前記金属配線上の一部分に開口部を有する第２の樹脂
層を有し、前記第２の樹脂層の開口部に前記金属配線と
接続する金属電極を有するものである。In order to solve the conventional problems, a semiconductor device according to the present invention has a first structure in which an opening is formed on a passivation film on a surface of a semiconductor element at a position corresponding to an element electrode of the semiconductor element. A resin layer, and a metal wiring routed from the element electrode portion of the semiconductor element on the first resin layer, and a metal wiring on the metal wiring and on the first resin layer. A second resin layer having an opening in a part thereof is provided, and a metal electrode connected to the metal wiring is provided in the opening of the second resin layer.
【０００９】また半導体装置の製造方法においては、半
導体素子のパシベーション膜上に前記半導体素子の電極
部が開口部になるように第１の樹脂層を形成する工程
と、前記第１の樹脂層と前記電極の表層の一部をＯ2プ
ラズマにて削り取る工程と、前記第１の樹脂層上に前記
電極と接続する金属配線を形成する工程と、前記金属配
線上と前記第１の樹脂層上に前記金属配線上の一部に開
口部を有する第２の樹脂層を形成する工程と、前記開口
部に金属電極を形成する工程と、前記第１の樹脂層、前
記第２の樹脂層、前記金属配線および前記金属電極を形
成したウェハを裏面研磨およびダイシングする工程とか
らなるものである。In the method of manufacturing a semiconductor device, a step of forming a first resin layer on a passivation film of the semiconductor element so that an electrode portion of the semiconductor element becomes an opening; A step of shaving a part of the surface layer of the electrode with O 2 plasma, a step of forming a metal wiring connected to the electrode on the first resin layer, and a step of forming a metal wiring on the first resin layer. Forming a second resin layer having an opening in a part of the metal wiring, forming a metal electrode in the opening, the first resin layer, the second resin layer, Polishing and dicing the back surface of the wafer on which the metal wirings and the metal electrodes are formed.
【００１０】[0010]
【発明の実施の形態】前記構成の通り、チップ状態から
半導体装置を構成するものではなく、半導体素子が形成
された半導体ウェハ状態から半導体装置を構成すること
ができ、製造コスト的にも安価な工程を実現できるもの
である。また半導体装置においては、従来のような半導
体キャリアを用いた構造ではなく、高密度に構成された
ものである。そして半導体素子と外部基板との応力ひず
みに対しても、各樹脂層を介在させて対策しているの
で、信頼性上も優れた半導体装置である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, a semiconductor device can be formed not from a chip state but from a semiconductor wafer state on which semiconductor elements are formed, and the manufacturing cost is low. The process can be realized. Further, the semiconductor device has a high-density structure, instead of a conventional structure using a semiconductor carrier. Further, since the measures against stress and strain between the semiconductor element and the external substrate are provided by interposing each resin layer, the semiconductor device is excellent in reliability.
【００１１】以下、本発明の一実施形態について図面を
参照しながら説明する。第１の実施形態として、ＬＯＣ
（リード・オン・チップ）タイプのＤＲＡＭ素子をＣＳ
Ｐ構造にした場合について説明する。Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As a first embodiment, LOC
CS (lead-on-chip) type DRAM device
The case of the P structure will be described.
【００１２】図１は本実施形態のＣＳＰタイプの半導体
装置の平面図であり、図２は、図１のＢ１−Ｂ２箇所の
断面図である。以下、本実施形態の半導体装置の構造を
説明する。FIG. 1 is a plan view of a CSP type semiconductor device according to the present embodiment, and FIG. 2 is a sectional view taken along a line B1-B2 in FIG. Hereinafter, the structure of the semiconductor device of the present embodiment will be described.
【００１３】本実施形態の半導体装置は、外部との電気
的な接続は第２の樹脂層１０の開口部に位置するパッケ
ージ電極１１で行い、必要であればハンダボール等をそ
のパッケージ電極１１に付けるものである。半導体素子
１２の素子電極１３から引き出される金属配線１４は第
１の樹脂層１５上に形成され、この金属配線１４により
半導体素子１２の素子電極１３とパッケージ電極１１が
電気的に接続されている。また、パシベーション膜１６
上に形成されるポリイミド樹脂層１７、第１の樹脂層１
５および第２の樹脂層１０により、この半導体装置と外
部の実装基板とを実装した際に、その実装基板と半導体
素子１２のシリコン（Ｓｉ）との熱膨脹差によって生じ
る応力を緩和するものである。なお、第１の樹脂層１
５、第２の樹脂層１０は、エポキシ系ドライフィルムで
あるが、エポキシ系樹脂、シリコーン系樹脂、ポリイミ
ド系樹脂から選択した樹脂を用いるものである。なお、
金属配線１４、金属電極であるパッケージ電極１１の金
属には、銅（Ｃｕ）、アルミニウム（Ａｌ）、チタン
（Ｔｉ）、ニッケル（Ｎｉ）、金（Ａｕ）、クロム（Ｃ
ｒ）、パラジウム（Ｐｄ）、およびそれら金属の合金を
用いるものである。In the semiconductor device of this embodiment, the electrical connection with the outside is made by the package electrode 11 located at the opening of the second resin layer 10, and if necessary, a solder ball or the like is connected to the package electrode 11. It is something to attach. The metal wiring 14 drawn from the element electrode 13 of the semiconductor element 12 is formed on the first resin layer 15, and the element electrode 13 of the semiconductor element 12 and the package electrode 11 are electrically connected by the metal wiring 14. Also, the passivation film 16
Polyimide resin layer 17 formed on first resin layer 1
When the semiconductor device and an external mounting substrate are mounted, the stress caused by a difference in thermal expansion between the mounting substrate and silicon (Si) of the semiconductor element 12 is reduced by the fifth resin layer 10 and the second resin layer 10. . In addition, the first resin layer 1
5. The second resin layer 10 is an epoxy-based dry film, but uses a resin selected from an epoxy-based resin, a silicone-based resin, and a polyimide-based resin. In addition,
Copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni), gold (Au), chromium (C)
r), palladium (Pd), and alloys of these metals.
【００１４】次に図３〜図１３を参照して、本実施形態
の半導体装置の製造方法について説明する。なお、ここ
で本実施形態の半導体装置は、チップ状態から半導体装
置を構成するものではなく、半導体素子が形成された半
導体ウェハ状態から半導体装置を構成するものである。Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. Here, the semiconductor device of the present embodiment does not constitute a semiconductor device from a chip state, but constitutes a semiconductor device from a semiconductor wafer state on which semiconductor elements are formed.
【００１５】まず図３に示すように、半導体素子１２を
その表面に形成したシリコンよりなる半導体ウェハ１８
の表面全体にポリイミド層１７を形成し、素子電極１３
部とダイシング時のカットラインであるスクライブライ
ン部の除去を行い、パシベーション膜１６上にポリイミ
ド層を形成する。First, as shown in FIG. 3, a semiconductor wafer 18 made of silicon on which a semiconductor element 12 is formed is provided.
A polyimide layer 17 is formed on the entire surface of the
Then, a scribe line portion which is a cut line at the time of dicing is removed, and a polyimide layer is formed on the passivation film 16.
【００１６】次に図４に示すように、ポリイミド層１７
を形成した半導体ウェハ１８上にあらかじめフィルム状
に加工したエポキシ系ドライフィルム１９を貼り付け、
真空と熱により熱圧着させる。これにより第１の樹脂層
１５が形成される。Next, as shown in FIG.
An epoxy-based dry film 19 previously processed into a film is pasted on a semiconductor wafer 18 on which
Thermocompression bonding by vacuum and heat. Thereby, the first resin layer 15 is formed.
【００１７】次に図５に示すように、第１の樹脂層１５
上にレジスト塗布を行い、プリ硬化、パターン露光、現
像およびポスト硬化を行って、半導体ウェハ１８の第１
の樹脂層１５上にエッチング用のレジストマスク２０を
形成する。Next, as shown in FIG. 5, the first resin layer 15
A resist coating is performed on the semiconductor wafer, and pre-curing, pattern exposure, development, and post-curing are performed.
A resist mask 20 for etching is formed on the resin layer 15 of FIG.
【００１８】次に図６に示すように、前工程で形成した
レジストマスク２０を用いてエッチングを行い、マスク
開口部の第１の樹脂層１５を除去し、半導体素子１２の
素子電極１３を露出させる。Next, as shown in FIG. 6, etching is performed using the resist mask 20 formed in the previous step, the first resin layer 15 in the mask opening is removed, and the device electrode 13 of the semiconductor device 12 is exposed. Let it.
【００１９】次に図７に示すように、レジストマスク２
０の除去を行い、半導体ウェハ１８表面に第１の樹脂層
１５を露出させる。Next, as shown in FIG.
0 is removed to expose the first resin layer 15 on the surface of the semiconductor wafer 18.
【００２０】次に図８に示すように、半導体素子１２上
の素子電極１３のアルミニウム（Ａｌ）酸化膜（図示せ
ず）の除去と、第１の樹脂層１５の表面の粗面化を行う
ために、Ｏ2プラズマ２１を照射し、第１の樹脂層１５
の表面のプラズマエッチングを行う。Next, as shown in FIG. 8, the aluminum (Al) oxide film (not shown) of the device electrode 13 on the semiconductor device 12 is removed, and the surface of the first resin layer 15 is roughened. For this purpose, the first resin layer 15 is irradiated with an O 2 plasma 21.
Is subjected to plasma etching.
【００２１】次に図９に示すように、開口部を有する半
導体ウェハ１８の全面に蒸着により、金属薄膜２２を形
成する。Next, as shown in FIG. 9, a metal thin film 22 is formed on the entire surface of the semiconductor wafer 18 having an opening by vapor deposition.
【００２２】次に図１０に示すように、全面に金属薄膜
２２を形成した半導体ウェハ１８をエッチング、さらに
めっきを行うことにより金属配線１４を形成する。Next, as shown in FIG. 10, the metal wiring 14 is formed by etching and further plating the semiconductor wafer 18 having the metal thin film 22 formed on the entire surface.
【００２３】次に図１１に示すように、半導体ウェハ１
８表面に第２の樹脂層１０を形成する。Next, as shown in FIG.
The second resin layer 10 is formed on the surface of the substrate.
【００２４】そして図１２に示すように、金属配線１４
上に無電解めっき法によりパッケージ電極１１を形成
し、個々の半導体装置が完成する。Then, as shown in FIG.
A package electrode 11 is formed thereon by an electroless plating method, and individual semiconductor devices are completed.
【００２５】最後に図１３に示すように、半導体ウェハ
１８の裏面研磨と、半導体ウェハ１８のスクライブライ
ン２３のダイシングにより、個々の半導体装置２４を分
離する。Finally, as shown in FIG. 13, the individual semiconductor devices 24 are separated by polishing the back surface of the semiconductor wafer 18 and dicing the scribe lines 23 of the semiconductor wafer 18.
【００２６】以上のような工程により、ウェハ状態から
ＬＯＣ（リード・オン・チップ）タイプのＤＲＡＭ素子
のＣＳＰタイプの半導体装置を製造することができる。Through the above steps, a CSP type semiconductor device of a LOC (lead-on-chip) type DRAM element can be manufactured from the wafer state.
【００２７】次に図１４〜図１８を参照して、本実施形
態のＣＳＰタイプの半導体装置を製造するための第１の
樹脂層の形成工程の別の方法について説明する。Next, another method of forming a first resin layer for manufacturing the CSP type semiconductor device of the present embodiment will be described with reference to FIGS.
【００２８】まず図１４に示すように、半導体素子１２
を形成した半導体ウェハ１８全面に接着剤用樹脂２５を
塗布し、プリ硬化させる。First, as shown in FIG.
The resin 25 for adhesive is applied to the entire surface of the semiconductor wafer 18 on which is formed, and pre-cured.
【００２９】次に図１５に示すように、前工程で形成し
た接着剤用樹脂２５に対して、エポキシ系ドライフィル
ム１９を貼り付けポスト硬化して接着させる。Next, as shown in FIG. 15, an epoxy-based dry film 19 is attached to the adhesive resin 25 formed in the previous step by post-curing and bonding.
【００３０】次に図１６に示すように、半導体ウェハ１
８の半導体素子１２の素子電極１３部に開口部ができる
ようにエッチング用のレジストマスク２０をエポキシ系
ドライフィルム１９上に形成する。Next, as shown in FIG.
A resist mask 20 for etching is formed on the epoxy-based dry film 19 so that an opening is formed in the element electrode 13 of the semiconductor element 12 of FIG.
【００３１】次に図１７に示すように、エッチングによ
り、マスク開口部下のエポキシ系ドライフィルム１９と
接着剤用樹脂２５を除去し、パシベーション膜１６上に
接着剤用樹脂２５、エポキシ系ドライフィルム１９を形
成する。Next, as shown in FIG. 17, the epoxy dry film 19 and the adhesive resin 25 under the mask opening are removed by etching, and the adhesive resin 25 and the epoxy dry film 19 are formed on the passivation film 16. To form
【００３２】最後に図１８に示すように、レジストマス
ク２０を除去し、パシベーション膜１６上に接着剤用樹
脂２５、エポキシ系ドライフィルム１９よりなる第１の
樹脂層１５を形成する。Finally, as shown in FIG. 18, the resist mask 20 is removed, and a first resin layer 15 made of an adhesive resin 25 and an epoxy dry film 19 is formed on the passivation film 16.
【００３３】以上、図１４〜図１８に示したような工程
により、接着剤用樹脂を用いて第１の樹脂層１５を形成
することができる。As described above, the first resin layer 15 can be formed using the adhesive resin by the steps shown in FIGS.
【００３４】次に図１９〜図２２を参照して、本実施形
態のＣＳＰタイプの半導体装置を製造するための第１の
樹脂層の形成工程の別の方法について説明する。Next, another method of forming the first resin layer for manufacturing the CSP type semiconductor device of this embodiment will be described with reference to FIGS.
【００３５】まず図１９に示すように、半導体素子１２
が形成された半導体ウェハ１８全体にエポキシ系ドライ
フィルム１９を貼り付け、真空圧と熱により熱圧着させ
る。First, as shown in FIG.
An epoxy-based dry film 19 is attached to the entire semiconductor wafer 18 on which is formed, and thermocompression-bonded by vacuum pressure and heat.
【００３６】次に図２０に示すように、半導体素子１２
の素子電極１３部に開口部ができるようにエッチング用
のレジストマスク２０をエポキシ系ドライフィルム１９
上に形成する。Next, as shown in FIG.
An etching resist mask 20 is formed on the epoxy-based dry film 19 so that an opening is formed in the device electrode 13.
Form on top.
【００３７】そして図２１に示すように、エッチングに
より、マスク開口部下のエポキシ系ドライフィルム１９
を除去し、パシベーション膜１６上にのみエポキシ系ド
ライフィルム１９を残存させる。Then, as shown in FIG. 21, the epoxy dry film 19 under the mask opening is etched.
Is removed, and the epoxy-based dry film 19 is left only on the passivation film 16.
【００３８】最後に図２２に示すように、レジストマス
ク２０を除去し、第１の樹脂層１５を形成する。Finally, as shown in FIG. 22, the resist mask 20 is removed, and a first resin layer 15 is formed.
【００３９】以上のようにこの方法は、ポリイミド樹脂
層なしの第１の樹脂層１５を形成するものである。As described above, this method forms the first resin layer 15 without the polyimide resin layer.
【００４０】以上、本実施形態は、チップ状態から半導
体装置を構成するものではなく、半導体素子が形成され
た半導体ウェハー状態から半導体装置を構成することが
でき、製造コスト的にも安価な工程を実現できるもので
ある。また半導体装置においては、従来のような半導体
キャリアを用いた構造ではなく、高密度に構成されたも
のである。そして半導体素子と外部基板との応力ひずみ
に対しても、各樹脂層を介在させて対策しているので、
信頼性上も優れた半導体装置である。As described above, the present embodiment does not constitute a semiconductor device from a chip state, but can constitute a semiconductor device from a semiconductor wafer state on which semiconductor elements are formed. It can be realized. Further, the semiconductor device has a high-density structure, instead of a conventional structure using a semiconductor carrier. Also, since the stress and strain between the semiconductor element and the external substrate are dealt with by interposing each resin layer,
The semiconductor device is also excellent in reliability.
【００４１】[0041]
【発明の効果】以上、本発明のような構造を取ることに
より、ピン数の少ないＤＲＡＭや汎用マイコン等の半導
体素子がより高密度に実装できるようになる。また、Ｃ
ＳＰタイプの半導体装置の製造をウェハ単位で一括して
行うので、低コストで供給することができる。またパッ
ケージ電極の下にヤング率の小さい樹脂層を形成してい
るので、外部基板との実装時の熱膨脹差によって生じる
応力を緩和することができる半導体装置である。As described above, by adopting the structure according to the present invention, semiconductor elements such as DRAMs and general-purpose microcomputers having a small number of pins can be mounted at a higher density. Also, C
Since the manufacture of the SP type semiconductor device is performed collectively for each wafer, the semiconductor device can be supplied at low cost. In addition, since a resin layer having a small Young's modulus is formed under the package electrode, the semiconductor device can reduce stress caused by a difference in thermal expansion during mounting with an external substrate.
【図１】本発明の一実施形態の半導体装置を示す平面図FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態の半導体装置を示す断面図FIG. 2 is a sectional view showing a semiconductor device according to one embodiment of the present invention;
【図３】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 3 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図４】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 4 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図５】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 5 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図６】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 6 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図７】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 7 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図８】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 8 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図９】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 9 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１０】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 10 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１１】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 11 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１２】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 12 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１３】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 13 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１４】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 14 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１５】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 15 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１６】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 16 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１７】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 17 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１８】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 18 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図１９】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 19 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図２０】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 20 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図２１】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 21 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図２２】本発明の一実施形態の半導体装置の製造方法
を示す断面図FIG. 22 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図２３】従来の半導体装置を示す平面図FIG. 23 is a plan view showing a conventional semiconductor device.
【図２４】従来の半導体装置を示す底面図FIG. 24 is a bottom view showing a conventional semiconductor device.
【図２５】従来の半導体装置を示す断面図FIG. 25 is a sectional view showing a conventional semiconductor device.
１ 半導体素子 ２ 半導体キャリア ３ 金属突起 ４ 接続材料 ５ 封止樹脂 ６ 表面電極 ７ ビア ８ 内装電極 ９ 裏面電極 １０ 第２の樹脂層 １１ パッケージ電極 １２ 半導体素子 １３ 素子電極 １４ 金属配線 １５ 第１の樹脂層 １６ パシベーション膜 １７ ポリイミド樹脂層 １８ 半導体ウェハ １９ エポキシ系ドライフィルム ２０ レジストマスク ２１ Ｏ2プラズマ ２２ 金属薄膜 ２３ スクライブライン ２４ 半導体装置 ２５ 接着剤用樹脂DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Semiconductor carrier 3 Metal projection 4 Connection material 5 Sealing resin 6 Front electrode 7 Via 8 Interior electrode 9 Back electrode 10 Second resin layer 11 Package electrode 12 Semiconductor element 13 Element electrode 14 Metal wiring 15 First resin layer 16 passivation film 17 of polyimide resin layer 18 semiconductor wafer 19 epoxy-based dry film 20 resist mask 21 O 2 plasma 22 metal thin film 23 scribe line 24 semiconductor devices for resin 25 adhesive
Claims (8)
前記半導体素子の素子電極部に相当する位置に開口部を
有する第１の樹脂層を有し、前記第１の樹脂層上に前記
半導体素子の前記素子電極部から配線される金属配線を
有し、前記金属配線上と前記第１の樹脂層上に前記金属
配線上の一部分に開口部を有する第２の樹脂層を有し、
前記第２の樹脂層の開口部に前記金属配線と接続する金
属電極を有することを特徴とする半導体装置。A first resin layer having an opening at a position corresponding to an element electrode portion of the semiconductor element on a passivation film on a surface of the semiconductor element; and a first resin layer having an opening on the first resin layer. A second resin layer having a metal wiring routed from the element electrode portion and having an opening on a part of the metal wiring on the metal wiring and on the first resin layer;
A semiconductor device having a metal electrode connected to the metal wiring in an opening of the second resin layer.
リイミド系樹脂、エポキシ系樹脂、シリコーン系樹脂の
中から選択した樹脂であることを特徴とする請求項１記
載の半導体装置。2. The semiconductor device according to claim 1, wherein the first resin layer and the second resin layer are resins selected from a polyimide resin, an epoxy resin, and a silicone resin.
は、銅、アルミニウム、チタン、ニッケル、金、クロ
ム、パラジウム、および前記金属の合金の中から選択し
た金属であることを特徴とする請求項１記載の半導体装
置。3. The metal used for the metal wiring and metal electrode is a metal selected from copper, aluminum, titanium, nickel, gold, chromium, palladium, and alloys of the metals. 13. The semiconductor device according to claim 1.
半導体素子の電極部が開口部になるように第１の樹脂層
を形成する工程と、前記第１の樹脂層と前記電極の表層
の一部をＯ2プラズマにて削り取る工程と、前記第１の
樹脂層上に前記電極と接続する金属配線を形成する工程
と、前記金属配線上と前記第１の樹脂層上に前記金属配
線上の一部に開口部を有する第２の樹脂層を形成する工
程と、前記開口部に金属電極を形成する工程と、前記第
１の樹脂層、前記第２の樹脂層、前記金属配線および前
記金属電極を形成したウェハを裏面研磨およびダイシン
グする工程とからなることを特徴とする半導体装置の製
造方法。4. A step of forming a first resin layer on a passivation film of a semiconductor element such that an electrode of the semiconductor element becomes an opening, and a part of the first resin layer and a surface layer of the electrode. Shaving the metal wiring with O 2 plasma, forming a metal wiring connected to the electrode on the first resin layer, and removing one of the metal wiring on the metal wiring and the first resin layer. Forming a second resin layer having an opening in a portion, forming a metal electrode in the opening, forming the first resin layer, the second resin layer, the metal wiring, and the metal electrode Polishing the wafer on which the substrate is formed and dicing the back surface.
素子の形成されたウェハ上に樹脂を塗布する工程と、前
記樹脂を硬化する工程と、樹脂層を形成した前記ウェハ
上に予め形成された樹脂フィルムを貼り付ける工程と、
前記樹脂フィルム上に前記半導体素子の電極を有する位
置に開口部を有するレジスト膜を形成する工程と、前記
ウェハの前記レジストの前記開口部に相当する位置の前
記樹脂層および前記樹脂フィルムをエッチングにより除
去する工程と、前記レジスト層を除去する工程とを有す
ることを特徴とする請求項４記載の半導体装置の製造方
法。5. The step of forming a first resin layer includes a step of applying a resin on a wafer on which semiconductor elements are formed, a step of curing the resin, and a step of forming a resin layer on the wafer in advance. Attaching a formed resin film,
Forming a resist film having an opening at a position having the electrode of the semiconductor element on the resin film, and etching the resin layer and the resin film at a position corresponding to the opening of the resist on the wafer by etching; 5. The method according to claim 4, further comprising a step of removing the resist layer and a step of removing the resist layer.
素子の形成されたウェハ上に電極部が開口部になるよう
にポリイミド樹脂層を形成する工程と、前記ポリイミド
樹脂層を形成した前記ウェハ上に予め形成された樹脂フ
ィルムを貼り付ける工程と、前記樹脂フィルム上に前記
半導体素子の電極を有する位置に開口部を有するレジス
ト膜を形成する工程と、前記ウェハの前記レジストの前
記開口部に相当する位置の前記樹脂層および前記樹脂フ
ィルムをエッチングにより除去する工程と、前記レジス
ト層を除去する工程とを有することを特徴とする請求項
４記載の半導体装置の製造方法。6. The step of forming a first resin layer includes forming a polyimide resin layer on a wafer on which semiconductor elements are formed so that an electrode portion becomes an opening, and forming the polyimide resin layer. A step of attaching a resin film previously formed on the wafer, a step of forming a resist film having an opening at a position having an electrode of the semiconductor element on the resin film, and a step of forming the resist film on the wafer. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising: a step of removing the resin layer and the resin film at positions corresponding to the portions by etching; and a step of removing the resist layer.
素子の形成されたウェハ上に予め形成された樹脂フィル
ムを貼り付ける工程と、前記樹脂フィルム上に前記半導
体素子の電極を有する位置に開口部を有するレジスト膜
を形成する工程と、前記ウェハの前記レジストの前記開
口部に相当する位置の前記樹脂層および前記樹脂フィル
ムをエッチングにより除去する工程と、前記レジスト層
を除去する工程とを有することを特徴とする請求項４記
載の半導体装置の製造方法。7. The step of forming the first resin layer includes the step of attaching a resin film formed in advance on a wafer on which a semiconductor element is formed, and the step of forming a position having an electrode of the semiconductor element on the resin film. Forming a resist film having an opening in the wafer, removing the resin layer and the resin film at a position corresponding to the opening in the resist of the wafer by etching, and removing the resist layer. 5. The method for manufacturing a semiconductor device according to claim 4, comprising:
法、またはめっき法を用いることを特徴とする請求項４
記載の半導体装置の製造方法。8. The method according to claim 4, wherein the metal wiring and the metal electrode are formed by a vapor deposition method or a plating method.
The manufacturing method of the semiconductor device described in the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23878696A JP3402086B2 (en) | 1996-09-10 | 1996-09-10 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23878696A JP3402086B2 (en) | 1996-09-10 | 1996-09-10 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1092865A true JPH1092865A (en) | 1998-04-10 |
| JP3402086B2 JP3402086B2 (en) | 2003-04-28 |
Family
ID=17035269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23878696A Expired - Fee Related JP3402086B2 (en) | 1996-09-10 | 1996-09-10 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3402086B2 (en) |
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| KR100319624B1 (en) * | 1999-05-20 | 2002-01-09 | 김영환 | Semiconductor chip package and method for fabricating thereof |
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