JP2002261192A - Wafer level csp - Google Patents
Wafer level cspInfo
- Publication number
- JP2002261192A JP2002261192A JP2001057277A JP2001057277A JP2002261192A JP 2002261192 A JP2002261192 A JP 2002261192A JP 2001057277 A JP2001057277 A JP 2001057277A JP 2001057277 A JP2001057277 A JP 2001057277A JP 2002261192 A JP2002261192 A JP 2002261192A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- wafer level
- level csp
- electrode
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Formation Of Insulating Films (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体素子を収納す
る小型パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small package for housing a semiconductor device.
【0002】[0002]
【従来の技術】携帯電話,デジタルカメラなど電子携帯
機器は,小型,軽量化のニーズが高く,電子機器を構成す
る電子部品は,より小さく,より薄く,より軽いものが要
求される。現在,小型携帯電子機器において,BGA,CSPと
いった小型パッケージが適用されており,今後,ベアチッ
プ実装あるいはウエハレベルで組立が可能なチップスケ
ールの超小型パッケージが導入されることが予想され
る。特に,ウエハレベルで形成されるCSPチップサイズパ
ッケージ、またはチップスケールパッケージは,BGA,CSP
と同程度の信頼性を有し,ベアチップよりも取り扱いが
容易であるため,次世代のパッケージとして注目され
る。2. Description of the Related Art There is a great need for smaller and lighter electronic portable devices such as mobile phones and digital cameras, and smaller, thinner and lighter electronic components are required for electronic devices. At present, small packages such as BGA and CSP are applied to small portable electronic devices, and it is expected that a chip-scale ultra-small package that can be mounted on a bare chip or assembled at a wafer level will be introduced in the future. In particular, CSP chip size packages formed at the wafer level or chip scale packages are BGA, CSP
It has the same level of reliability and is easier to handle than bare chips, so it is attracting attention as a next-generation package.
【0003】代表的なウエハレベルCSPの断面構造を
図5に示す。その製造方法は,次に示すプロセスで製造さ
れる。ウエハプロセスが終了した半導体基板15をバック
グラインドで500um程度まで研削し,半導体基板15上にポ
リイミドなどの保護膜17を形成し,電極パッド16および
その他の必要部分を開口させる。次に銅の再配線層18を
メッキ法によって形成し,電極をアレイ状に再配置す
る。外部接続用の電極を形成するためメッキ法で銅ポス
ト19を形成し,次に,モールド樹脂20を封止する。最後に
基板実装用のバンプ電極21をボールマウンターもしくは
スクリーン印刷で形成する。従来は,以上の方法で,ウエ
ハレベルのCSPの製造が行なわれてきた。FIG. 5 shows a cross-sectional structure of a typical wafer level CSP. The manufacturing method is manufactured by the following process. After the wafer process is completed, the semiconductor substrate 15 is ground to about 500 μm by back grinding, a protective film 17 such as polyimide is formed on the semiconductor substrate 15, and the electrode pads 16 and other necessary parts are opened. Next, a copper redistribution layer 18 is formed by plating, and the electrodes are rearranged in an array. Copper posts 19 are formed by plating to form electrodes for external connection, and then the mold resin 20 is sealed. Finally, a bump electrode 21 for mounting the substrate is formed by a ball mounter or screen printing. Conventionally, wafer-level CSP has been manufactured by the above method.
【0004】[0004]
【発明が解決しようとする課題】しかし,前記ウエハレ
ベルCSPにおいては,外部接続用の電極を形成するた
めに,銅のポストを形成させる必要がある。銅ポストは,
バンプ電極または実装基板と接続するためポスト面は完
全に銅を露出させる必要があるが,銅ポストは,メッキ形
成されるためポストのバラツキが生じ,ポスト面にモー
ルド樹脂が付着し半田ボールとの接合信頼性が低下する
問題が生じる。また,ポストのバラツキを吸収するため
には,モールド装置のトランスファ圧力を高精度にし,さ
らに特殊フィルムを使用する必要があり,パッケージの
製造コストが高くなってしまうという問題が生じる。さ
らに,銅ポストがモールド樹脂の流動抵抗となり樹脂が
ウエハ面上に均一に拡がらず,樹脂の未充填が生じ,組立
歩留りが低下する問題を引き起こす。However, in the wafer level CSP, it is necessary to form a copper post in order to form an electrode for external connection. Copper post
It is necessary to completely expose the copper on the post surface in order to connect to the bump electrode or the mounting board.However, the copper post is plated and formed, causing variations in the post. There is a problem that the joining reliability is reduced. In addition, in order to absorb the variation of the posts, it is necessary to make the transfer pressure of the molding device highly accurate and to use a special film, which causes a problem that the manufacturing cost of the package increases. In addition, the copper post causes the flow resistance of the mold resin, and the resin does not spread evenly on the wafer surface, causing unfilled resin, which causes a problem of lowering the assembly yield.
【0005】また,基板接合用のバンプ電極はモールド
樹脂封止側の銅ポスト上に形成するためバンプ電極の形
成は,電解メッキ法が使用できず,ボールマウントあるい
はスクリーン印刷法により行われる。そのため,100um以
下の狭ピッチバンプ電極の形成は困難になる。[0005] Further, since the bump electrode for bonding the substrate is formed on the copper post on the mold resin sealing side, the bump electrode cannot be formed by electrolytic plating, but is formed by ball mounting or screen printing. Therefore, it is difficult to form a narrow pitch bump electrode of 100 μm or less.
【0006】本発明のウエハレベルCSPは,基板接合用の
電極をウエハ裏面に形成し,銅ポストを使用しない構造
である。また,基板実装用の電極がモールド封止面にな
いため,上記課題をすべて解消することができる。[0006] The wafer level CSP of the present invention has a structure in which electrodes for substrate bonding are formed on the back surface of the wafer and no copper posts are used. In addition, since there is no substrate mounting electrode on the mold sealing surface, all of the above problems can be solved.
【0007】[0007]
【課題を解決するための手段】本発明のウエハレベルC
SPは,ウエハ裏面側に基板実装用の電極を有し,その構
造は,スクライブライン上の特定箇所に形成したスルー
ホールの側面を利用して,ウエハ表裏間の電気接合をと
ることで実現する。スルーホールはシリコン基板のスク
ライブライン上をハーフエッチングした凹部をバックグ
ラインドを用いて裏面研磨することで形成される。SUMMARY OF THE INVENTION Wafer level C of the present invention
SP has a substrate mounting electrode on the back side of the wafer, and its structure is realized by making electrical connection between the front and back of the wafer using the side of the through hole formed at a specific location on the scribe line . The through-hole is formed by polishing the back surface of the concave portion obtained by half-etching the scribe line on the silicon substrate using back grinding.
【0008】[0008]
【作用】前記手段によって,樹脂封止を行う半導体回路
側には,基板接続用の電極が存在しないため,銅ポスト形
成が不要で,さらに特殊フィルムを使用する必要がな
い。ポストによる樹脂の流動抵抗もなくなり,モールド
時の未充填不良が解消される。また、基板接続用の電極
がモールド封止面にないため,バンプ形成は,半田ボール
マウント,スクリーン印刷法のほか電解メッキ法が適用
でき,100um以下の狭ピッチ対応のバンプ形成が可能にな
る。According to the above-mentioned means, since there is no electrode for connecting the substrate on the side of the semiconductor circuit to be resin-sealed, there is no need to form a copper post, and there is no need to use a special film. The flow resistance of the resin due to the post is also eliminated, and the unfilling failure at the time of molding is eliminated. In addition, since there is no electrode for connecting the substrate on the mold sealing surface, the bump can be formed by an electroplating method in addition to a solder ball mount and a screen printing method, and a bump corresponding to a narrow pitch of 100 μm or less can be formed.
【0009】[0009]
【発明の実施の形態】次に,本発明の実施例を図面を参
照しながら説明する。図1は,本発明の第1実施例を表し
た上面図で,図2から図4は断面図である。第1実施例の
ウエハレベルCSPの構造を図面を参照しながら説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a top view showing a first embodiment of the present invention, and FIGS. 2 to 4 are sectional views. The structure of the wafer level CSP of the first embodiment will be described with reference to the drawings.
【0010】パッケージ組立に用いられる半導体回路形
成後のウエハは,図2(a)に示すように,半導体基板1に電
極パッド2が形成され,電極パット2の上層にチッ化シリ
コンなどの保護膜3が電極パッド2およびスクライブラ
イン4上を除く部分に形成した形態とする。As shown in FIG. 2A, the wafer after the formation of the semiconductor circuit used for the package assembly has an electrode pad 2 formed on a semiconductor substrate 1 and a protective film such as silicon nitride on the electrode pad 2. 3 is formed in a portion except on the electrode pad 2 and the scribe line 4.
【0011】第1の工程は,図2(b)に示すようにスク
ライブラインエリアの特定箇所にハーフエッチング箇所
5を選択的にウエットエッチングし,約50〜100um深さの
凹部を形成する。In the first step, as shown in FIG. 2B, a half-etched portion 5 is selectively wet-etched at a specific portion of the scribe line area to form a concave portion having a depth of about 50 to 100 μm.
【0012】次に図2(c)に示すようにポリイミドな
どの絶縁膜6をウエハ全面に形成し,図2(d)に示す
ように電極パッド2およびスクライブライン上のハーフ
エッチング箇所5を選択的に開口させる。Next, as shown in FIG. 2C, an insulating film 6 of polyimide or the like is formed on the entire surface of the wafer, and as shown in FIG. 2D, the electrode pads 2 and the half-etched portions 5 on the scribe lines are selected. And make it open.
【0013】次に,2000Å〜5000Å厚さの銅をスパッタ
リングにより成膜した後,図3(a)に示すようにレジ
スト7を所望形状にパターニングし,図3(b)に示す
厚さ約20〜50um程度の銅,アルミなどの金属配線層8を
メッキ法によって形成させ,その上層に必要に応じて,ポ
リイミドなどの絶縁層9を全面に形成させる。Next, after a copper film having a thickness of 2000 to 5000 mm is formed by sputtering, a resist 7 is patterned into a desired shape as shown in FIG. A metal wiring layer 8 of about 50 μm of copper, aluminum or the like is formed by plating, and an insulating layer 9 of polyimide or the like is formed over the entire surface as necessary.
【0014】次に図3(c)に示すように半導体回路の
保護,パッケージのハンドリング,放熱性などを向上させ
る目的でトランスファモールドあるいはポッティングな
どで厚さ30um〜100um程度のモールド樹脂10を半導体
回路側全面に封止する。Next, as shown in FIG. 3C, a mold resin 10 having a thickness of about 30 μm to 100 μm is transferred to the semiconductor circuit by transfer molding or potting for the purpose of protecting the semiconductor circuit, handling the package, and improving heat dissipation. Seal the entire side.
【0015】次に,図3(d)に示すようにシリコン基
板1を実装用途に従い,厚さ20um〜200umにバックグライ
ンドする。Next, as shown in FIG. 3D, the silicon substrate 1 is back ground to a thickness of 20 μm to 200 μm according to the mounting application.
【0016】次に図4(a)に示すように,半導体基板1
の研削面にポリイミドなどの絶縁膜11を成膜した後,
所望形状にパターニングする図4(b)。次に,銅など
の金属膜をウエハ裏面全面にスパッタなどの方法で成膜
した後,レジストパターニングし,図4(c)に示すよう
に厚さ10〜50um程度の電極パッド12を半導体基板1の
裏面にメッキなどの方法で形成する。Next, as shown in FIG.
After forming an insulating film 11 such as polyimide on the ground surface of
FIG. 4B illustrates patterning into a desired shape. Next, after a metal film such as copper is formed on the entire back surface of the wafer by a method such as sputtering, resist patterning is performed, and an electrode pad 12 having a thickness of about 10 to 50 μm is formed on the semiconductor substrate 1 as shown in FIG. Is formed on the back surface by plating or the like.
【0017】最後に,図5に示すようにスクライブライ
ンの中心をスクライブ幅の50%程度の切りしろでダイシ
ングしパッケージを個片にする。上述の方法で,半導体
基板1の裏面に実装用の電極パッド12するウエハレベ
ルのパッケージを提供することができる。Finally, as shown in FIG. 5, the center of the scribe line is diced with a margin of about 50% of the scribe width to make a package. With the above-described method, a wafer-level package having the mounting electrode pads 12 on the back surface of the semiconductor substrate 1 can be provided.
【0018】次に,本発明の第二の実施例について説明
する。図6は,本発明の第2実施例を表した断面図であ
る。半導体基板1の表面の一部に電極パッド2を形成
し、電極パッド2の周囲に保護膜3と、保護膜3の上に
絶縁膜6が形成され、最上層に絶縁膜9が形成されてい
る。そして半導体基板1の裏面の一部に、絶縁膜11と
電極パッドが形成されている。図6に示すように,第2
の実施例は,モールド樹脂封止を行なわない構造のため,
パッケージの厚さを100um以下にすることができ,ICカー
ドなど用途に対応することができる。Next, a second embodiment of the present invention will be described. FIG. 6 is a sectional view showing a second embodiment of the present invention. An electrode pad 2 is formed on a part of the surface of the semiconductor substrate 1, a protective film 3 is formed around the electrode pad 2, an insulating film 6 is formed on the protective film 3, and an insulating film 9 is formed on the uppermost layer. I have. An insulating film 11 and an electrode pad are formed on a part of the back surface of the semiconductor substrate 1. As shown in FIG.
In the embodiment of the present invention, the structure does not perform molding resin sealing.
The thickness of the package can be reduced to 100um or less, and it can be used for applications such as IC cards.
【0019】次に,本発明の第3の実施例について説明
する。図7は,本発明の第3の実施例を表した断面図であ
る。図7に示すように,第3の実施例は,ウエハ裏面の実装
用電極パッドにボールマウント法,スクリーン印刷法ほ
か電界メッキ法によってバンプ電極13が形成できるた
め,100um以下の狭ピッチのバンプ形成を可能にする。こ
の時は,ウエハ裏面に形成した絶縁膜をエラストマなど
の緩衝材14を代替えに使用すると実装基板とバンプ間
の応力を吸収し,実装時の信頼性が向上する。Next, a third embodiment of the present invention will be described. FIG. 7 is a sectional view showing a third embodiment of the present invention. As shown in FIG. 7, in the third embodiment, the bump electrodes 13 can be formed on the mounting electrode pads on the back surface of the wafer by a ball mounting method, a screen printing method, or an electrolytic plating method. Enable. At this time, if the insulating film formed on the back surface of the wafer is used as a buffer material 14 such as an elastomer, the stress between the mounting substrate and the bumps is absorbed, and the reliability at the time of mounting is improved.
【0020】[0020]
【発明の効果】本発明のウエハレベルCSPは,外部接
続用の電極を形成するための銅のポストを形成させる必
要がなく,ポストのバラツキを吸収させるためのモール
ド装置の改良,特殊フィルムの使用する必要がなくなり,
パッケージの製造コストが低くできる。銅ポストがない
ためモールド樹脂が流動抵抗を受けずにウエハ面上に均
一に拡がるため,樹脂の未充填が生じず,組立歩留りが向
上する。また,基板接合用のバンプはモールド樹脂封止
面側にないため,電解メッキ法によるバンプ形成ができ,
100um以下の狭ピッチバンプ電極の形成が可能になる。According to the wafer level CSP of the present invention, there is no need to form a copper post for forming an electrode for external connection, and an improved molding device for absorbing the variation of the post and the use of a special film are used. There is no need to
The manufacturing cost of the package can be reduced. Since there is no copper post, the mold resin spreads evenly on the wafer surface without receiving flow resistance, so that no resin is filled, and the assembly yield is improved. In addition, since there is no bump for substrate bonding on the mold resin sealing surface side, bumps can be formed by electrolytic plating.
It is possible to form a narrow pitch bump electrode of 100 μm or less.
【図1】第一の実施例の半導体装置の上面図。FIG. 1 is a top view of a semiconductor device according to a first embodiment.
【図2】第一の実施例の半導体装置の断面図。FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment.
【図3】第一の実施例の半導体装置の断面図。FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment.
【図4】第一の実施例の半導体装置の断面図。FIG. 4 is a sectional view of the semiconductor device according to the first embodiment;
【図5】第一の実施例の半導体装置の断面図。FIG. 5 is a sectional view of the semiconductor device according to the first embodiment;
【図6】第二の実施例の半導体装置の断面図。FIG. 6 is a sectional view of a semiconductor device according to a second embodiment.
【図7】第三の実施例の半導体装置の断面図。FIG. 7 is a sectional view of a semiconductor device according to a third embodiment.
【図8】従来のウエハレベルCSPの断面図。FIG. 8 is a sectional view of a conventional wafer level CSP.
1・・・・・・半導体基板 2・・・・・・電極パッド 3・・・・・・保護膜 4・・・・・・スクライブエリア 5・・・・・・ハーフエッチング箇所 6・・・・・絶縁膜 7・・・・・レジスト 8・・・・・金属配線層 9・・・・・絶縁層 10・・・・・モールド樹脂 11・・・・・絶縁膜 12・・・・・電極パッド 13・・・・・バンプ電極 14・・・・・緩衝材 15・・・・・半導体基板 16・・・・・電極パッド 17・・・・・保護膜 18・・・・・再配線層 19・・・・・銅ポスト 20・・・・・モールド樹脂 21・・・・・バンプ電極 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Electrode pad 3 ... Protective film 4 ... Scribe area 5 ... Half-etched location 6 ... .... Insulating film 7 ... Resist 8 ... Metal wiring layer 9 ... Insulating layer 10 ... Mold resin 11 ... Insulating film 12 ... Electrode pad 13 ... Bump electrode 14 ... Buffer material 15 ... Semiconductor substrate 16 ... Electrode pad 17 ... Protective film 18 ... Rewiring Layer 19: Copper post 20: Mold resin 21: Bump electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/768 H01L 21/90 B 21/60 21/92 604M 604A 604R Fターム(参考) 5F033 HH08 HH11 JJ01 JJ08 JJ11 KK08 KK11 MM30 PP27 QQ07 QQ09 QQ37 QQ47 RR22 TT07 VV07 XX34 5F043 AA01 FF06 GG03 5F058 AA10 AB10 AC02 AH05 5F061 AA02 BA07 CA04 CA21 FA06──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/768 H01L 21/90 B 21/60 21/92 604M 604A 604R F term (Reference) 5F033 HH08 HH11 JJ01 JJ08 JJ11 KK08 KK11 MM30 PP27 QQ07 QQ09 QQ37 QQ47 RR22 TT07 VV07 XX34 5F043 AA01 FF06 GG03 5F058 AA10 AB10 AC02 AH05 5F061 AA02 BA07 CA04 CA21 FA06
Claims (8)
有することを特徴とするウエハレベルCSP。1. A wafer level CSP having an electrode for bonding a substrate on a back surface of a semiconductor substrate.
て半導体回路の電極と電気接合をとることを特徴とする
請求項1に記載のウエハレベルCSP。2. The wafer level CSP according to claim 1, wherein the electrode is electrically connected to an electrode of a semiconductor circuit through a side surface of the through hole.
あることを特徴とする請求項2に記載のウエハレベルC
SP。3. The wafer level C according to claim 2, wherein the through hole is in a scribe line.
SP.
方法で形成された凹部をバックグラインドで裏面研削す
ることで形成されることを特徴とする請求項2に記載の
ウエハレベルCSP。4. The wafer-level CSP according to claim 2, wherein the through-hole is formed by back-grinding a concave portion formed by a method such as etching by back grinding.
が絶縁膜と金属膜の2層構造であることを特徴とする請
求項2に記載のウエハレベルCSP。5. The wafer level CSP according to claim 2, wherein a film formed on a side surface of the through hole has a two-layer structure of an insulating film and a metal film.
領域にあることを特徴とする請求項2に記載のウエハレ
ベルCSP。6. The wafer level CSP according to claim 2, wherein the through hole is in an active region of the semiconductor substrate.
方法で形成された凹部をバックグラインドで裏面研削す
ることで形成されることを特徴とする請求項2に記載の
ウエハレベルCSP。7. The wafer-level CSP according to claim 2, wherein the through-hole is formed by back-grinding a concave portion formed by a method such as etching by back grinding.
が絶縁膜と金属膜の2層構造であることを特徴とする請
求項2に記載のウエハレベルCSP。8. The wafer level CSP according to claim 2, wherein a film formed on a side surface of the through hole has a two-layer structure of an insulating film and a metal film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007059890A (en) * | 2005-07-29 | 2007-03-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of producing the same |
JP2008034704A (en) * | 2006-07-31 | 2008-02-14 | New Japan Radio Co Ltd | Manufacturing method of semiconductor device |
JP2009032754A (en) * | 2007-07-24 | 2009-02-12 | Sony Corp | Semiconductor device and manufacturing method therefor |
US7642635B2 (en) | 2003-02-28 | 2010-01-05 | Elpida Memory, Inc. | Stacked semiconductor package |
US8557699B2 (en) | 2005-07-29 | 2013-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH10135270A (en) * | 1996-10-31 | 1998-05-22 | Casio Comput Co Ltd | Semiconductor device and manufacture thereof |
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JPH10135270A (en) * | 1996-10-31 | 1998-05-22 | Casio Comput Co Ltd | Semiconductor device and manufacture thereof |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7642635B2 (en) | 2003-02-28 | 2010-01-05 | Elpida Memory, Inc. | Stacked semiconductor package |
JP2007059890A (en) * | 2005-07-29 | 2007-03-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of producing the same |
US8557699B2 (en) | 2005-07-29 | 2013-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9059098B2 (en) | 2005-07-29 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9437620B2 (en) | 2005-07-29 | 2016-09-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2008034704A (en) * | 2006-07-31 | 2008-02-14 | New Japan Radio Co Ltd | Manufacturing method of semiconductor device |
JP2009032754A (en) * | 2007-07-24 | 2009-02-12 | Sony Corp | Semiconductor device and manufacturing method therefor |
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