JP2008034704A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2008034704A
JP2008034704A JP2006208025A JP2006208025A JP2008034704A JP 2008034704 A JP2008034704 A JP 2008034704A JP 2006208025 A JP2006208025 A JP 2006208025A JP 2006208025 A JP2006208025 A JP 2006208025A JP 2008034704 A JP2008034704 A JP 2008034704A
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semiconductor device
recess
semiconductor substrate
electrode
metal
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Tatsutomo Arima
立知 有馬
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device applicable to a miniature thin semiconductor device, particularly to a compound semiconductor device of GaAs or the like. <P>SOLUTION: After a circuit element is formed on a principal surface of a semiconductor substrate, a plurality of recesses 3 are formed in an electrode formation scheduled region. A metal film 4 connected with an electrode of the circuit element and covering an inner wall of the recess is formed and the inside of the recess is filled with an electrode metal 6. Thereafter, the surface is coated with a resin layer 7. The rear surface of the semiconductor substrate is etched to expose the metal film 4. Part of the electrode metal 6 filled in the recess is left behind in the recess, and the electrode metal is cut down into individual semiconductor devices. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関し、特に小型、薄型化に適した半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for downsizing and thinning.

近年、携帯モバイル通信等の発達に伴い、フロントエンド、スイッチ、アンプなど様々な高周波デバイスが必要とされ、高周波における高速性の優れたGaAs半導体装置が多く用いられている。   In recent years, with the development of portable mobile communication and the like, various high-frequency devices such as a front end, a switch, and an amplifier are required, and GaAs semiconductor devices excellent in high-speed performance at high frequencies are often used.

同時にこの種の半導体装置では、小型、薄型化が強く求められている。小型、薄型化を実現する技術の一つに、いわゆるウエハレベルCSP(チップスケールパッケージ、あるいはチップサイズパッケージ)がある。ウエハレベルCSPは、例えば、ウエハ主面に回路素子を形成後、配線層や導電ポストを形成し、主面を樹脂封止し、裏面にバンプを形成した後、個片化することで形成することができる。最近では半導体装置をさらに薄型化するため、半導体ウエハの裏面を研磨、除去することも行われている。   At the same time, this type of semiconductor device is strongly required to be small and thin. One of the technologies for realizing a small size and a thin thickness is a so-called wafer level CSP (chip scale package or chip size package). The wafer level CSP is formed, for example, by forming circuit elements on the main surface of the wafer, forming wiring layers and conductive posts, sealing the main surface with resin, forming bumps on the back surface, and then dividing into individual pieces. be able to. Recently, in order to further reduce the thickness of a semiconductor device, the back surface of a semiconductor wafer is also polished and removed.

また、導電ポストを形成しないウエハレベルCSPの製造方法も様々提案されている。例えば特許文献1には、3次元実装用パッケージとして、半導体基板主面のチップパッドを貫通する孔を形成し、この孔に電極金属層を充填して裏面を研磨した後、露出した電極金属層にメッキバンプを形成する技術が開示されている。さらに特許文献2には、半導体基板のダイシングライン上にスルーホールを形成し、その側面を利用してウエハ表裏間を電気的に接続し、裏面側に基板実装用の電極を配置して小型化を図る技術が開示されている。このスルーホールは、ウエハのダイシングライン上をハーフエッチングして凹部を形成し、その後、半導体基板を裏面研磨することによって形成される構成となっている。
特開2006−005343号公報 特開2002−261192号公報
Various methods for manufacturing a wafer level CSP in which a conductive post is not formed have been proposed. For example, in Patent Document 1, as a three-dimensional mounting package, a hole penetrating the chip pad on the main surface of the semiconductor substrate is formed, and after filling the electrode metal layer into this hole and polishing the back surface, the exposed electrode metal layer Discloses a technique for forming plated bumps. Furthermore, in Patent Document 2, a through hole is formed on a dicing line of a semiconductor substrate, the front and back surfaces of the wafer are electrically connected using the side surface, and an electrode for mounting the substrate is disposed on the back surface side to reduce the size. A technique for achieving this is disclosed. The through-hole is formed by half-etching the dicing line of the wafer to form a recess, and then polishing the back surface of the semiconductor substrate.
JP 2006-005343 A JP 2002-261192 A

従来のウエハレベルCSPの製造方法では、半導体装置の小型、薄型化を図るため、半導体基板の裏面を研磨していた。主にシリコンからなる薄型の半導体装置では、半導体基板の厚さを50〜100μm、さらにはそれ以下まで研磨していた。このように薄い半導体基板は、非常に割れやすくなる。そのため、研磨技術も高度なものとなり、特別な設備が必要であった。一方、GaAs等の化合物半導体は、非常に割れやすく、シリコンからなる従来の製造方法に従う研磨による薄型化には、限界があった。   In the conventional wafer level CSP manufacturing method, the back surface of the semiconductor substrate is polished in order to reduce the size and thickness of the semiconductor device. In a thin semiconductor device mainly made of silicon, the thickness of the semiconductor substrate is polished to 50 to 100 μm, and even less. Such a thin semiconductor substrate is very easily broken. Therefore, the polishing technique has become sophisticated and special equipment is required. On the other hand, compound semiconductors such as GaAs are very fragile, and there is a limit to thinning by polishing according to a conventional manufacturing method made of silicon.

本発明は、通常の半導体装置の製造装置のみで、小型、薄型の半導体装置、特にGaAs等の化合物半導体装置に適用することができる半導体装置の製造方法を提供することを目的とする。   An object of the present invention is to provide a method for manufacturing a semiconductor device that can be applied to a small and thin semiconductor device, particularly a compound semiconductor device such as GaAs, using only a normal semiconductor device manufacturing apparatus.

上記目的を達成するため本願請求項1に係る発明は、半導体基板の主面に回路素子を形成する工程と、前記回路素子が形成された素子領域に隣接するダイシングラインに沿った電極形成予定領域に複数の凹部を形成する工程と、前記回路素子の電極と接続すると共に、前記凹部の内壁を被覆する金属膜を形成する工程と、前記凹部内を電極金属で充填した後、前記主面を樹脂層で被覆する工程と、前記半導体基板の別の主面をエッチングし、前記凹部の内壁を被覆する前記金属膜を露出させる工程と、前記ダイシングラインに沿い、前記凹部内に充填した前記電極金属の一部を前記凹部の側壁部に残し、前記樹脂層、前記半導体基板、前記電極金属及び前記金属膜を切断して、個々の半導体装置に個片化する工程とを含むことを特徴とする。   In order to achieve the above object, an invention according to claim 1 of the present application includes a step of forming a circuit element on a main surface of a semiconductor substrate, and an electrode formation scheduled region along a dicing line adjacent to the element region where the circuit element is formed. Forming a plurality of recesses in the substrate, connecting the electrodes of the circuit elements, forming a metal film covering the inner wall of the recesses, filling the recesses with electrode metal, and then forming the main surface A step of coating with a resin layer; a step of etching another main surface of the semiconductor substrate to expose the metal film covering the inner wall of the recess; and the electrode filled in the recess along the dicing line A step of leaving a part of the metal on the side wall of the recess, cutting the resin layer, the semiconductor substrate, the electrode metal, and the metal film into individual semiconductor devices. To do.

本願請求項2に係る発明は、請求項1記載の半導体装置の製造方法において、前記凹部の内壁を被覆する金属膜を形成すると同時に、前記ダイシングラインに沿って前記金属膜を相互に電気的に接続する導電ラインを形成する工程を含み、前記導電ラインから供給された電荷により前記凹部内に選択的に電極金属を析出させることによって、前記凹部内を前記電極金属で充填することと、前記樹脂層、前記半導体基板、前記電極金属及び前記金属膜を切断すると同時に前記導電ラインを切断することを特徴とする。   According to a second aspect of the present invention, in the method for manufacturing a semiconductor device according to the first aspect, the metal film is formed to cover the inner wall of the recess, and at the same time, the metal films are electrically connected to each other along the dicing line. Filling the inside of the recess with the electrode metal by selectively depositing an electrode metal in the recess by a charge supplied from the conductive line, and forming a conductive line to be connected; and the resin The conductive line is cut simultaneously with cutting the layer, the semiconductor substrate, the electrode metal and the metal film.

本願請求項3に係る発明は、請求項1又は2いずれか記載の半導体装置の製造方法において、前記半導体装置に個片化する工程は、少なくとも前記金属膜、前記半導体基板及び前記電極金属、あるいは更に前記導電ラインを切断すると共に、前記樹脂層の一部を切断する工程と、前記樹脂層を完全に切断する工程とからなることを特徴とする。   According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, the step of dividing into the semiconductor device includes at least the metal film, the semiconductor substrate, and the electrode metal, or The method further comprises cutting the conductive line, cutting a part of the resin layer, and cutting the resin layer completely.

本発明の製造方法では、研磨によらずエッチングによって半導体基板を薄膜化し、しかも半導体基板の主表面に樹脂層を形成した後で薄型化するため、半導体基板の割れ等の発生はない。更に本発明の製造方法は、通常の半導体装置の製造工程のみで構成されているため、歩留まり良く半導体装置を形成することができる。   In the manufacturing method of the present invention, the semiconductor substrate is thinned by etching without being polished, and further thinned after forming the resin layer on the main surface of the semiconductor substrate, so that the semiconductor substrate is not cracked. Furthermore, since the manufacturing method of the present invention includes only a normal semiconductor device manufacturing process, a semiconductor device can be formed with high yield.

本発明の製造方法によってGaAs等からなる化合物半導体装置を形成する場合、GaAs等の化合物半導体は、Siに比べて金属に対するエッチング選択性を良い。そのため電極を構成する金属を損傷させることなく、半導体基板を薄型化することができ、好適である。   When a compound semiconductor device made of GaAs or the like is formed by the manufacturing method of the present invention, a compound semiconductor such as GaAs has better etching selectivity with respect to a metal than Si. Therefore, the semiconductor substrate can be thinned without damaging the metal constituting the electrode, which is preferable.

以下、本発明の実施例について、化合物半導体のGaAsからなる半導体装置の製造方法を例に取り、詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail by taking a method of manufacturing a semiconductor device made of compound semiconductor GaAs as an example.

図1は本発明の第1の実施例の半導体装置の製造方法の説明図である。 まず、GaAsからなる半導体基板1上に、通常の半導体装置の製造方法により、回路素子を複数個形成する。図1では、回路素子が形成された1つの素子領域2を図示しており、回路素子は図示を省略している。次に、隣接する素子領域2間に配置するダイシングラインに沿って、複数の凹部3を形成する(図1a)。この凹部3は、半導体装置の電極が形成される位置に形成する。   FIG. 1 is an explanatory diagram of a method of manufacturing a semiconductor device according to the first embodiment of the present invention. First, a plurality of circuit elements are formed on a semiconductor substrate 1 made of GaAs by an ordinary semiconductor device manufacturing method. In FIG. 1, one element region 2 in which circuit elements are formed is illustrated, and the circuit elements are not illustrated. Next, a plurality of recesses 3 are formed along dicing lines arranged between adjacent element regions 2 (FIG. 1a). The recess 3 is formed at a position where the electrode of the semiconductor device is formed.

次に、通常のフォトリソグラフ法により、凹部3の内壁を被覆するように金属を蒸着し、金属膜4をパターニングする(図1b)。この金属膜4のパターニングと同時に、ダイシングラインに沿って、金属膜3を相互に電気的に接続する導電ライン5を形成する(図2)。電極膜4及び導電ライン5は、単層膜、多層膜のいずれでも良く、半導体基板1及び後述する電極金属に対して充分な接着性を有する金属を選択すればよい。一例として、金(Au)を用いることができる。   Next, a metal is vapor-deposited so that the inner wall of the recessed part 3 may be coat | covered by the normal photolithographic method, and the metal film 4 is patterned (FIG. 1b). Simultaneously with the patterning of the metal film 4, conductive lines 5 are formed along the dicing lines to electrically connect the metal films 3 to each other (FIG. 2). The electrode film 4 and the conductive line 5 may be either a single layer film or a multilayer film, and a metal having sufficient adhesion to the semiconductor substrate 1 and an electrode metal described later may be selected. As an example, gold (Au) can be used.

次に、導電ライン5に電圧を印加し、電気メッキ法により凹部3の内に電極金属6を充填する。この電極金属6は例えばAuであり、図示を省略しているが、金属膜4の一部を露出するように、フォトレジストをパターニングし、フォトレジストをマスクとして使用して、露出する金属膜4上に選択メッキを行う(図1c)。なお、先の説明で導電ライン5を形成せず、無電解メッキ法により、凹部3内に電極金属6を形成することもできる。   Next, a voltage is applied to the conductive line 5, and the electrode metal 6 is filled in the recess 3 by electroplating. The electrode metal 6 is, for example, Au and is not shown. However, the photoresist is patterned so that a part of the metal film 4 is exposed, and the exposed metal film 4 is used using the photoresist as a mask. Selective plating is performed on the top (FIG. 1c). Note that the electrode metal 6 can also be formed in the recess 3 by electroless plating without forming the conductive line 5 in the above description.

回路素子及び電極金属6等が形成された半導体基板1の主面全面を樹脂層7で被覆する(図1d)。ここで使用する樹脂は、例えば、エポキシ樹脂系で、半導体基板1にストレスがかからないようにフィラーを混入させ使用する。樹脂層7の形成方法は、ポッティング法、回転塗布法またはキャスティング法等いずれでもよい。樹脂層7を形成する前に、SiNなどの保護膜で半導体基板1全面を覆うと信頼性を確保でき、好適である。   The entire main surface of the semiconductor substrate 1 on which the circuit elements and the electrode metal 6 are formed is covered with a resin layer 7 (FIG. 1d). The resin used here is, for example, an epoxy resin system, and is used by mixing a filler so that the semiconductor substrate 1 is not stressed. The resin layer 7 may be formed by any method such as potting, spin coating, or casting. Before the resin layer 7 is formed, it is preferable that the entire surface of the semiconductor substrate 1 is covered with a protective film such as SiN because reliability can be secured.

次に半導体基板1を薄膜化する。本発明では、半導体基板1のエッチング液を用いて、図1(e)に示すように、半導体基板1の裏面(別の主面に相当)に金属膜4が露出し、電極金属6と共に、裏面側に突出するまで半導体基板1をエッチングする。なお、半導体基板1が十分に厚い場合は、所定の厚さまで半導体基板1を研磨した後、エッチングにより半導体基板1を薄くすることもできる。この場合、半導体基板1は十分な厚さがあり、また樹脂層7が半導体基板1の主面に形成されているので、研磨により割れ等が発生することは全くない。金属膜4等が裏面側に突出する寸法は、半導体基板1のエッチング量を制御することによって、適宜設定することができる。   Next, the semiconductor substrate 1 is thinned. In the present invention, the metal film 4 is exposed on the back surface (corresponding to another main surface) of the semiconductor substrate 1 using the etching solution of the semiconductor substrate 1 as shown in FIG. The semiconductor substrate 1 is etched until it protrudes to the back side. When the semiconductor substrate 1 is sufficiently thick, the semiconductor substrate 1 can be thinned by etching after the semiconductor substrate 1 is polished to a predetermined thickness. In this case, the semiconductor substrate 1 has a sufficient thickness, and since the resin layer 7 is formed on the main surface of the semiconductor substrate 1, no cracks or the like are generated by polishing. The dimension by which the metal film 4 or the like protrudes on the back side can be appropriately set by controlling the etching amount of the semiconductor substrate 1.

その後、半導体基板1の裏面側からダイシングラインに沿ってダイシングソーを走行させ、金属膜4、電極金属6、導電ライン5、半導体基板1及び樹脂層7の一部を切断し、第1の溝8を形成する(図1f)。このとき、樹脂層7が残されているため、個々の半導体装置に分離することはない。   Thereafter, a dicing saw is run along the dicing line from the back side of the semiconductor substrate 1 to cut a part of the metal film 4, the electrode metal 6, the conductive line 5, the semiconductor substrate 1 and the resin layer 7, and the first groove 8 is formed (FIG. 1f). At this time, since the resin layer 7 remains, it is not separated into individual semiconductor devices.

図3は第1の溝8を形成した後の半導体基板の裏面斜視図である。図3に示すように、第1の溝8を形成することによって、導電ライン5は除去され、また隣接する半導体装置との間に形成されている金属膜4及び電極金属6も、先に形成した凹部の側壁部に残るのみで、半導体装置毎に分離され、独立した電極となる。従って、このような状態で露出する電極金属6にプローブを接触させれば、半導体装置の特性試験を行うことができることになる。   FIG. 3 is a rear perspective view of the semiconductor substrate after the first groove 8 is formed. As shown in FIG. 3, by forming the first groove 8, the conductive line 5 is removed, and the metal film 4 and the electrode metal 6 formed between the adjacent semiconductor devices are also formed first. It remains only on the side wall of the recessed portion, and is separated for each semiconductor device and becomes an independent electrode. Therefore, if the probe is brought into contact with the electrode metal 6 exposed in such a state, the characteristic test of the semiconductor device can be performed.

最後に、樹脂層7側から第1の溝8に沿い、第1の溝8に達する深さで再びダイシングソーを走行させ、樹脂層7を完全に切断する第2の溝9を形成する(図1g)。その結果、図4に断面形状を示す半導体装置10を形成することができる。   Finally, the dicing saw runs again at a depth reaching the first groove 8 along the first groove 8 from the resin layer 7 side, thereby forming a second groove 9 that completely cuts the resin layer 7 ( FIG. 1g). As a result, the semiconductor device 10 whose cross-sectional shape is shown in FIG. 4 can be formed.

図4に示すように、本発明により形成した半導体装置10は、回路素子が形成された半導体基板1の主面は、樹脂層7で被覆され、露出する半導体基板1の裏面(別の主面)から、金属膜4及び電極金属6が突出した突起性電極(バンプ電極)が形成されている。このような構造の半導体装置10を実装基板に実装する場合、突起性電極が半導体装置の側面に露出する構造となるため、実装後のハンダ這い上がりが目視でき、実装信頼性を高めることができる。さらに、半導体基板1は、非常に薄いため放熱性が良く、特に高出力の半導体装置の特性改善が期待される。   As shown in FIG. 4, in the semiconductor device 10 formed according to the present invention, the main surface of the semiconductor substrate 1 on which the circuit elements are formed is covered with the resin layer 7, and the exposed back surface (another main surface) of the semiconductor substrate 1 is exposed. ) To form protruding electrodes (bump electrodes) from which the metal film 4 and the electrode metal 6 protrude. When the semiconductor device 10 having such a structure is mounted on the mounting substrate, the protruding electrode is exposed on the side surface of the semiconductor device, so that solder rising after mounting can be visually observed, and mounting reliability can be improved. . Furthermore, since the semiconductor substrate 1 is very thin, the heat dissipation is good, and in particular, improvement in characteristics of a high-power semiconductor device is expected.

次に第2の実施例について説明する。図5は、第1の実施例で説明した図2に相当する説明図である。第1の実施例と比較して第2の実施例は、凹部3の形状のみが異なる。すなわち、図5に凹部内部に蒸着される金属膜4aを示すように、凹部がダイシングライン側にT字状に形成されている。このように形成することにより、ダイシングソーを走行させる際や、個片化後の半導体装置を実装する際の衝撃などによって、突起性電極が凹部内から剥離することを防止することができる。従って、凹部形状は図5のようにT字状の他、台形や円などの組み合わせでもよく、アンカー効果が期待される形状を採用することができる。   Next, a second embodiment will be described. FIG. 5 is an explanatory view corresponding to FIG. 2 described in the first embodiment. Compared with the first embodiment, the second embodiment differs only in the shape of the recess 3. That is, the recess is formed in a T shape on the dicing line side as shown in FIG. By forming in this way, it is possible to prevent the protruding electrode from being peeled off from the inside of the recess due to an impact at the time of running the dicing saw or mounting the semiconductor device after separation. Accordingly, the recess shape may be a combination of trapezoids and circles in addition to the T shape as shown in FIG. 5, and a shape that is expected to have an anchor effect can be adopted.

このように凹部の形状を変更した場合であっても、前述の第1の実施例同様の製造工程により半導体装置を形成することができる。   Even when the shape of the recess is changed in this way, the semiconductor device can be formed by the same manufacturing process as in the first embodiment.

以上本発明について、GaAsからなる半導体装置の製造方法を例に取り説明したが、本発明はこれに限定されるものでないことはいうまでもない。例えば、化合物半導体としてAlGaAsやInP等を用いた半導体装置についても、同様に形成することができる。   Although the present invention has been described by taking the method of manufacturing a semiconductor device made of GaAs as an example, it goes without saying that the present invention is not limited to this. For example, a semiconductor device using AlGaAs, InP, or the like as a compound semiconductor can be formed similarly.

本発明の第1の実施例の説明図である。It is explanatory drawing of the 1st Example of this invention. 本発明の第1の実施例の途中工程の説明図である。It is explanatory drawing of the intermediate process of the 1st Example of this invention. 本発明の第1の実施例の別の途中工程の説明図である。It is explanatory drawing of another middle process of the 1st Example of this invention. 本発明により形成された半導体装置の断面図である。It is sectional drawing of the semiconductor device formed by this invention. 本発明の第2の実施例の説明図である。It is explanatory drawing of the 2nd Example of this invention.

符号の説明Explanation of symbols

1;半導体基板、2;素子領域、3;凹部、4、4a;金属膜、5;導電ライン、6;電極金属、7;樹脂層、8;第1の溝、9;第2溝、10;半導体装置
DESCRIPTION OF SYMBOLS 1; Semiconductor substrate, 2; Element area | region, 3; Concave part, 4 and 4a; Metal film, 5; Conductive line, 6: Electrode metal, 7; Resin layer, 8; ; Semiconductor device

Claims (3)

半導体基板の主面に回路素子を形成する工程と、
前記回路素子が形成された素子領域に隣接するダイシングラインに沿った電極形成予定領域に複数の凹部を形成する工程と、
前記回路素子の電極と接続すると共に、前記凹部の内壁を被覆する金属膜を形成する工程と、
前記凹部内を電極金属で充填した後、前記主面を樹脂層で被覆する工程と、
前記半導体基板の別の主面をエッチングし、前記凹部の内壁を被覆する前記金属膜を露出させる工程と、
前記ダイシングラインに沿い、前記凹部内に充填した前記電極金属の一部を前記凹部の側壁部に残し、前記樹脂層、前記半導体基板、前記電極金属及び前記金属膜を切断して、個々の半導体装置に個片化する工程とを含むことを特徴とする半導体装置の製造方法。
Forming a circuit element on the main surface of the semiconductor substrate;
Forming a plurality of recesses in an electrode formation scheduled region along a dicing line adjacent to an element region in which the circuit element is formed;
Forming a metal film that connects to the electrode of the circuit element and covers the inner wall of the recess;
After filling the recess with an electrode metal, covering the main surface with a resin layer;
Etching another main surface of the semiconductor substrate to expose the metal film covering the inner wall of the recess;
Along the dicing line, a part of the electrode metal filled in the recess is left on the side wall of the recess, and the resin layer, the semiconductor substrate, the electrode metal and the metal film are cut to form individual semiconductors. A method of manufacturing a semiconductor device, comprising the step of dividing the device into pieces.
請求項1記載の半導体装置の製造方法において、前記凹部の内壁を被覆する金属膜を形成すると同時に、前記ダイシングラインに沿って前記金属膜を相互に電気的に接続する導電ラインを形成する工程を含み、
前記導電ラインから供給される電荷により前記凹部内に選択的に電極金属を析出させることによって、前記凹部内を前記電極金属で充填することと、
前記樹脂層、前記半導体基板、前記電極金属及び前記金属膜を切断すると同時に前記導電ラインを切断することを特徴とする半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a metal film that covers an inner wall of the recess, and simultaneously forming a conductive line that electrically connects the metal film along the dicing line. Including
Filling the recess with the electrode metal by selectively depositing an electrode metal in the recess by the charge supplied from the conductive line;
A method of manufacturing a semiconductor device, comprising cutting the conductive line simultaneously with cutting the resin layer, the semiconductor substrate, the electrode metal, and the metal film.
請求項1又は2いずれか記載の半導体装置の製造方法において、前記半導体装置に個片化する工程は、少なくとも前記金属膜、前記半導体基板及び前記電極金属、あるいは更に前記導電ラインを切断すると共に、前記樹脂層の一部を切断する工程と、前記樹脂層を完全に切断する工程とからなることを特徴とする半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of separating the semiconductor device includes cutting at least the metal film, the semiconductor substrate and the electrode metal, or further the conductive line, A method for manufacturing a semiconductor device, comprising: cutting a part of the resin layer; and cutting the resin layer completely.
JP2006208025A 2006-07-31 2006-07-31 Manufacturing method of semiconductor device Pending JP2008034704A (en)

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